2015-04-09 Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>

        Backport from trunk r219578.
        2015-01-14  Joey Ye  <joey.ye@arm.com>

        * config/arm/arm.c (arm_compute_save_reg_mask):
        Do not save lr in case of tail call.
        * config/arm/thumb2.md (*thumb2_pop_single): New pattern.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@221935 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog.linaro b/gcc/ChangeLog.linaro
index 4bb4cf9..c72f812 100644 (file)
--- a/gcc/ChangeLog.linaro
+++ b/gcc/ChangeLog.linaro
@@ -1,5 +1,14 @@
 2015-04-09  Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>
 
+       Backport from trunk r219578.
+       2015-01-14  Joey Ye  <joey.ye@arm.com>
+
+       * config/arm/arm.c (arm_compute_save_reg_mask):
+       Do not save lr in case of tail call.
+       * config/arm/thumb2.md (*thumb2_pop_single): New pattern.
+
+2015-04-09  Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>
+
        Backport from trunk r219544.
        2015-01-13  Renlin Li  <renlin.li@arm.com>
 

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index b02f56d..124aaec 100644 (file)
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -19254,6 +19254,7 @@ arm_compute_save_reg_mask (void)
       || (save_reg_mask
          && optimize_size
          && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
+         && !crtl->tail_call_emit
          && !crtl->calls_eh_return))
     save_reg_mask |= 1 << LR_REGNUM;
 

diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md
index 6ea0810..2fb5548 100644 (file)
--- a/gcc/config/arm/thumb2.md
+++ b/gcc/config/arm/thumb2.md
@@ -267,6 +267,17 @@
    (set_attr "type" "multiple")]
 )
 
+;; Pop a single register as its size is preferred over a post-incremental load
+(define_insn "*thumb2_pop_single"
+  [(set (match_operand:SI 0 "low_register_operand" "=r")
+        (mem:SI (post_inc:SI (reg:SI SP_REGNUM))))]
+  "TARGET_THUMB2 && (reload_in_progress || reload_completed)"
+  "pop\t{%0}"
+  [(set_attr "type" "load1")
+   (set_attr "length" "2")
+   (set_attr "predicable" "yes")]
+)
+
 ;; We have two alternatives here for memory loads (and similarly for stores)
 ;; to reflect the fact that the permissible constant pool ranges differ
 ;; between ldr instructions taking low regs and ldr instructions taking high