Signed-off-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178021
setTargetDAGCombine(ISD::SETCC);
- setSchedulingPreference(Sched::Source);
+ setSchedulingPreference(Sched::RegPressure);
}
SDValue SITargetLowering::LowerFormalArguments(
return Reserved;
}
+unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
+ MachineFunction &MF) const {
+ return RC->getNumRegs();
+}
+
const TargetRegisterClass *
SIRegisterInfo::getISARegClass(const TargetRegisterClass * rc) const {
switch (rc->getID()) {
virtual BitVector getReservedRegs(const MachineFunction &MF) const;
+ virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
+ MachineFunction &MF) const;
+
/// \param RC is an AMDIL reg class.
///
/// \returns the SI register class that is equivalent to \p RC.