intel/isl: tile 64 calculations work with 1D surfaces

Depth/stencil surfaces cannot be linear but they can be 1D, so they
end up being tile64 when sparse (as we force every sparse resource to
be either tile64 or linear).

According to the "1D surfaces" page from BSpec, our driver treats 1D
surfaces as 2D surfaces with a height of 1 texel, since we don't
enable the corresponding bit from HAS_SLICE_CHICKEN7. And since we
support 2D surfaces, we should also support 1D.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22974>

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 2960c9a..9175f3c 100644 (file)
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -494,8 +494,8 @@ isl_tiling_get_info(enum isl_tiling tiling,
 #define tile_extent(bs, cv, cu, a) \
       isl_extent4d((1 << cu) / bs, 1 << cv, 1, a)
 
-      /* Only 2D surfaces are handled. */
-      assert(dim == ISL_SURF_DIM_2D);
+      /* Only 1D and 2D surfaces are handled. */
+      assert(dim != ISL_SURF_DIM_3D);
 
       if (samples == 1 || msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED) {
          switch (format_bpb) {

diff --git a/src/intel/isl/isl_gfx12.c b/src/intel/isl/isl_gfx12.c
index 79d89c9..215e901 100644 (file)
--- a/src/intel/isl/isl_gfx12.c
+++ b/src/intel/isl/isl_gfx12.c
@@ -70,8 +70,8 @@ isl_gfx125_filter_tiling(const struct isl_device *dev,
    if (info->dim != ISL_SURF_DIM_2D)
       *flags &= ~ISL_TILING_X_BIT;
 
-   /* ISL only implements Tile64 support for 2D surfaces. */
-   if (info->dim != ISL_SURF_DIM_2D)
+   /* ISL only implements Tile64 support for 1D and 2D surfaces. */
+   if (info->dim == ISL_SURF_DIM_3D)
       *flags &= ~ISL_TILING_64_BIT;
 
    /* TILE64 does not work with YCRCB formats, according to bspec 58767: