{
/* Find the highest supported frequency <= rate and switch to it */
struct mpu_rate * ptr;
- unsigned long dpll1_rate, ref_rate;
+ unsigned long ref_rate;
- dpll1_rate = ck_dpll1_p->rate;
ref_rate = ck_ref_p->rate;
for (ptr = omap1_rate_table; ptr->rate; ptr++) {
void *cb_data;
int active;
- unsigned long addr, size;
+ unsigned long addr;
int rotate, data_type, xres, yres;
int vxres;
int mirror;
static void omap_pm_init_proc(void)
{
- struct proc_dir_entry *entry;
-
- entry = create_proc_read_entry("driver/omap_pm",
- S_IWUSR | S_IRUGO, NULL,
- omap_pm_read_proc, NULL);
+ /* XXX Appears to leak memory */
+ create_proc_read_entry("driver/omap_pm",
+ S_IWUSR | S_IRUGO, NULL,
+ omap_pm_read_proc, NULL);
}
#endif /* DEBUG && CONFIG_PROC_FS */
static void am35xx_enable_emac_int(void)
{
- u32 regval;
-
- regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
- regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR |
- AM35XX_CPGMAC_C0_TX_PULSE_CLR |
- AM35XX_CPGMAC_C0_MISC_PULSE_CLR |
- AM35XX_CPGMAC_C0_RX_THRESH_CLR);
- omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
- regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+ u32 v;
+
+ v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+ v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR |
+ AM35XX_CPGMAC_C0_MISC_PULSE_CLR | AM35XX_CPGMAC_C0_RX_THRESH_CLR);
+ omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
+ omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
}
static void am35xx_disable_emac_int(void)
{
- u32 regval;
+ u32 v;
- regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
- regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR |
- AM35XX_CPGMAC_C0_TX_PULSE_CLR);
- omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
- regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+ v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+ v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR);
+ omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
+ omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
}
static struct emac_platform_data am35xx_emac_pdata = {
void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en)
{
- unsigned int regval;
+ u32 v;
int err;
am35xx_emac_pdata.rmii_en = rmii_en;
return;
}
- regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
- regval = regval & (~(AM35XX_CPGMACSS_SW_RST));
- omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
- regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
+ v = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
+ v &= ~AM35XX_CPGMACSS_SW_RST;
+ omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET);
+ omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */
}
static void __init omap3_evm_init(void)
{
+ struct omap_board_mux *obm;
+
omap3_evm_get_revision();
regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
- if (cpu_is_omap3630())
- omap3_mux_init(omap36x_board_mux, OMAP_PACKAGE_CBB);
- else
- omap3_mux_init(omap35x_board_mux, OMAP_PACKAGE_CBB);
+ obm = (cpu_is_omap3630()) ? omap36x_board_mux : omap35x_board_mux;
+ omap3_mux_init(obm, OMAP_PACKAGE_CBB);
omap_board_config = omap3_evm_config;
omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
static int __init omap3_l3_init(void)
{
- int l;
struct omap_hwmod *oh;
struct platform_device *pdev;
char oh_name[L3_MODULES_MAX_LEN];
if (!(cpu_is_omap34xx()))
return -ENODEV;
- l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
+ snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
oh = omap_hwmod_lookup(oh_name);
static int __init omap4_l3_init(void)
{
- int l, i;
+ int i;
struct omap_hwmod *oh[3];
struct platform_device *pdev;
char oh_name[L3_MODULES_MAX_LEN];
return -ENODEV;
for (i = 0; i < L3_MODULES; i++) {
- l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
+ snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
oh[i] = omap_hwmod_lookup(oh_name);
if (!(oh[i]))
pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1);
pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL);
- if (!pdata) {
+ if (!pdata->regs) {
pr_err("gpio%d: Memory allocation failed\n", id);
return -ENOMEM;
}
const int t_wpl = 40;
const int t_wph = 30;
int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
- int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
+ int div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
int err, ticks_cez;
int cs = cfg->cs, freq = *freq_ptr;
break;
}
- tick_ns = gpmc_ticks_to_ns(1);
div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period);
gpmc_clk_ns = gpmc_ticks_to_ns(div);
if (gpmc_clk_ns < 15) /* >66Mhz */
int mux_mode;
mux_mode = omap_mux_get_by_name(muxname, &partition, &mux);
- if (mux_mode < 0)
+ if (mux_mode < 0 || !mux)
return mux_mode;
old_mode = omap_mux_read(partition, mux->reg_offset);
static void omap2_enter_mpu_retention(void)
{
- int only_idle = 0;
-
/* Putting MPU into the WFI state while a transfer is active
* seems to cause the I2C block to timeout. Why? Good question. */
if (omap2_i2c_active())
omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
OMAP2_PM_PWSTCTRL);
- only_idle = 1;
}
omap2_sram_idle();
int per_next_state = PWRDM_POWER_ON;
int core_next_state = PWRDM_POWER_ON;
int per_going_off;
- int core_prev_state, per_prev_state;
+ int core_prev_state;
u32 sdrc_pwr = 0;
mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
pwrdm_post_transition();
/* PER */
- if (per_next_state < PWRDM_POWER_ON) {
- per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
+ if (per_next_state < PWRDM_POWER_ON)
omap2_gpio_resume_after_idle();
- }
/* Disable IO-PAD and IO-CHAIN wakeup */
if (omap3_has_io_wakeup() &&
static int __init omap3_pm_init(void)
{
struct power_state *pwrst, *tmp;
- struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
+ struct clockdomain *neon_clkdm, *mpu_clkdm;
int ret;
if (!cpu_is_omap34xx())
neon_clkdm = clkdm_lookup("neon_clkdm");
mpu_clkdm = clkdm_lookup("mpu_clkdm");
- per_clkdm = clkdm_lookup("per_clkdm");
- core_clkdm = clkdm_lookup("core_clkdm");
#ifdef CONFIG_SUSPEND
omap_pm_suspend = omap3_pm_suspend;
*/
int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
{
- int nr_regs = irq_setup->nr_regs;
+ int nr_regs;
u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
int offset, i;
struct irq_chip_generic *gc;
if (!irq_setup)
return -EINVAL;
+ nr_regs = irq_setup->nr_regs;
+
if (prcm_irq_setup) {
pr_err("PRCM: already initialized; won't reinitialize\n");
return -EINVAL;
tmp = (t.sync_clk + fclk_ps - 1) / fclk_ps;
if (tmp > 4)
return -ERANGE;
- if (tmp <= 0)
+ if (tmp == 0)
tmp = 1;
t.page_burst_access = (fclk_ps * tmp) / 1000;
int omap_dm_timer_stop(struct omap_dm_timer *timer)
{
unsigned long rate = 0;
- struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
+ struct dmtimer_platform_data *pdata;
if (unlikely(!timer))
return -EINVAL;
+ pdata = timer->pdev->dev.platform_data;
if (!pdata->needs_manual_reset)
rate = clk_get_rate(timer->fclk);
static int omap_device_fill_resources(struct omap_device *od,
struct resource *res)
{
- int c = 0;
int i, r;
for (i = 0; i < od->hwmods_cnt; i++) {
r = omap_hwmod_fill_resources(od->hwmods[i], res);
res += r;
- c += r;
}
return 0;
#endif
pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
omap_writel(syscon, OTG_SYSCON_1);
-
- status = 0;
}
#else