ppc/85xx: Ensure that MAS8 is zero when writing TLB entries.

Its reset value is random, and we sometimes read uninitialized TLB
arrays.  Make sure that we don't retain MAS8 from reading such an entry
if the VF bit in MAS8 is set, attempts to use the mapping will trap.

Signed-off-by: Scott Wood <scottwood@freescale.com>

diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index eaed0e0be5f5077a42abf804c54a28eb874f8310..7a23b4f811dacd7d205c76301d4ca4398dd98731 100644 (file)
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -156,6 +156,10 @@ _start_e500:
        mtspr   MCSR,r0                 /* machine check syndrome register */
        mtxer   r0                      /* clear integer exception register */
 
+#ifdef CONFIG_SYS_BOOK3E_HV
+       mtspr   MAS8,r0                 /* make sure MAS8 is clear */
+#endif
+
        /* Enable Time Base and Select Time Base Clock */
        lis     r0,HID0_EMCP@h          /* Enable machine check */
 #if defined(CONFIG_ENABLE_36BIT_PHYS)

diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c
index 0497a29ba83f78e91385d03f8f3650a35bbf7764..03c2449b5c3c4c999074684db5b2bee43c0a179f 100644 (file)
--- a/cpu/mpc85xx/tlb.c
+++ b/cpu/mpc85xx/tlb.c
@@ -50,6 +50,9 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn,
        mtspr(MAS3, _mas3);
 #ifdef CONFIG_ENABLE_36BIT_PHYS
        mtspr(MAS7, _mas7);
+#endif
+#ifdef CONFIG_SYS_BOOK3E_HV
+       mtspr(MAS8, 0);
 #endif
        asm volatile("isync;msync;tlbwe;isync");
 

diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 0a4c66c9d9e6643ede70f9dab33dce6b0909f01a..3764a5a51d53955da0290df0dee35c12980a19bd 100644 (file)
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -518,6 +518,7 @@
 #define SPRN_MAS5      0x275   /* MMU Assist Register 5 */
 #define SPRN_MAS6      0x276   /* MMU Assist Register 6 */
 #define SPRN_MAS7      0x3B0   /* MMU Assist Register 7 */
+#define SPRN_MAS8      0x155   /* MMU Assist Register 8 */
 
 #define SPRN_IVOR32    0x210   /* Interrupt Vector Offset Register 32 */
 #define SPRN_IVOR33    0x211   /* Interrupt Vector Offset Register 33 */
@@ -720,6 +721,7 @@
 #define MAS5   SPRN_MAS5
 #define MAS6   SPRN_MAS6
 #define MAS7   SPRN_MAS7
+#define MAS8   SPRN_MAS8
 
 #if defined(CONFIG_4xx) || defined(CONFIG_44x) || defined(CONFIG_MPC85xx)
 #define DAR_DEAR DEAR