drm/amd/display: Move LTTPR cap read into its own function

[WHY]
We want LTTPR capabilities to be readable from more places than just
retrieve_link_cap

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 0e2741c..38fabaf 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -3619,47 +3619,16 @@ static bool dpcd_read_sink_ext_caps(struct dc_link *link)
        return true;
 }
 
-static bool retrieve_link_cap(struct dc_link *link)
+bool dp_retrieve_lttpr_cap(struct dc_link *link)
 {
-       /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
-        * which means size 16 will be good for both of those DPCD register block reads
-        */
-       uint8_t dpcd_data[16];
        uint8_t lttpr_dpcd_data[6];
-
-       /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
-        */
-       uint8_t dpcd_dprx_data = '\0';
-       uint8_t dpcd_power_state = '\0';
-
-       struct dp_device_vendor_id sink_id;
-       union down_stream_port_count down_strm_port_count;
-       union edp_configuration_cap edp_config_cap;
-       union dp_downstream_port_present ds_port = { 0 };
-       enum dc_status status = DC_ERROR_UNEXPECTED;
-       uint32_t read_dpcd_retry_cnt = 3;
-       int i;
-       struct dp_sink_hw_fw_revision dp_hw_fw_revision;
-       bool is_lttpr_present = false;
-       const uint32_t post_oui_delay = 30; // 30ms
        bool vbios_lttpr_enable = false;
        bool vbios_lttpr_interop = false;
        struct dc_bios *bios = link->dc->ctx->dc_bios;
+       enum dc_status status = DC_ERROR_UNEXPECTED;
+       bool is_lttpr_present = false;
 
-       memset(dpcd_data, '\0', sizeof(dpcd_data));
        memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
-       memset(&down_strm_port_count,
-               '\0', sizeof(union down_stream_port_count));
-       memset(&edp_config_cap, '\0',
-               sizeof(union edp_configuration_cap));
-
-       /* if extended timeout is supported in hardware,
-        * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
-        * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
-        */
-       dc_link_aux_try_to_configure_timeout(link->ddc,
-                       LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
-
        /* Query BIOS to determine if LTTPR functionality is forced on by system */
        if (bios->funcs->get_lttpr_caps) {
                enum bp_result bp_query_result;
@@ -3741,7 +3710,45 @@ static bool retrieve_link_cap(struct dc_link *link)
                else
                        link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
        }
+       return is_lttpr_present;
+}
+
+static bool retrieve_link_cap(struct dc_link *link)
+{
+       /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
+        * which means size 16 will be good for both of those DPCD register block reads
+        */
+       uint8_t dpcd_data[16];
+       /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
+        */
+       uint8_t dpcd_dprx_data = '\0';
+       uint8_t dpcd_power_state = '\0';
+
+       struct dp_device_vendor_id sink_id;
+       union down_stream_port_count down_strm_port_count;
+       union edp_configuration_cap edp_config_cap;
+       union dp_downstream_port_present ds_port = { 0 };
+       enum dc_status status = DC_ERROR_UNEXPECTED;
+       uint32_t read_dpcd_retry_cnt = 3;
+       int i;
+       struct dp_sink_hw_fw_revision dp_hw_fw_revision;
+       const uint32_t post_oui_delay = 30; // 30ms
+       bool is_lttpr_present = false;
+
+       memset(dpcd_data, '\0', sizeof(dpcd_data));
+       memset(&down_strm_port_count,
+               '\0', sizeof(union down_stream_port_count));
+       memset(&edp_config_cap, '\0',
+               sizeof(union edp_configuration_cap));
+
+       /* if extended timeout is supported in hardware,
+        * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
+        * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
+        */
+       dc_link_aux_try_to_configure_timeout(link->ddc,
+                       LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
 
+       is_lttpr_present = dp_retrieve_lttpr_cap(link);
        if (!is_lttpr_present)
                dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);