[mlir] Initial MLIR VP intrinsic integration test on host and RVV emulator.

This patch adds the initial VP intrinsic integration test on the host backend and RVV emulator. Please see more detailed [discussion on the discourse](https://discourse.llvm.org/t/mlir-vp-ops-on-rvv-backend-integration-test-and-issues-report/66343).

- Run the test cases on the host by configuring the CMake option: `-DMLIR_INCLUDE_INTEGRATION_TESTS=ON`
- Build the RVV environment and run the test cases on RVV QEMU by [this doc](https://gist.github.com/zhanghb97/ad44407e169de298911b8a4235e68497).

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D137816

diff --git a/mlir/test/Integration/Dialect/LLVMIR/CPU/lit.local.cfg b/mlir/test/Integration/Dialect/LLVMIR/CPU/lit.local.cfg
index 83247d7..f5c79f3 100644 (file)
--- a/mlir/test/Integration/Dialect/LLVMIR/CPU/lit.local.cfg
+++ b/mlir/test/Integration/Dialect/LLVMIR/CPU/lit.local.cfg
@@ -3,3 +3,20 @@ import sys
 # No JIT on win32.
 if sys.platform == 'win32':
     config.unsupported = True
+
+lli_cmd = 'lli'
+if config.riscv_emulator_lli_executable:
+    lli_cmd = config.riscv_emulator_lli_executable
+
+config.substitutions.append(('%mlir_native_utils_lib_dir',
+    config.riscv_emulator_utils_lib_dir or config.mlir_lib_dir))
+
+if config.riscv_vector_emulator_executable:
+    # Run test in qemu emulator.
+    emulation_cmd = config.riscv_vector_emulator_executable
+    if config.riscv_vector_emulator_options:
+        emulation_cmd = emulation_cmd + ' ' + config.riscv_vector_emulator_options
+    emulation_cmd = emulation_cmd + ' ' + lli_cmd + ' --march=riscv64 -mattr=+v '
+    config.substitutions.append(('%lli', emulation_cmd))
+else:
+    config.substitutions.append(('%lli', lli_cmd))

diff --git a/mlir/test/Integration/Dialect/LLVMIR/CPU/test-vp-intrinsic.mlir b/mlir/test/Integration/Dialect/LLVMIR/CPU/test-vp-intrinsic.mlir
new file mode 100644 (file)
index 0000000..e8e5ef3
--- /dev/null
+++ b/mlir/test/Integration/Dialect/LLVMIR/CPU/test-vp-intrinsic.mlir
@@ -0,0 +1,32 @@
+// RUN: mlir-opt %s -convert-vector-to-llvm -convert-memref-to-llvm \
+// RUN:             -convert-func-to-llvm -reconcile-unrealized-casts | \
+// RUN: mlir-translate -mlir-to-llvmir | \
+// RUN: %lli --entry-function=entry \
+// RUN:      --dlopen=%mlir_native_utils_lib_dir/libmlir_c_runner_utils%shlibext | \
+// RUN: FileCheck %s
+
+memref.global "private" @gv_i32 : memref<20xi32> =
+    dense<[0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
+           10, 11, 12, 13, 14, 15, 16, 17, 18, 19]>
+
+func.func @entry() -> i32 {
+  %c0 = arith.constant 0 : index
+  %c10 = arith.constant 10 : index
+  %mem_i32 = memref.get_global @gv_i32 : memref<20xi32>
+  // When the vectors are defined as dense constant vector,
+  // the vp intrinsic will be optimized/eliminated on some backend (e.g. X86).
+  // So this test case loads the vector from a memref to test the vp intrinsic
+  // backend support.
+  %vec1 = vector.load %mem_i32[%c0] : memref<20xi32>, vector<8xi32>
+  %vec2 = vector.load %mem_i32[%c10] : memref<20xi32>, vector<8xi32>
+  %mask = arith.constant dense<[1, 0, 1, 0, 1, 0, 1, 0]> : vector<8xi1>
+  %evl = arith.constant 4 : i32
+
+  %res = "llvm.intr.vp.add" (%vec1, %vec2, %mask, %evl) :
+         (vector<8xi32>, vector<8xi32>, vector<8xi1>, i32) -> vector<8xi32>
+  vector.print %res : vector<8xi32>
+  // CHECK: ( 10, {{.*}}, 14, {{.*}}, {{.*}}, {{.*}}, {{.*}}, {{.*}} )
+
+  %ret = arith.constant 0 : i32
+  return %ret : i32
+}

diff --git a/mlir/test/lit.site.cfg.py.in b/mlir/test/lit.site.cfg.py.in
index 5bca43b..e0826e0 100644 (file)
--- a/mlir/test/lit.site.cfg.py.in
+++ b/mlir/test/lit.site.cfg.py.in
@@ -36,12 +36,17 @@ config.intel_sde_executable = "@INTEL_SDE_EXECUTABLE@"
 config.mlir_run_amx_tests = @MLIR_RUN_AMX_TESTS@
 config.mlir_run_arm_sve_tests = @MLIR_RUN_ARM_SVE_TESTS@
 config.mlir_run_x86vector_tests = @MLIR_RUN_X86VECTOR_TESTS@
+config.mlir_run_riscv_vector_tests = "@MLIR_RUN_RISCV_VECTOR_TESTS@"
 config.mlir_run_cuda_tensor_core_tests = @MLIR_RUN_CUDA_TENSOR_CORE_TESTS@
 config.mlir_include_integration_tests = @MLIR_INCLUDE_INTEGRATION_TESTS@
 config.arm_emulator_executable = "@ARM_EMULATOR_EXECUTABLE@"
 config.arm_emulator_options = "@ARM_EMULATOR_OPTIONS@"
 config.arm_emulator_lli_executable = "@ARM_EMULATOR_LLI_EXECUTABLE@"
 config.arm_emulator_utils_lib_dir = "@ARM_EMULATOR_UTILS_LIB_DIR@"
+config.riscv_vector_emulator_executable = "@RISCV_VECTOR_EMULATOR_EXECUTABLE@"
+config.riscv_vector_emulator_options = "@RISCV_VECTOR_EMULATOR_OPTIONS@"
+config.riscv_emulator_lli_executable = "@RISCV_EMULATOR_LLI_EXECUTABLE@"
+config.riscv_emulator_utils_lib_dir = "@RISCV_EMULATOR_UTILS_LIB_DIR@"
 
 import lit.llvm
 lit.llvm.initialize(lit_config, config)