+2014-09-03 Jiong Wang <jiong.wang@arm.com>
+
+ * config/tc-aarch64.c (parse_operands): Recognize PAIRREG.
+ (aarch64_features): Add entry for lse extension.
+
2014-08-26 Jiong Wang <jiong.wang@arm.com>
* config/tc-arm.c (aeabi_set_public_attributes): Update selected_cpu
case AARCH64_OPND_Rs:
case AARCH64_OPND_Ra:
case AARCH64_OPND_Rt_SYS:
+ case AARCH64_OPND_PAIRREG:
po_int_reg_or_fail (1, 0);
break;
{"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0)},
{"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0)},
{"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)},
+ {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0)},
{"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
{NULL, AARCH64_ARCH_NONE}
};
+2014-09-03 Jiong Wang <jiong.wang@arm.com>
+
+ * gas/aarch64/lse-atomic.d: New.
+ * gas/aarch64/lse-atomic.s: Likewise.
+ * gas/aarch64/illegal-lse.d: Likewise.
+ * gas/aarch64/illegal-lse.l: Likewise.
+ * gas/aarch64/illegal-lse.s: Likewise.
+ * gas/aarch64/diagnostic.s: Check processor feature detect for lse
+ instruction.
+ * gas/aarch64/diagnostic.l: Likewise.
+
2014-08-26 Jiong Wang <jiong.wang@arm.com>
* gas/arm/blx-bl-convert.d: New testcase.
[^:]*:108: Error: constant expression required at operand 1 -- `clrex kk'
[^:]*:109: Error: operand 5 should be an integer register -- `sys #0,c0,c0,#0,kk'
[^:]*:110: Error: unexpected comma before the omitted optional operand at operand 5 -- `sys #0,c0,c0,#0,'
+[^:]*:112: Error: selected processor does not support `casp w0,w1,w2,w3,\[x4\]'
clrex kk
sys #0, c0, c0, #0, kk
sys #0, c0, c0, #0,
+
+ casp w0,w1,w2,w3,[x4]
--- /dev/null
+#name: LSE Illegal Instruction Operands
+#source: illegal-lse.s
+#as: -march=armv8-a+lse -mno-verbose-error
+#error-output: illegal-lse.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:68: Error: operand mismatch -- `cas w0,x1,\[x2\]'
+[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `cas w2,w3,\[w4\]'
+[^:]*:68: Error: operand mismatch -- `casa w0,x1,\[x2\]'
+[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casa w2,w3,\[w4\]'
+[^:]*:68: Error: operand mismatch -- `casl w0,x1,\[x2\]'
+[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casl w2,w3,\[w4\]'
+[^:]*:68: Error: operand mismatch -- `casal w0,x1,\[x2\]'
+[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casal w2,w3,\[w4\]'
+[^:]*:68: Error: operand mismatch -- `casb w0,x1,\[x2\]'
+[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casb w2,w3,\[w4\]'
+[^:]*:68: Error: operand mismatch -- `cash w0,x1,\[x2\]'
+[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `cash w2,w3,\[w4\]'
+[^:]*:68: Error: operand mismatch -- `casab w0,x1,\[x2\]'
+[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casab w2,w3,\[w4\]'
+[^:]*:68: Error: operand mismatch -- `caslb w0,x1,\[x2\]'
+[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `caslb w2,w3,\[w4\]'
+[^:]*:68: Error: operand mismatch -- `casalb w0,x1,\[x2\]'
+[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casalb w2,w3,\[w4\]'
+[^:]*:68: Error: operand mismatch -- `casah w0,x1,\[x2\]'
+[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casah w2,w3,\[w4\]'
+[^:]*:68: Error: operand mismatch -- `caslh w0,x1,\[x2\]'
+[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `caslh w2,w3,\[w4\]'
+[^:]*:68: Error: operand mismatch -- `casalh w0,x1,\[x2\]'
+[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casalh w2,w3,\[w4\]'
+[^:]*:68: Error: operand mismatch -- `cas w0,x1,\[x2\]'
+[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `cas x2,x3,\[w4\]'
+[^:]*:68: Error: operand mismatch -- `casa w0,x1,\[x2\]'
+[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casa x2,x3,\[w4\]'
+[^:]*:68: Error: operand mismatch -- `casl w0,x1,\[x2\]'
+[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casl x2,x3,\[w4\]'
+[^:]*:68: Error: operand mismatch -- `casal w0,x1,\[x2\]'
+[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casal x2,x3,\[w4\]'
+[^:]*:69: Error: operand mismatch -- `swp w0,x1,\[x2\]'
+[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swp w2,w3,\[w4\]'
+[^:]*:69: Error: operand mismatch -- `swpa w0,x1,\[x2\]'
+[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpa w2,w3,\[w4\]'
+[^:]*:69: Error: operand mismatch -- `swpl w0,x1,\[x2\]'
+[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpl w2,w3,\[w4\]'
+[^:]*:69: Error: operand mismatch -- `swpal w0,x1,\[x2\]'
+[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpal w2,w3,\[w4\]'
+[^:]*:69: Error: operand mismatch -- `swpb w0,x1,\[x2\]'
+[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpb w2,w3,\[w4\]'
+[^:]*:69: Error: operand mismatch -- `swph w0,x1,\[x2\]'
+[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swph w2,w3,\[w4\]'
+[^:]*:69: Error: operand mismatch -- `swpab w0,x1,\[x2\]'
+[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpab w2,w3,\[w4\]'
+[^:]*:69: Error: operand mismatch -- `swplb w0,x1,\[x2\]'
+[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swplb w2,w3,\[w4\]'
+[^:]*:69: Error: operand mismatch -- `swpalb w0,x1,\[x2\]'
+[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpalb w2,w3,\[w4\]'
+[^:]*:69: Error: operand mismatch -- `swpah w0,x1,\[x2\]'
+[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpah w2,w3,\[w4\]'
+[^:]*:69: Error: operand mismatch -- `swplh w0,x1,\[x2\]'
+[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swplh w2,w3,\[w4\]'
+[^:]*:69: Error: operand mismatch -- `swpalh w0,x1,\[x2\]'
+[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpalh w2,w3,\[w4\]'
+[^:]*:69: Error: operand mismatch -- `swp w0,x1,\[x2\]'
+[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swp x2,x3,\[w4\]'
+[^:]*:69: Error: operand mismatch -- `swpa w0,x1,\[x2\]'
+[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpa x2,x3,\[w4\]'
+[^:]*:69: Error: operand mismatch -- `swpl w0,x1,\[x2\]'
+[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpl x2,x3,\[w4\]'
+[^:]*:69: Error: operand mismatch -- `swpal w0,x1,\[x2\]'
+[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpal x2,x3,\[w4\]'
+[^:]*:70: Error: reg pair must start from even reg at operand 1 -- `casp w1,w1,w2,w3,\[x5\]'
+[^:]*:70: Error: reg pair must be contiguous at operand 2 -- `casp w4,w4,w6,w7,\[sp\]'
+[^:]*:70: Error: operand mismatch -- `casp w0,x1,x2,x3,\[x2\]'
+[^:]*:70: Error: operand 5 should be an address with base register \(no offset\) -- `casp x4,x5,x6,x7,\[w8\]'
+[^:]*:70: Error: reg pair must start from even reg at operand 1 -- `caspa w1,w1,w2,w3,\[x5\]'
+[^:]*:70: Error: reg pair must be contiguous at operand 2 -- `caspa w4,w4,w6,w7,\[sp\]'
+[^:]*:70: Error: operand mismatch -- `caspa w0,x1,x2,x3,\[x2\]'
+[^:]*:70: Error: operand 5 should be an address with base register \(no offset\) -- `caspa x4,x5,x6,x7,\[w8\]'
+[^:]*:70: Error: reg pair must start from even reg at operand 1 -- `caspl w1,w1,w2,w3,\[x5\]'
+[^:]*:70: Error: reg pair must be contiguous at operand 2 -- `caspl w4,w4,w6,w7,\[sp\]'
+[^:]*:70: Error: operand mismatch -- `caspl w0,x1,x2,x3,\[x2\]'
+[^:]*:70: Error: operand 5 should be an address with base register \(no offset\) -- `caspl x4,x5,x6,x7,\[w8\]'
+[^:]*:70: Error: reg pair must start from even reg at operand 1 -- `caspal w1,w1,w2,w3,\[x5\]'
+[^:]*:70: Error: reg pair must be contiguous at operand 2 -- `caspal w4,w4,w6,w7,\[sp\]'
+[^:]*:70: Error: operand mismatch -- `caspal w0,x1,x2,x3,\[x2\]'
+[^:]*:70: Error: operand 5 should be an address with base register \(no offset\) -- `caspal x4,x5,x6,x7,\[w8\]'
+[^:]*:71: Error: operand mismatch -- `ldadd w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldadd w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldadda w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldadda w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldaddl w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddl w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldaddal w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddal w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldaddb w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddb w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldaddh w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddh w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldaddab w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddab w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldaddlb w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddlb w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldaddalb w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddalb w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldaddah w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddah w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldaddlh w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddlh w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldaddalh w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddalh w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldadd w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldadd x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldadda w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldadda x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldaddl w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddl x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldaddal w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddal x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldclr w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclr w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldclra w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclra w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldclrl w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclrl w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldclral w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclral w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldclrb w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclrb w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldclrh w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclrh w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldclrab w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclrab w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldclrlb w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclrlb w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldclralb w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclralb w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldclrah w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclrah w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldclrlh w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclrlh w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldclralh w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclralh w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldclr w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclr x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldclra w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclra x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldclrl w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclrl x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldclral w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclral x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldeor w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeor w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldeora w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeora w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldeorl w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeorl w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldeoral w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeoral w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldeorb w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeorb w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldeorh w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeorh w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldeorab w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeorab w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldeorlb w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeorlb w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldeoralb w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeoralb w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldeorah w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeorah w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldeorlh w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeorlh w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldeoralh w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeoralh w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldeor w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeor x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldeora w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeora x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldeorl w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeorl x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldeoral w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeoral x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldset w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldset w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldseta w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldseta w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsetl w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetl w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsetal w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetal w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsetb w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetb w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldseth w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldseth w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsetab w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetab w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsetlb w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetlb w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsetalb w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetalb w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsetah w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetah w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsetlh w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetlh w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsetalh w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetalh w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldset w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldset x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldseta w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldseta x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsetl w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetl x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsetal w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetal x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsmax w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmax w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsmaxa w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxa w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsmaxl w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxl w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsmaxal w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxal w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsmaxb w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxb w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsmaxh w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxh w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsmaxab w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxab w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsmaxlb w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxlb w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsmaxalb w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxalb w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsmaxah w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxah w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsmaxlh w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxlh w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsmaxalh w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxalh w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsmax w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmax x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsmaxa w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxa x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsmaxl w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxl x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsmaxal w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxal x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsmin w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmin w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsmina w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmina w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsminl w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminl w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsminal w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminal w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsminb w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminb w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsminh w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminh w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsminab w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminab w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsminlb w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminlb w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsminalb w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminalb w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsminah w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminah w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsminlh w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminlh w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsminalh w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminalh w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsmin w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmin x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsmina w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmina x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsminl w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminl x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldsminal w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminal x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldumax w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumax w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldumaxa w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxa w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldumaxl w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxl w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldumaxal w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxal w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldumaxb w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxb w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldumaxh w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxh w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldumaxab w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxab w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldumaxlb w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxlb w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldumaxalb w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxalb w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldumaxah w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxah w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldumaxlh w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxlh w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldumaxalh w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxalh w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldumax w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumax x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldumaxa w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxa x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldumaxl w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxl x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldumaxal w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxal x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldumin w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumin w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldumina w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumina w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `lduminl w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminl w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `lduminal w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminal w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `lduminb w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminb w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `lduminh w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminh w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `lduminab w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminab w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `lduminlb w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminlb w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `lduminalb w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminalb w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `lduminah w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminah w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `lduminlh w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminlh w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `lduminalh w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminalh w2,w3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldumin w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumin x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `ldumina w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumina x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `lduminl w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminl x2,x3,\[w4\]'
+[^:]*:71: Error: operand mismatch -- `lduminal w0,x1,\[x2\]'
+[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminal x2,x3,\[w4\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stadd w2,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `staddl w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `staddb x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `staddb w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `staddh x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `staddh w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `staddlb x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `staddlb w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `staddlh x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `staddlh w2,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stadd x0,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `staddl x0,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stclr w2,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stclrl w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `stclrb x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stclrb w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `stclrh x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stclrh w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `stclrlb x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stclrlb w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `stclrlh x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stclrlh w2,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stclr x0,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stclrl x0,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `steor w2,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `steorl w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `steorb x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `steorb w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `steorh x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `steorh w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `steorlb x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `steorlb w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `steorlh x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `steorlh w2,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `steor x0,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `steorl x0,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stset w2,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsetl w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `stsetb x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsetb w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `stseth x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stseth w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `stsetlb x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsetlb w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `stsetlh x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsetlh w2,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stset x0,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsetl x0,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmax w2,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmaxl w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `stsmaxb x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmaxb w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `stsmaxh x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmaxh w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `stsmaxlb x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmaxlb w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `stsmaxlh x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmaxlh w2,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmax x0,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmaxl x0,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmin w2,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsminl w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `stsminb x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsminb w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `stsminh x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsminh w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `stsminlb x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsminlb w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `stsminlh x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsminlh w2,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmin x0,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsminl x0,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumax w2,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumaxl w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `stumaxb x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumaxb w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `stumaxh x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumaxh w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `stumaxlb x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumaxlb w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `stumaxlh x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumaxlh w2,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumax x0,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumaxl x0,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumin w2,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stuminl w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `stuminb x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stuminb w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `stuminh x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stuminh w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `stuminlb x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stuminlb w2,\[w3\]'
+[^:]*:72: Error: operand mismatch -- `stuminlh x0,\[x2\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stuminlh w2,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumin x0,\[w3\]'
+[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stuminl x0,\[w3\]'
--- /dev/null
+/* illegal-lse.s Test file For AArch64 LSE atomic instructions that
+ could be rejected by the assembler.
+
+ Copyright 2014 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+
+ .macro format_0_check op
+ .irp suffix, , a, l, al, b, h, ab, lb, alb, ah, lh, alh
+ \op\suffix w0, x1, [x2]
+ \op\suffix w2, w3, [w4]
+ .endr
+ .irp suffix, , a, l, al
+ \op\suffix w0, x1, [x2]
+ \op\suffix x2, x3, [w4]
+ .endr
+ .endm
+
+ .macro format_0_no_rt_no_acquire_check op
+ .irp suffix, , l, b, h, lb, lh
+ \op\suffix x0, [x2]
+ \op\suffix w2, [w3]
+ .endr
+ .irp suffix, , l
+ \op\suffix x0, [w3]
+ .endr
+ .endm
+
+ .macro format_1_check op
+ .irp suffix, , a, l, al
+ \op\suffix w1, w1, w2, w3, [x5]
+ \op\suffix w4, w4, w6, w7, [sp]
+ \op\suffix w0, x1, x2, x3, [x2]
+ \op\suffix x4, x5, x6, x7, [w8]
+ .endr
+ .endm
+
+ .macro format_2_check op
+ .irp suffix, add, clr, eor, set, smax, smin, umax, umin
+ format_0_check \op\suffix
+ .endr
+ .endm
+
+ .macro format_3_check op
+ .irp suffix, add, clr, eor, set, smax, smin, umax, umin
+ format_0_no_rt_no_acquire_check \op\suffix
+ .endr
+ .endm
+
+ .text
+func:
+ format_0_check cas
+ format_0_check swp
+ format_1_check casp
+ format_2_check ld
+ format_3_check st
--- /dev/null
+#objdump: -dr
+#as:-march=armv8-a+lse
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 88a07c41 cas w0, w1, \[x2\]
+ 4: 88a27fe3 cas w2, w3, \[sp\]
+ 8: 88e07c41 casa w0, w1, \[x2\]
+ c: 88e27fe3 casa w2, w3, \[sp\]
+ 10: 88a0fc41 casl w0, w1, \[x2\]
+ 14: 88a2ffe3 casl w2, w3, \[sp\]
+ 18: 88e0fc41 casal w0, w1, \[x2\]
+ 1c: 88e2ffe3 casal w2, w3, \[sp\]
+ 20: 08a07c41 casb w0, w1, \[x2\]
+ 24: 08a27fe3 casb w2, w3, \[sp\]
+ 28: 48a07c41 cash w0, w1, \[x2\]
+ 2c: 48a27fe3 cash w2, w3, \[sp\]
+ 30: 08e07c41 casab w0, w1, \[x2\]
+ 34: 08e27fe3 casab w2, w3, \[sp\]
+ 38: 08a0fc41 caslb w0, w1, \[x2\]
+ 3c: 08a2ffe3 caslb w2, w3, \[sp\]
+ 40: 08e0fc41 casalb w0, w1, \[x2\]
+ 44: 08e2ffe3 casalb w2, w3, \[sp\]
+ 48: 48e07c41 casah w0, w1, \[x2\]
+ 4c: 48e27fe3 casah w2, w3, \[sp\]
+ 50: 48a0fc41 caslh w0, w1, \[x2\]
+ 54: 48a2ffe3 caslh w2, w3, \[sp\]
+ 58: 48e0fc41 casalh w0, w1, \[x2\]
+ 5c: 48e2ffe3 casalh w2, w3, \[sp\]
+ 60: c8a07c41 cas x0, x1, \[x2\]
+ 64: c8a27fe3 cas x2, x3, \[sp\]
+ 68: c8e07c41 casa x0, x1, \[x2\]
+ 6c: c8e27fe3 casa x2, x3, \[sp\]
+ 70: c8a0fc41 casl x0, x1, \[x2\]
+ 74: c8a2ffe3 casl x2, x3, \[sp\]
+ 78: c8e0fc41 casal x0, x1, \[x2\]
+ 7c: c8e2ffe3 casal x2, x3, \[sp\]
+ 80: b8208041 swp w0, w1, \[x2\]
+ 84: b82283e3 swp w2, w3, \[sp\]
+ 88: b8a08041 swpa w0, w1, \[x2\]
+ 8c: b8a283e3 swpa w2, w3, \[sp\]
+ 90: b8608041 swpl w0, w1, \[x2\]
+ 94: b86283e3 swpl w2, w3, \[sp\]
+ 98: b8e08041 swpal w0, w1, \[x2\]
+ 9c: b8e283e3 swpal w2, w3, \[sp\]
+ a0: 38208041 swpb w0, w1, \[x2\]
+ a4: 382283e3 swpb w2, w3, \[sp\]
+ a8: 78208041 swph w0, w1, \[x2\]
+ ac: 782283e3 swph w2, w3, \[sp\]
+ b0: 38a08041 swpab w0, w1, \[x2\]
+ b4: 38a283e3 swpab w2, w3, \[sp\]
+ b8: 38608041 swplb w0, w1, \[x2\]
+ bc: 386283e3 swplb w2, w3, \[sp\]
+ c0: 38e08041 swpalb w0, w1, \[x2\]
+ c4: 38e283e3 swpalb w2, w3, \[sp\]
+ c8: 78a08041 swpah w0, w1, \[x2\]
+ cc: 78a283e3 swpah w2, w3, \[sp\]
+ d0: 78608041 swplh w0, w1, \[x2\]
+ d4: 786283e3 swplh w2, w3, \[sp\]
+ d8: 78e08041 swpalh w0, w1, \[x2\]
+ dc: 78e283e3 swpalh w2, w3, \[sp\]
+ e0: f8208041 swp x0, x1, \[x2\]
+ e4: f82283e3 swp x2, x3, \[sp\]
+ e8: f8a08041 swpa x0, x1, \[x2\]
+ ec: f8a283e3 swpa x2, x3, \[sp\]
+ f0: f8608041 swpl x0, x1, \[x2\]
+ f4: f86283e3 swpl x2, x3, \[sp\]
+ f8: f8e08041 swpal x0, x1, \[x2\]
+ fc: f8e283e3 swpal x2, x3, \[sp\]
+ 100: 08207ca2 casp w0, w1, w2, w3, \[x5\]
+ 104: 08247fe6 casp w4, w5, w6, w7, \[sp\]
+ 108: 48207c42 casp x0, x1, x2, x3, \[x2\]
+ 10c: 48247fe6 casp x4, x5, x6, x7, \[sp\]
+ 110: 08607ca2 caspa w0, w1, w2, w3, \[x5\]
+ 114: 08647fe6 caspa w4, w5, w6, w7, \[sp\]
+ 118: 48607c42 caspa x0, x1, x2, x3, \[x2\]
+ 11c: 48647fe6 caspa x4, x5, x6, x7, \[sp\]
+ 120: 0820fca2 caspl w0, w1, w2, w3, \[x5\]
+ 124: 0824ffe6 caspl w4, w5, w6, w7, \[sp\]
+ 128: 4820fc42 caspl x0, x1, x2, x3, \[x2\]
+ 12c: 4824ffe6 caspl x4, x5, x6, x7, \[sp\]
+ 130: 0860fca2 caspal w0, w1, w2, w3, \[x5\]
+ 134: 0864ffe6 caspal w4, w5, w6, w7, \[sp\]
+ 138: 4860fc42 caspal x0, x1, x2, x3, \[x2\]
+ 13c: 4864ffe6 caspal x4, x5, x6, x7, \[sp\]
+ 140: b8200041 ldadd w0, w1, \[x2\]
+ 144: b82203e3 ldadd w2, w3, \[sp\]
+ 148: b8a00041 ldadda w0, w1, \[x2\]
+ 14c: b8a203e3 ldadda w2, w3, \[sp\]
+ 150: b8600041 ldaddl w0, w1, \[x2\]
+ 154: b86203e3 ldaddl w2, w3, \[sp\]
+ 158: b8e00041 ldaddal w0, w1, \[x2\]
+ 15c: b8e203e3 ldaddal w2, w3, \[sp\]
+ 160: 38200041 ldaddb w0, w1, \[x2\]
+ 164: 382203e3 ldaddb w2, w3, \[sp\]
+ 168: 78200041 ldaddh w0, w1, \[x2\]
+ 16c: 782203e3 ldaddh w2, w3, \[sp\]
+ 170: 38a00041 ldaddab w0, w1, \[x2\]
+ 174: 38a203e3 ldaddab w2, w3, \[sp\]
+ 178: 38600041 ldaddlb w0, w1, \[x2\]
+ 17c: 386203e3 ldaddlb w2, w3, \[sp\]
+ 180: 38e00041 ldaddalb w0, w1, \[x2\]
+ 184: 38e203e3 ldaddalb w2, w3, \[sp\]
+ 188: 78a00041 ldaddah w0, w1, \[x2\]
+ 18c: 78a203e3 ldaddah w2, w3, \[sp\]
+ 190: 78600041 ldaddlh w0, w1, \[x2\]
+ 194: 786203e3 ldaddlh w2, w3, \[sp\]
+ 198: 78e00041 ldaddalh w0, w1, \[x2\]
+ 19c: 78e203e3 ldaddalh w2, w3, \[sp\]
+ 1a0: f8200041 ldadd x0, x1, \[x2\]
+ 1a4: f82203e3 ldadd x2, x3, \[sp\]
+ 1a8: f8a00041 ldadda x0, x1, \[x2\]
+ 1ac: f8a203e3 ldadda x2, x3, \[sp\]
+ 1b0: f8600041 ldaddl x0, x1, \[x2\]
+ 1b4: f86203e3 ldaddl x2, x3, \[sp\]
+ 1b8: f8e00041 ldaddal x0, x1, \[x2\]
+ 1bc: f8e203e3 ldaddal x2, x3, \[sp\]
+ 1c0: b8201041 ldclr w0, w1, \[x2\]
+ 1c4: b82213e3 ldclr w2, w3, \[sp\]
+ 1c8: b8a01041 ldclra w0, w1, \[x2\]
+ 1cc: b8a213e3 ldclra w2, w3, \[sp\]
+ 1d0: b8601041 ldclrl w0, w1, \[x2\]
+ 1d4: b86213e3 ldclrl w2, w3, \[sp\]
+ 1d8: b8e01041 ldclral w0, w1, \[x2\]
+ 1dc: b8e213e3 ldclral w2, w3, \[sp\]
+ 1e0: 38201041 ldclrb w0, w1, \[x2\]
+ 1e4: 382213e3 ldclrb w2, w3, \[sp\]
+ 1e8: 78201041 ldclrh w0, w1, \[x2\]
+ 1ec: 782213e3 ldclrh w2, w3, \[sp\]
+ 1f0: 38a01041 ldclrab w0, w1, \[x2\]
+ 1f4: 38a213e3 ldclrab w2, w3, \[sp\]
+ 1f8: 38601041 ldclrlb w0, w1, \[x2\]
+ 1fc: 386213e3 ldclrlb w2, w3, \[sp\]
+ 200: 38e01041 ldclralb w0, w1, \[x2\]
+ 204: 38e213e3 ldclralb w2, w3, \[sp\]
+ 208: 78a01041 ldclrah w0, w1, \[x2\]
+ 20c: 78a213e3 ldclrah w2, w3, \[sp\]
+ 210: 78601041 ldclrlh w0, w1, \[x2\]
+ 214: 786213e3 ldclrlh w2, w3, \[sp\]
+ 218: 78e01041 ldclralh w0, w1, \[x2\]
+ 21c: 78e213e3 ldclralh w2, w3, \[sp\]
+ 220: f8201041 ldclr x0, x1, \[x2\]
+ 224: f82213e3 ldclr x2, x3, \[sp\]
+ 228: f8a01041 ldclra x0, x1, \[x2\]
+ 22c: f8a213e3 ldclra x2, x3, \[sp\]
+ 230: f8601041 ldclrl x0, x1, \[x2\]
+ 234: f86213e3 ldclrl x2, x3, \[sp\]
+ 238: f8e01041 ldclral x0, x1, \[x2\]
+ 23c: f8e213e3 ldclral x2, x3, \[sp\]
+ 240: b8202041 ldeor w0, w1, \[x2\]
+ 244: b82223e3 ldeor w2, w3, \[sp\]
+ 248: b8a02041 ldeora w0, w1, \[x2\]
+ 24c: b8a223e3 ldeora w2, w3, \[sp\]
+ 250: b8602041 ldeorl w0, w1, \[x2\]
+ 254: b86223e3 ldeorl w2, w3, \[sp\]
+ 258: b8e02041 ldeoral w0, w1, \[x2\]
+ 25c: b8e223e3 ldeoral w2, w3, \[sp\]
+ 260: 38202041 ldeorb w0, w1, \[x2\]
+ 264: 382223e3 ldeorb w2, w3, \[sp\]
+ 268: 78202041 ldeorh w0, w1, \[x2\]
+ 26c: 782223e3 ldeorh w2, w3, \[sp\]
+ 270: 38a02041 ldeorab w0, w1, \[x2\]
+ 274: 38a223e3 ldeorab w2, w3, \[sp\]
+ 278: 38602041 ldeorlb w0, w1, \[x2\]
+ 27c: 386223e3 ldeorlb w2, w3, \[sp\]
+ 280: 38e02041 ldeoralb w0, w1, \[x2\]
+ 284: 38e223e3 ldeoralb w2, w3, \[sp\]
+ 288: 78a02041 ldeorah w0, w1, \[x2\]
+ 28c: 78a223e3 ldeorah w2, w3, \[sp\]
+ 290: 78602041 ldeorlh w0, w1, \[x2\]
+ 294: 786223e3 ldeorlh w2, w3, \[sp\]
+ 298: 78e02041 ldeoralh w0, w1, \[x2\]
+ 29c: 78e223e3 ldeoralh w2, w3, \[sp\]
+ 2a0: f8202041 ldeor x0, x1, \[x2\]
+ 2a4: f82223e3 ldeor x2, x3, \[sp\]
+ 2a8: f8a02041 ldeora x0, x1, \[x2\]
+ 2ac: f8a223e3 ldeora x2, x3, \[sp\]
+ 2b0: f8602041 ldeorl x0, x1, \[x2\]
+ 2b4: f86223e3 ldeorl x2, x3, \[sp\]
+ 2b8: f8e02041 ldeoral x0, x1, \[x2\]
+ 2bc: f8e223e3 ldeoral x2, x3, \[sp\]
+ 2c0: b8203041 ldset w0, w1, \[x2\]
+ 2c4: b82233e3 ldset w2, w3, \[sp\]
+ 2c8: b8a03041 ldseta w0, w1, \[x2\]
+ 2cc: b8a233e3 ldseta w2, w3, \[sp\]
+ 2d0: b8603041 ldsetl w0, w1, \[x2\]
+ 2d4: b86233e3 ldsetl w2, w3, \[sp\]
+ 2d8: b8e03041 ldsetal w0, w1, \[x2\]
+ 2dc: b8e233e3 ldsetal w2, w3, \[sp\]
+ 2e0: 38203041 ldsetb w0, w1, \[x2\]
+ 2e4: 382233e3 ldsetb w2, w3, \[sp\]
+ 2e8: 78203041 ldseth w0, w1, \[x2\]
+ 2ec: 782233e3 ldseth w2, w3, \[sp\]
+ 2f0: 38a03041 ldsetab w0, w1, \[x2\]
+ 2f4: 38a233e3 ldsetab w2, w3, \[sp\]
+ 2f8: 38603041 ldsetlb w0, w1, \[x2\]
+ 2fc: 386233e3 ldsetlb w2, w3, \[sp\]
+ 300: 38e03041 ldsetalb w0, w1, \[x2\]
+ 304: 38e233e3 ldsetalb w2, w3, \[sp\]
+ 308: 78a03041 ldsetah w0, w1, \[x2\]
+ 30c: 78a233e3 ldsetah w2, w3, \[sp\]
+ 310: 78603041 ldsetlh w0, w1, \[x2\]
+ 314: 786233e3 ldsetlh w2, w3, \[sp\]
+ 318: 78e03041 ldsetalh w0, w1, \[x2\]
+ 31c: 78e233e3 ldsetalh w2, w3, \[sp\]
+ 320: f8203041 ldset x0, x1, \[x2\]
+ 324: f82233e3 ldset x2, x3, \[sp\]
+ 328: f8a03041 ldseta x0, x1, \[x2\]
+ 32c: f8a233e3 ldseta x2, x3, \[sp\]
+ 330: f8603041 ldsetl x0, x1, \[x2\]
+ 334: f86233e3 ldsetl x2, x3, \[sp\]
+ 338: f8e03041 ldsetal x0, x1, \[x2\]
+ 33c: f8e233e3 ldsetal x2, x3, \[sp\]
+ 340: b8204041 ldsmax w0, w1, \[x2\]
+ 344: b82243e3 ldsmax w2, w3, \[sp\]
+ 348: b8a04041 ldsmaxa w0, w1, \[x2\]
+ 34c: b8a243e3 ldsmaxa w2, w3, \[sp\]
+ 350: b8604041 ldsmaxl w0, w1, \[x2\]
+ 354: b86243e3 ldsmaxl w2, w3, \[sp\]
+ 358: b8e04041 ldsmaxal w0, w1, \[x2\]
+ 35c: b8e243e3 ldsmaxal w2, w3, \[sp\]
+ 360: 38204041 ldsmaxb w0, w1, \[x2\]
+ 364: 382243e3 ldsmaxb w2, w3, \[sp\]
+ 368: 78204041 ldsmaxh w0, w1, \[x2\]
+ 36c: 782243e3 ldsmaxh w2, w3, \[sp\]
+ 370: 38a04041 ldsmaxab w0, w1, \[x2\]
+ 374: 38a243e3 ldsmaxab w2, w3, \[sp\]
+ 378: 38604041 ldsmaxlb w0, w1, \[x2\]
+ 37c: 386243e3 ldsmaxlb w2, w3, \[sp\]
+ 380: 38e04041 ldsmaxalb w0, w1, \[x2\]
+ 384: 38e243e3 ldsmaxalb w2, w3, \[sp\]
+ 388: 78a04041 ldsmaxah w0, w1, \[x2\]
+ 38c: 78a243e3 ldsmaxah w2, w3, \[sp\]
+ 390: 78604041 ldsmaxlh w0, w1, \[x2\]
+ 394: 786243e3 ldsmaxlh w2, w3, \[sp\]
+ 398: 78e04041 ldsmaxalh w0, w1, \[x2\]
+ 39c: 78e243e3 ldsmaxalh w2, w3, \[sp\]
+ 3a0: f8204041 ldsmax x0, x1, \[x2\]
+ 3a4: f82243e3 ldsmax x2, x3, \[sp\]
+ 3a8: f8a04041 ldsmaxa x0, x1, \[x2\]
+ 3ac: f8a243e3 ldsmaxa x2, x3, \[sp\]
+ 3b0: f8604041 ldsmaxl x0, x1, \[x2\]
+ 3b4: f86243e3 ldsmaxl x2, x3, \[sp\]
+ 3b8: f8e04041 ldsmaxal x0, x1, \[x2\]
+ 3bc: f8e243e3 ldsmaxal x2, x3, \[sp\]
+ 3c0: b8205041 ldsmin w0, w1, \[x2\]
+ 3c4: b82253e3 ldsmin w2, w3, \[sp\]
+ 3c8: b8a05041 ldsmina w0, w1, \[x2\]
+ 3cc: b8a253e3 ldsmina w2, w3, \[sp\]
+ 3d0: b8605041 ldsminl w0, w1, \[x2\]
+ 3d4: b86253e3 ldsminl w2, w3, \[sp\]
+ 3d8: b8e05041 ldsminal w0, w1, \[x2\]
+ 3dc: b8e253e3 ldsminal w2, w3, \[sp\]
+ 3e0: 38205041 ldsminb w0, w1, \[x2\]
+ 3e4: 382253e3 ldsminb w2, w3, \[sp\]
+ 3e8: 78205041 ldsminh w0, w1, \[x2\]
+ 3ec: 782253e3 ldsminh w2, w3, \[sp\]
+ 3f0: 38a05041 ldsminab w0, w1, \[x2\]
+ 3f4: 38a253e3 ldsminab w2, w3, \[sp\]
+ 3f8: 38605041 ldsminlb w0, w1, \[x2\]
+ 3fc: 386253e3 ldsminlb w2, w3, \[sp\]
+ 400: 38e05041 ldsminalb w0, w1, \[x2\]
+ 404: 38e253e3 ldsminalb w2, w3, \[sp\]
+ 408: 78a05041 ldsminah w0, w1, \[x2\]
+ 40c: 78a253e3 ldsminah w2, w3, \[sp\]
+ 410: 78605041 ldsminlh w0, w1, \[x2\]
+ 414: 786253e3 ldsminlh w2, w3, \[sp\]
+ 418: 78e05041 ldsminalh w0, w1, \[x2\]
+ 41c: 78e253e3 ldsminalh w2, w3, \[sp\]
+ 420: f8205041 ldsmin x0, x1, \[x2\]
+ 424: f82253e3 ldsmin x2, x3, \[sp\]
+ 428: f8a05041 ldsmina x0, x1, \[x2\]
+ 42c: f8a253e3 ldsmina x2, x3, \[sp\]
+ 430: f8605041 ldsminl x0, x1, \[x2\]
+ 434: f86253e3 ldsminl x2, x3, \[sp\]
+ 438: f8e05041 ldsminal x0, x1, \[x2\]
+ 43c: f8e253e3 ldsminal x2, x3, \[sp\]
+ 440: b8206041 ldumax w0, w1, \[x2\]
+ 444: b82263e3 ldumax w2, w3, \[sp\]
+ 448: b8a06041 ldumaxa w0, w1, \[x2\]
+ 44c: b8a263e3 ldumaxa w2, w3, \[sp\]
+ 450: b8606041 ldumaxl w0, w1, \[x2\]
+ 454: b86263e3 ldumaxl w2, w3, \[sp\]
+ 458: b8e06041 ldumaxal w0, w1, \[x2\]
+ 45c: b8e263e3 ldumaxal w2, w3, \[sp\]
+ 460: 38206041 ldumaxb w0, w1, \[x2\]
+ 464: 382263e3 ldumaxb w2, w3, \[sp\]
+ 468: 78206041 ldumaxh w0, w1, \[x2\]
+ 46c: 782263e3 ldumaxh w2, w3, \[sp\]
+ 470: 38a06041 ldumaxab w0, w1, \[x2\]
+ 474: 38a263e3 ldumaxab w2, w3, \[sp\]
+ 478: 38606041 ldumaxlb w0, w1, \[x2\]
+ 47c: 386263e3 ldumaxlb w2, w3, \[sp\]
+ 480: 38e06041 ldumaxalb w0, w1, \[x2\]
+ 484: 38e263e3 ldumaxalb w2, w3, \[sp\]
+ 488: 78a06041 ldumaxah w0, w1, \[x2\]
+ 48c: 78a263e3 ldumaxah w2, w3, \[sp\]
+ 490: 78606041 ldumaxlh w0, w1, \[x2\]
+ 494: 786263e3 ldumaxlh w2, w3, \[sp\]
+ 498: 78e06041 ldumaxalh w0, w1, \[x2\]
+ 49c: 78e263e3 ldumaxalh w2, w3, \[sp\]
+ 4a0: f8206041 ldumax x0, x1, \[x2\]
+ 4a4: f82263e3 ldumax x2, x3, \[sp\]
+ 4a8: f8a06041 ldumaxa x0, x1, \[x2\]
+ 4ac: f8a263e3 ldumaxa x2, x3, \[sp\]
+ 4b0: f8606041 ldumaxl x0, x1, \[x2\]
+ 4b4: f86263e3 ldumaxl x2, x3, \[sp\]
+ 4b8: f8e06041 ldumaxal x0, x1, \[x2\]
+ 4bc: f8e263e3 ldumaxal x2, x3, \[sp\]
+ 4c0: b8207041 ldumin w0, w1, \[x2\]
+ 4c4: b82273e3 ldumin w2, w3, \[sp\]
+ 4c8: b8a07041 ldumina w0, w1, \[x2\]
+ 4cc: b8a273e3 ldumina w2, w3, \[sp\]
+ 4d0: b8607041 lduminl w0, w1, \[x2\]
+ 4d4: b86273e3 lduminl w2, w3, \[sp\]
+ 4d8: b8e07041 lduminal w0, w1, \[x2\]
+ 4dc: b8e273e3 lduminal w2, w3, \[sp\]
+ 4e0: 38207041 lduminb w0, w1, \[x2\]
+ 4e4: 382273e3 lduminb w2, w3, \[sp\]
+ 4e8: 78207041 lduminh w0, w1, \[x2\]
+ 4ec: 782273e3 lduminh w2, w3, \[sp\]
+ 4f0: 38a07041 lduminab w0, w1, \[x2\]
+ 4f4: 38a273e3 lduminab w2, w3, \[sp\]
+ 4f8: 38607041 lduminlb w0, w1, \[x2\]
+ 4fc: 386273e3 lduminlb w2, w3, \[sp\]
+ 500: 38e07041 lduminalb w0, w1, \[x2\]
+ 504: 38e273e3 lduminalb w2, w3, \[sp\]
+ 508: 78a07041 lduminah w0, w1, \[x2\]
+ 50c: 78a273e3 lduminah w2, w3, \[sp\]
+ 510: 78607041 lduminlh w0, w1, \[x2\]
+ 514: 786273e3 lduminlh w2, w3, \[sp\]
+ 518: 78e07041 lduminalh w0, w1, \[x2\]
+ 51c: 78e273e3 lduminalh w2, w3, \[sp\]
+ 520: f8207041 ldumin x0, x1, \[x2\]
+ 524: f82273e3 ldumin x2, x3, \[sp\]
+ 528: f8a07041 ldumina x0, x1, \[x2\]
+ 52c: f8a273e3 ldumina x2, x3, \[sp\]
+ 530: f8607041 lduminl x0, x1, \[x2\]
+ 534: f86273e3 lduminl x2, x3, \[sp\]
+ 538: f8e07041 lduminal x0, x1, \[x2\]
+ 53c: f8e273e3 lduminal x2, x3, \[sp\]
+ 540: b820005f stadd w0, \[x2\]
+ 544: b82203ff stadd w2, \[sp\]
+ 548: b860005f staddl w0, \[x2\]
+ 54c: b86203ff staddl w2, \[sp\]
+ 550: 3820005f staddb w0, \[x2\]
+ 554: 382203ff staddb w2, \[sp\]
+ 558: 7820005f staddh w0, \[x2\]
+ 55c: 782203ff staddh w2, \[sp\]
+ 560: 3860005f staddlb w0, \[x2\]
+ 564: 386203ff staddlb w2, \[sp\]
+ 568: 7860005f staddlh w0, \[x2\]
+ 56c: 786203ff staddlh w2, \[sp\]
+ 570: f820005f stadd x0, \[x2\]
+ 574: f82203ff stadd x2, \[sp\]
+ 578: f860005f staddl x0, \[x2\]
+ 57c: f86203ff staddl x2, \[sp\]
+ 580: b820105f stclr w0, \[x2\]
+ 584: b82213ff stclr w2, \[sp\]
+ 588: b860105f stclrl w0, \[x2\]
+ 58c: b86213ff stclrl w2, \[sp\]
+ 590: 3820105f stclrb w0, \[x2\]
+ 594: 382213ff stclrb w2, \[sp\]
+ 598: 7820105f stclrh w0, \[x2\]
+ 59c: 782213ff stclrh w2, \[sp\]
+ 5a0: 3860105f stclrlb w0, \[x2\]
+ 5a4: 386213ff stclrlb w2, \[sp\]
+ 5a8: 7860105f stclrlh w0, \[x2\]
+ 5ac: 786213ff stclrlh w2, \[sp\]
+ 5b0: f820105f stclr x0, \[x2\]
+ 5b4: f82213ff stclr x2, \[sp\]
+ 5b8: f860105f stclrl x0, \[x2\]
+ 5bc: f86213ff stclrl x2, \[sp\]
+ 5c0: b820205f steor w0, \[x2\]
+ 5c4: b82223ff steor w2, \[sp\]
+ 5c8: b860205f steorl w0, \[x2\]
+ 5cc: b86223ff steorl w2, \[sp\]
+ 5d0: 3820205f steorb w0, \[x2\]
+ 5d4: 382223ff steorb w2, \[sp\]
+ 5d8: 7820205f steorh w0, \[x2\]
+ 5dc: 782223ff steorh w2, \[sp\]
+ 5e0: 3860205f steorlb w0, \[x2\]
+ 5e4: 386223ff steorlb w2, \[sp\]
+ 5e8: 7860205f steorlh w0, \[x2\]
+ 5ec: 786223ff steorlh w2, \[sp\]
+ 5f0: f820205f steor x0, \[x2\]
+ 5f4: f82223ff steor x2, \[sp\]
+ 5f8: f860205f steorl x0, \[x2\]
+ 5fc: f86223ff steorl x2, \[sp\]
+ 600: b820305f stset w0, \[x2\]
+ 604: b82233ff stset w2, \[sp\]
+ 608: b860305f stsetl w0, \[x2\]
+ 60c: b86233ff stsetl w2, \[sp\]
+ 610: 3820305f stsetb w0, \[x2\]
+ 614: 382233ff stsetb w2, \[sp\]
+ 618: 7820305f stseth w0, \[x2\]
+ 61c: 782233ff stseth w2, \[sp\]
+ 620: 3860305f stsetlb w0, \[x2\]
+ 624: 386233ff stsetlb w2, \[sp\]
+ 628: 7860305f stsetlh w0, \[x2\]
+ 62c: 786233ff stsetlh w2, \[sp\]
+ 630: f820305f stset x0, \[x2\]
+ 634: f82233ff stset x2, \[sp\]
+ 638: f860305f stsetl x0, \[x2\]
+ 63c: f86233ff stsetl x2, \[sp\]
+ 640: b820405f stsmax w0, \[x2\]
+ 644: b82243ff stsmax w2, \[sp\]
+ 648: b860405f stsmaxl w0, \[x2\]
+ 64c: b86243ff stsmaxl w2, \[sp\]
+ 650: 3820405f stsmaxb w0, \[x2\]
+ 654: 382243ff stsmaxb w2, \[sp\]
+ 658: 7820405f stsmaxh w0, \[x2\]
+ 65c: 782243ff stsmaxh w2, \[sp\]
+ 660: 3860405f stsmaxlb w0, \[x2\]
+ 664: 386243ff stsmaxlb w2, \[sp\]
+ 668: 7860405f stsmaxlh w0, \[x2\]
+ 66c: 786243ff stsmaxlh w2, \[sp\]
+ 670: f820405f stsmax x0, \[x2\]
+ 674: f82243ff stsmax x2, \[sp\]
+ 678: f860405f stsmaxl x0, \[x2\]
+ 67c: f86243ff stsmaxl x2, \[sp\]
+ 680: b820505f stsmin w0, \[x2\]
+ 684: b82253ff stsmin w2, \[sp\]
+ 688: b860505f stsminl w0, \[x2\]
+ 68c: b86253ff stsminl w2, \[sp\]
+ 690: 3820505f stsminb w0, \[x2\]
+ 694: 382253ff stsminb w2, \[sp\]
+ 698: 7820505f stsminh w0, \[x2\]
+ 69c: 782253ff stsminh w2, \[sp\]
+ 6a0: 3860505f stsminlb w0, \[x2\]
+ 6a4: 386253ff stsminlb w2, \[sp\]
+ 6a8: 7860505f stsminlh w0, \[x2\]
+ 6ac: 786253ff stsminlh w2, \[sp\]
+ 6b0: f820505f stsmin x0, \[x2\]
+ 6b4: f82253ff stsmin x2, \[sp\]
+ 6b8: f860505f stsminl x0, \[x2\]
+ 6bc: f86253ff stsminl x2, \[sp\]
+ 6c0: b820605f stumax w0, \[x2\]
+ 6c4: b82263ff stumax w2, \[sp\]
+ 6c8: b860605f stumaxl w0, \[x2\]
+ 6cc: b86263ff stumaxl w2, \[sp\]
+ 6d0: 3820605f stumaxb w0, \[x2\]
+ 6d4: 382263ff stumaxb w2, \[sp\]
+ 6d8: 7820605f stumaxh w0, \[x2\]
+ 6dc: 782263ff stumaxh w2, \[sp\]
+ 6e0: 3860605f stumaxlb w0, \[x2\]
+ 6e4: 386263ff stumaxlb w2, \[sp\]
+ 6e8: 7860605f stumaxlh w0, \[x2\]
+ 6ec: 786263ff stumaxlh w2, \[sp\]
+ 6f0: f820605f stumax x0, \[x2\]
+ 6f4: f82263ff stumax x2, \[sp\]
+ 6f8: f860605f stumaxl x0, \[x2\]
+ 6fc: f86263ff stumaxl x2, \[sp\]
+ 700: b820705f stumin w0, \[x2\]
+ 704: b82273ff stumin w2, \[sp\]
+ 708: b860705f stuminl w0, \[x2\]
+ 70c: b86273ff stuminl w2, \[sp\]
+ 710: 3820705f stuminb w0, \[x2\]
+ 714: 382273ff stuminb w2, \[sp\]
+ 718: 7820705f stuminh w0, \[x2\]
+ 71c: 782273ff stuminh w2, \[sp\]
+ 720: 3860705f stuminlb w0, \[x2\]
+ 724: 386273ff stuminlb w2, \[sp\]
+ 728: 7860705f stuminlh w0, \[x2\]
+ 72c: 786273ff stuminlh w2, \[sp\]
+ 730: f820705f stumin x0, \[x2\]
+ 734: f82273ff stumin x2, \[sp\]
+ 738: f860705f stuminl x0, \[x2\]
+ 73c: f86273ff stuminl x2, \[sp\]
--- /dev/null
+/* lse-atomic.s Test file For AArch64 LSE atomic instructions encoding.
+
+ Copyright 2014 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+
+ .macro format_0 op
+ .irp suffix, , a, l, al, b, h, ab, lb, alb, ah, lh, alh
+ \op\suffix w0, w1, [x2]
+ \op\suffix w2, w3, [sp]
+ .endr
+ .irp suffix, , a, l, al
+ \op\suffix x0, x1, [x2]
+ \op\suffix x2, x3, [sp]
+ .endr
+ .endm
+
+ .macro format_0_no_rt_no_acquire op
+ .irp suffix, , l, b, h, lb, lh
+ \op\suffix w0, [x2]
+ \op\suffix w2, [sp]
+ .endr
+ .irp suffix, , l
+ \op\suffix x0, [x2]
+ \op\suffix x2, [sp]
+ .endr
+ .endm
+
+ .macro format_1 op
+ .irp suffix, , a, l, al
+ \op\suffix w0, w1, w2, w3, [x5]
+ \op\suffix w4, w5, w6, w7, [sp]
+ \op\suffix x0, x1, x2, x3, [x2]
+ \op\suffix x4, x5, x6, x7, [sp]
+ .endr
+ .endm
+
+ .macro format_2 op
+ .irp suffix, add, clr, eor, set, smax, smin, umax, umin
+ format_0 \op\suffix
+ .endr
+ .endm
+
+ .macro format_3 op
+ .irp suffix, add, clr, eor, set, smax, smin, umax, umin
+ format_0_no_rt_no_acquire \op\suffix
+ .endr
+ .endm
+
+ .text
+func:
+ format_0 cas
+ format_0 swp
+ format_1 casp
+ format_2 ld
+ format_3 st
+2014-09-03 Jiong Wang <jiong.wang@arm.com>
+
+ * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
+ (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
+ (aarch64_insn_class): Add lse_atomic.
+ (F_LSE_SZ): New field added.
+ (opcode_has_special_coder): Recognize F_LSE_SZ.
+
2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
* mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
+#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
/* Architectures are the sum of the base and extensions. */
#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
+ AARCH64_OPND_PAIRREG, /* Paired register operand. */
AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
loadlit,
log_imm,
log_shift,
+ lse_atomic,
movewide,
pcreladdr,
ic_system,
#define F_N (1 << 23)
/* Opcode dependent field. */
#define F_OD(X) (((X) & 0x7) << 24)
-/* Next bit is 27. */
+/* Instruction has the field of 'sz'. */
+#define F_LSE_SZ (1 << 27)
+/* Next bit is 28. */
static inline bfd_boolean
alias_opcode_p (const aarch64_opcode *opcode)
static inline bfd_boolean
opcode_has_special_coder (const aarch64_opcode *opcode)
{
- return (opcode->flags & (F_SF | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
+ return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
| F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
: FALSE;
}
+2014-09-03 Jiong Wang <jiong.wang@arm.com>
+
+ * aarch64-tbl.h (QL_R4NIL): New qualifiers.
+ (aarch64_feature_lse): New feature added.
+ (LSE): New Added.
+ (aarch64_opcode_table): New LSE instructions added. Improve
+ descriptions for ldarb/ldarh/ldar.
+ (aarch64_opcode_table): Describe PAIRREG.
+ * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
+ * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
+ (aarch64_print_operand): Recognize PAIRREG.
+ (operand_general_constraint_met_p): Check reg pair constraints for CASP
+ instructions.
+ * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
+ (do_special_decoding): Recognize F_LSE_SZ.
+ * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
+
2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
* micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
case 774: /* tst */
value = 773; /* --> ands. */
break;
- case 777: /* mov */
- value = 776; /* --> movn. */
- break;
- case 779: /* mov */
- value = 778; /* --> movz. */
- break;
- case 790: /* sevl */
- case 789: /* sev */
- case 788: /* wfi */
- case 787: /* wfe */
- case 786: /* yield */
- case 785: /* nop */
- value = 784; /* --> hint. */
- break;
- case 799: /* tlbi */
- case 798: /* ic */
- case 797: /* dc */
- case 796: /* at */
- value = 795; /* --> sys. */
+ case 900: /* staddb */
+ value = 804; /* --> ldaddb. */
+ break;
+ case 901: /* staddh */
+ value = 805; /* --> ldaddh. */
+ break;
+ case 902: /* stadd */
+ value = 806; /* --> ldadd. */
+ break;
+ case 903: /* staddlb */
+ value = 808; /* --> ldaddlb. */
+ break;
+ case 904: /* staddlh */
+ value = 811; /* --> ldaddlh. */
+ break;
+ case 905: /* staddl */
+ value = 814; /* --> ldaddl. */
+ break;
+ case 906: /* stclrb */
+ value = 816; /* --> ldclrb. */
+ break;
+ case 907: /* stclrh */
+ value = 817; /* --> ldclrh. */
+ break;
+ case 908: /* stclr */
+ value = 818; /* --> ldclr. */
+ break;
+ case 909: /* stclrlb */
+ value = 820; /* --> ldclrlb. */
+ break;
+ case 910: /* stclrlh */
+ value = 823; /* --> ldclrlh. */
+ break;
+ case 911: /* stclrl */
+ value = 826; /* --> ldclrl. */
+ break;
+ case 912: /* steorb */
+ value = 828; /* --> ldeorb. */
+ break;
+ case 913: /* steorh */
+ value = 829; /* --> ldeorh. */
+ break;
+ case 914: /* steor */
+ value = 830; /* --> ldeor. */
+ break;
+ case 915: /* steorlb */
+ value = 832; /* --> ldeorlb. */
+ break;
+ case 916: /* steorlh */
+ value = 835; /* --> ldeorlh. */
+ break;
+ case 917: /* steorl */
+ value = 838; /* --> ldeorl. */
+ break;
+ case 918: /* stsetb */
+ value = 840; /* --> ldsetb. */
+ break;
+ case 919: /* stseth */
+ value = 841; /* --> ldseth. */
+ break;
+ case 920: /* stset */
+ value = 842; /* --> ldset. */
+ break;
+ case 921: /* stsetlb */
+ value = 844; /* --> ldsetlb. */
+ break;
+ case 922: /* stsetlh */
+ value = 847; /* --> ldsetlh. */
+ break;
+ case 923: /* stsetl */
+ value = 850; /* --> ldsetl. */
+ break;
+ case 924: /* stsmaxb */
+ value = 852; /* --> ldsmaxb. */
+ break;
+ case 925: /* stsmaxh */
+ value = 853; /* --> ldsmaxh. */
+ break;
+ case 926: /* stsmax */
+ value = 854; /* --> ldsmax. */
+ break;
+ case 927: /* stsmaxlb */
+ value = 856; /* --> ldsmaxlb. */
+ break;
+ case 928: /* stsmaxlh */
+ value = 859; /* --> ldsmaxlh. */
+ break;
+ case 929: /* stsmaxl */
+ value = 862; /* --> ldsmaxl. */
+ break;
+ case 930: /* stsminb */
+ value = 864; /* --> ldsminb. */
+ break;
+ case 931: /* stsminh */
+ value = 865; /* --> ldsminh. */
+ break;
+ case 932: /* stsmin */
+ value = 866; /* --> ldsmin. */
+ break;
+ case 933: /* stsminlb */
+ value = 868; /* --> ldsminlb. */
+ break;
+ case 934: /* stsminlh */
+ value = 871; /* --> ldsminlh. */
+ break;
+ case 935: /* stsminl */
+ value = 874; /* --> ldsminl. */
+ break;
+ case 936: /* stumaxb */
+ value = 876; /* --> ldumaxb. */
+ break;
+ case 937: /* stumaxh */
+ value = 877; /* --> ldumaxh. */
+ break;
+ case 938: /* stumax */
+ value = 878; /* --> ldumax. */
+ break;
+ case 939: /* stumaxlb */
+ value = 880; /* --> ldumaxlb. */
+ break;
+ case 940: /* stumaxlh */
+ value = 883; /* --> ldumaxlh. */
+ break;
+ case 941: /* stumaxl */
+ value = 886; /* --> ldumaxl. */
+ break;
+ case 942: /* stuminb */
+ value = 888; /* --> lduminb. */
+ break;
+ case 943: /* stuminh */
+ value = 889; /* --> lduminh. */
+ break;
+ case 944: /* stumin */
+ value = 890; /* --> ldumin. */
+ break;
+ case 945: /* stuminlb */
+ value = 892; /* --> lduminlb. */
+ break;
+ case 946: /* stuminlh */
+ value = 895; /* --> lduminlh. */
+ break;
+ case 947: /* stuminl */
+ value = 898; /* --> lduminl. */
+ break;
+ case 949: /* mov */
+ value = 948; /* --> movn. */
+ break;
+ case 951: /* mov */
+ value = 950; /* --> movz. */
+ break;
+ case 962: /* sevl */
+ case 961: /* sev */
+ case 960: /* wfi */
+ case 959: /* wfe */
+ case 958: /* yield */
+ case 957: /* nop */
+ value = 956; /* --> hint. */
+ break;
+ case 971: /* tlbi */
+ case 970: /* ic */
+ case 969: /* dc */
+ case 968: /* at */
+ value = 967; /* --> sys. */
break;
default: return NULL;
}
case 8:
case 9:
case 10:
- case 13:
case 14:
case 15:
case 16:
- case 18:
+ case 17:
case 19:
case 20:
case 21:
case 24:
case 25:
case 26:
- case 34:
+ case 27:
case 35:
+ case 36:
return aarch64_ins_regno (self, info, code, inst);
- case 11:
- return aarch64_ins_reg_extended (self, info, code, inst);
case 12:
+ return aarch64_ins_reg_extended (self, info, code, inst);
+ case 13:
return aarch64_ins_reg_shifted (self, info, code, inst);
- case 17:
+ case 18:
return aarch64_ins_ft (self, info, code, inst);
- case 27:
case 28:
case 29:
- return aarch64_ins_reglane (self, info, code, inst);
case 30:
- return aarch64_ins_reglist (self, info, code, inst);
+ return aarch64_ins_reglane (self, info, code, inst);
case 31:
- return aarch64_ins_ldst_reglist (self, info, code, inst);
+ return aarch64_ins_reglist (self, info, code, inst);
case 32:
- return aarch64_ins_ldst_reglist_r (self, info, code, inst);
+ return aarch64_ins_ldst_reglist (self, info, code, inst);
case 33:
+ return aarch64_ins_ldst_reglist_r (self, info, code, inst);
+ case 34:
return aarch64_ins_ldst_elemlist (self, info, code, inst);
- case 36:
- case 45:
+ case 37:
case 46:
case 47:
case 48:
case 55:
case 56:
case 57:
- case 66:
+ case 58:
case 67:
case 68:
case 69:
+ case 70:
return aarch64_ins_imm (self, info, code, inst);
- case 37:
case 38:
- return aarch64_ins_advsimd_imm_shift (self, info, code, inst);
case 39:
+ return aarch64_ins_advsimd_imm_shift (self, info, code, inst);
case 40:
case 41:
+ case 42:
return aarch64_ins_advsimd_imm_modified (self, info, code, inst);
- case 58:
- return aarch64_ins_limm (self, info, code, inst);
case 59:
- return aarch64_ins_aimm (self, info, code, inst);
+ return aarch64_ins_limm (self, info, code, inst);
case 60:
- return aarch64_ins_imm_half (self, info, code, inst);
+ return aarch64_ins_aimm (self, info, code, inst);
case 61:
+ return aarch64_ins_imm_half (self, info, code, inst);
+ case 62:
return aarch64_ins_fbits (self, info, code, inst);
- case 63:
case 64:
+ case 65:
return aarch64_ins_cond (self, info, code, inst);
- case 70:
- case 76:
- return aarch64_ins_addr_simple (self, info, code, inst);
case 71:
- return aarch64_ins_addr_regoff (self, info, code, inst);
+ case 77:
+ return aarch64_ins_addr_simple (self, info, code, inst);
case 72:
+ return aarch64_ins_addr_regoff (self, info, code, inst);
case 73:
case 74:
- return aarch64_ins_addr_simm (self, info, code, inst);
case 75:
+ return aarch64_ins_addr_simm (self, info, code, inst);
+ case 76:
return aarch64_ins_addr_uimm12 (self, info, code, inst);
- case 77:
- return aarch64_ins_simd_addr_post (self, info, code, inst);
case 78:
- return aarch64_ins_sysreg (self, info, code, inst);
+ return aarch64_ins_simd_addr_post (self, info, code, inst);
case 79:
- return aarch64_ins_pstatefield (self, info, code, inst);
+ return aarch64_ins_sysreg (self, info, code, inst);
case 80:
+ return aarch64_ins_pstatefield (self, info, code, inst);
case 81:
case 82:
case 83:
- return aarch64_ins_sysins_op (self, info, code, inst);
case 84:
+ return aarch64_ins_sysins_op (self, info, code, inst);
case 85:
- return aarch64_ins_barrier (self, info, code, inst);
case 86:
+ return aarch64_ins_barrier (self, info, code, inst);
+ case 87:
return aarch64_ins_prfop (self, info, code, inst);
default: assert (0); abort ();
}
if (inst->opcode->flags & F_N)
insert_field (FLD_N, &inst->value, value, inst->opcode->mask);
}
+ if (inst->opcode->flags & F_LSE_SZ)
+ {
+ idx = select_operand_for_sf_field_coding (inst->opcode);
+ value = (inst->operands[idx].qualifier == AARCH64_OPND_QLF_X
+ || inst->operands[idx].qualifier == AARCH64_OPND_QLF_SP)
+ ? 1 : 0;
+ insert_field (FLD_lse_sz, &inst->value, value, 0);
+ }
if (inst->opcode->flags & F_SIZEQ)
encode_sizeq (inst);
if (inst->opcode->flags & F_FPTYPE)
10987654321098765432109876543210
xxxxxxxxxxxxxxxxxxxxxxxx0000xxx0
adr. */
- return 781;
+ return 953;
}
else
{
10987654321098765432109876543210
xxxxxxxxxxxxxxxxxxxxxxxx0000xxx1
adrp. */
- return 782;
+ return 954;
}
}
else
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxxxxxxx0xxxxx100x00100xx
- stxp. */
- return 731;
+ if (((word >> 31) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx0xxxxx100x00100x0
+ casp. */
+ return 788;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx0xxxxx100x00100x1
+ stxp. */
+ return 731;
+ }
}
}
else
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxxxxxxx1xxxxx100x00100xx
- stlxp. */
- return 732;
+ if (((word >> 31) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx1xxxxx100x00100x0
+ caspl. */
+ return 790;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx1xxxxx100x00100x1
+ stlxp. */
+ return 732;
+ }
}
}
}
{
if (((word >> 29) & 0x1) == 0)
{
- if (((word >> 31) & 0x1) == 0)
+ if (((word >> 15) & 0x1) == 0)
{
- if (((word >> 30) & 0x1) == 0)
+ if (((word >> 31) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxxxxxxxxxxxxxx01x0010000
- stlrb. */
- return 721;
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx0xxxxxx01x0010000
+ casb. */
+ return 776;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx0xxxxxx01x0010010
+ cash. */
+ return 777;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxxxxxxxxxxxxxxxxxxxxx01x0010010
- stlrh. */
- return 727;
+ xxxxxxxxxxxxxxx0xxxxxx01x00100x1
+ cas. */
+ return 778;
}
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxxxxxxxxxxxxxx01x00100x1
- stlr. */
- return 737;
+ if (((word >> 21) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx1xxxxx001x0010000
+ stlrb. */
+ return 721;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx1xxxxx001x0010010
+ stlrh. */
+ return 727;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx1xxxxx001x00100x1
+ stlr. */
+ return 737;
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx1xxxxx101x0010000
+ caslb. */
+ return 780;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx1xxxxx101x0010010
+ caslh. */
+ return 783;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx1xxxxx101x00100x1
+ casl. */
+ return 786;
+ }
+ }
}
}
else
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxxxxxxx0xxxxx110x00100xx
- ldxp. */
- return 735;
+ if (((word >> 31) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx0xxxxx110x00100x0
+ caspa. */
+ return 789;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx0xxxxx110x00100x1
+ ldxp. */
+ return 735;
+ }
}
}
else
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxxxxxxx1xxxxx110x00100xx
- ldaxp. */
- return 736;
+ if (((word >> 31) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx1xxxxx110x00100x0
+ caspal. */
+ return 791;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx1xxxxx110x00100x1
+ ldaxp. */
+ return 736;
+ }
}
}
}
{
if (((word >> 29) & 0x1) == 0)
{
- if (((word >> 31) & 0x1) == 0)
+ if (((word >> 15) & 0x1) == 0)
{
- if (((word >> 30) & 0x1) == 0)
+ if (((word >> 31) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxxxxxxxxxxxxxx11x0010000
- ldarb. */
- return 722;
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx0xxxxxx11x0010000
+ casab. */
+ return 779;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx0xxxxxx11x0010010
+ casah. */
+ return 782;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxxxxxxxxxxxxxxxxxxxxx11x0010010
- ldarh. */
- return 728;
+ xxxxxxxxxxxxxxx0xxxxxx11x00100x1
+ casa. */
+ return 785;
}
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxxxxxxxxxxxxxx11x00100x1
- ldar. */
- return 738;
+ if (((word >> 21) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx1xxxxx011x0010000
+ ldarb. */
+ return 722;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx1xxxxx011x0010010
+ ldarh. */
+ return 728;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx1xxxxx011x00100x1
+ ldar. */
+ return 738;
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx1xxxxx111x0010000
+ casalb. */
+ return 781;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx1xxxxx111x0010010
+ casalh. */
+ return 784;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxx1xxxxx111x00100x1
+ casal. */
+ return 787;
+ }
+ }
}
}
else
{
if (((word >> 11) & 0x1) == 0)
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 21) & 0x1) == 0)
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
- if (((word >> 31) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
- if (((word >> 30) & 0x1) == 0)
+ if (((word >> 31) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxx00xxxxxxxxxx0000011100
- sturb. */
- return 693;
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00xxxxxxxxx00000011100
+ sturb. */
+ return 693;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00xxxxxxxxx00000011110
+ sturh. */
+ return 703;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxxxxxxxxx00xxxxxxxxxx0000011110
- sturh. */
- return 703;
+ xxxxxxxxxx00xxxxxxxxx000000111x1
+ stur. */
+ return 709;
}
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxx00xxxxxxxxxx00000111x1
- stur. */
- return 709;
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00xxxxxxxxx01000011100
+ ldurb. */
+ return 694;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00xxxxxxxxx01000011110
+ ldurh. */
+ return 704;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00xxxxxxxxx010000111x1
+ ldur. */
+ return 710;
+ }
}
}
else
{
- if (((word >> 31) & 0x1) == 0)
+ if (((word >> 30) & 0x1) == 0)
{
- if (((word >> 30) & 0x1) == 0)
+ if (((word >> 31) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00xxxxxxxxx0x100011100
+ ldursb. */
+ return 697;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00xxxxxxxxx0x100011101
+ ldursw. */
+ return 713;
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00xxxxxxxxx0x100011110
+ ldursh. */
+ return 707;
+ }
+ else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxxxxxxxxx00xxxxxxxxxx1000011100
- ldurb. */
- return 694;
+ xxxxxxxxxx00xxxxxxxxx0x100011111
+ prfum. */
+ return 715;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000000xxxxx10000011100
+ ldaddb. */
+ return 804;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000000xxxxx10000011110
+ ldaddh. */
+ return 805;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000000xxxxx100000111x1
+ ldadd. */
+ return 806;
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000000xxxxx10100011100
+ ldaddab. */
+ return 807;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000000xxxxx10100011110
+ ldaddah. */
+ return 810;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000000xxxxx101000111x1
+ ldadda. */
+ return 813;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000000xxxxx11000011100
+ ldaddlb. */
+ return 808;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000000xxxxx11000011110
+ ldaddlh. */
+ return 811;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000000xxxxx110000111x1
+ ldaddl. */
+ return 814;
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000000xxxxx11100011100
+ ldaddalb. */
+ return 809;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000000xxxxx11100011110
+ ldaddalh. */
+ return 812;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000000xxxxx111000111x1
+ ldaddal. */
+ return 815;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000001xxxxx10000011100
+ swpb. */
+ return 792;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000001xxxxx10000011110
+ swph. */
+ return 793;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000001xxxxx100000111x1
+ swp. */
+ return 794;
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000001xxxxx10100011100
+ swpab. */
+ return 795;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000001xxxxx10100011110
+ swpah. */
+ return 798;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000001xxxxx101000111x1
+ swpa. */
+ return 801;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000001xxxxx11000011100
+ swplb. */
+ return 796;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000001xxxxx11000011110
+ swplh. */
+ return 799;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000001xxxxx110000111x1
+ swpl. */
+ return 802;
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000001xxxxx11100011100
+ swpalb. */
+ return 797;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000001xxxxx11100011110
+ swpalh. */
+ return 800;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx000001xxxxx111000111x1
+ swpal. */
+ return 803;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00001xxxxxx10000011100
+ ldsmaxb. */
+ return 852;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00001xxxxxx10000011110
+ ldsmaxh. */
+ return 853;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00001xxxxxx100000111x1
+ ldsmax. */
+ return 854;
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00001xxxxxx10100011100
+ ldsmaxab. */
+ return 855;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00001xxxxxx10100011110
+ ldsmaxah. */
+ return 858;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00001xxxxxx101000111x1
+ ldsmaxa. */
+ return 861;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00001xxxxxx11000011100
+ ldsmaxlb. */
+ return 856;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00001xxxxxx11000011110
+ ldsmaxlh. */
+ return 859;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00001xxxxxx110000111x1
+ ldsmaxl. */
+ return 862;
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00001xxxxxx11100011100
+ ldsmaxalb. */
+ return 857;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00001xxxxxx11100011110
+ ldsmaxalh. */
+ return 860;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00001xxxxxx111000111x1
+ ldsmaxal. */
+ return 863;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00010xxxxxx10000011100
+ ldeorb. */
+ return 828;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00010xxxxxx10000011110
+ ldeorh. */
+ return 829;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00010xxxxxx100000111x1
+ ldeor. */
+ return 830;
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00010xxxxxx10100011100
+ ldeorab. */
+ return 831;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00010xxxxxx10100011110
+ ldeorah. */
+ return 834;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00010xxxxxx101000111x1
+ ldeora. */
+ return 837;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00010xxxxxx11000011100
+ ldeorlb. */
+ return 832;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00010xxxxxx11000011110
+ ldeorlh. */
+ return 835;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00010xxxxxx110000111x1
+ ldeorl. */
+ return 838;
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00010xxxxxx11100011100
+ ldeoralb. */
+ return 833;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00010xxxxxx11100011110
+ ldeoralh. */
+ return 836;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00010xxxxxx111000111x1
+ ldeoral. */
+ return 839;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00011xxxxxx10000011100
+ ldumaxb. */
+ return 876;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00011xxxxxx10000011110
+ ldumaxh. */
+ return 877;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00011xxxxxx100000111x1
+ ldumax. */
+ return 878;
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00011xxxxxx10100011100
+ ldumaxab. */
+ return 879;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00011xxxxxx10100011110
+ ldumaxah. */
+ return 882;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00011xxxxxx101000111x1
+ ldumaxa. */
+ return 885;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00011xxxxxx11000011100
+ ldumaxlb. */
+ return 880;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00011xxxxxx11000011110
+ ldumaxlh. */
+ return 883;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00011xxxxxx110000111x1
+ ldumaxl. */
+ return 886;
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00011xxxxxx11100011100
+ ldumaxalb. */
+ return 881;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00011xxxxxx11100011110
+ ldumaxalh. */
+ return 884;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00011xxxxxx111000111x1
+ ldumaxal. */
+ return 887;
+ }
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00100xxxxxx10000011100
+ ldclrb. */
+ return 816;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00100xxxxxx10000011110
+ ldclrh. */
+ return 817;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00100xxxxxx100000111x1
+ ldclr. */
+ return 818;
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00100xxxxxx10100011100
+ ldclrab. */
+ return 819;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00100xxxxxx10100011110
+ ldclrah. */
+ return 822;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00100xxxxxx101000111x1
+ ldclra. */
+ return 825;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00100xxxxxx11000011100
+ ldclrlb. */
+ return 820;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00100xxxxxx11000011110
+ ldclrlh. */
+ return 823;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00100xxxxxx110000111x1
+ ldclrl. */
+ return 826;
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00100xxxxxx11100011100
+ ldclralb. */
+ return 821;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00100xxxxxx11100011110
+ ldclralh. */
+ return 824;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00100xxxxxx111000111x1
+ ldclral. */
+ return 827;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00101xxxxxx10000011100
+ ldsminb. */
+ return 864;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00101xxxxxx10000011110
+ ldsminh. */
+ return 865;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00101xxxxxx100000111x1
+ ldsmin. */
+ return 866;
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00101xxxxxx10100011100
+ ldsminab. */
+ return 867;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00101xxxxxx10100011110
+ ldsminah. */
+ return 870;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00101xxxxxx101000111x1
+ ldsmina. */
+ return 873;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00101xxxxxx11000011100
+ ldsminlb. */
+ return 868;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00101xxxxxx11000011110
+ ldsminlh. */
+ return 871;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00101xxxxxx110000111x1
+ ldsminl. */
+ return 874;
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00101xxxxxx11100011100
+ ldsminalb. */
+ return 869;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00101xxxxxx11100011110
+ ldsminalh. */
+ return 872;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00101xxxxxx111000111x1
+ ldsminal. */
+ return 875;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00110xxxxxx10000011100
+ ldsetb. */
+ return 840;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00110xxxxxx10000011110
+ ldseth. */
+ return 841;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00110xxxxxx100000111x1
+ ldset. */
+ return 842;
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00110xxxxxx10100011100
+ ldsetab. */
+ return 843;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00110xxxxxx10100011110
+ ldsetah. */
+ return 846;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00110xxxxxx101000111x1
+ ldseta. */
+ return 849;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00110xxxxxx11000011100
+ ldsetlb. */
+ return 844;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00110xxxxxx11000011110
+ ldsetlh. */
+ return 847;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00110xxxxxx110000111x1
+ ldsetl. */
+ return 850;
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00110xxxxxx11100011100
+ ldsetalb. */
+ return 845;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00110xxxxxx11100011110
+ ldsetalh. */
+ return 848;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00110xxxxxx111000111x1
+ ldsetal. */
+ return 851;
+ }
+ }
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxx00xxxxxxxxxx1000011110
- ldurh. */
- return 704;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00111xxxxxx10000011100
+ lduminb. */
+ return 888;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00111xxxxxx10000011110
+ lduminh. */
+ return 889;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00111xxxxxx100000111x1
+ ldumin. */
+ return 890;
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00111xxxxxx10100011100
+ lduminab. */
+ return 891;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00111xxxxxx10100011110
+ lduminah. */
+ return 894;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00111xxxxxx101000111x1
+ ldumina. */
+ return 897;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00111xxxxxx11000011100
+ lduminlb. */
+ return 892;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00111xxxxxx11000011110
+ lduminlh. */
+ return 895;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00111xxxxxx110000111x1
+ lduminl. */
+ return 898;
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00111xxxxxx11100011100
+ lduminalb. */
+ return 893;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00111xxxxxx11100011110
+ lduminalh. */
+ return 896;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxx00111xxxxxx111000111x1
+ lduminal. */
+ return 899;
+ }
+ }
+ }
}
}
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxx00xxxxxxxxxx10000111x1
- ldur. */
- return 710;
- }
- }
- }
- else
- {
- if (((word >> 30) & 0x1) == 0)
- {
- if (((word >> 31) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxx00xxxxxxxxxxx100011100
- ldursb. */
- return 697;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxx00xxxxxxxxxxx100011101
- ldursw. */
- return 713;
- }
- }
- else
- {
- if (((word >> 31) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxx00xxxxxxxxxxx100011110
- ldursh. */
- return 707;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxx00xxxxxxxxxxx100011111
- prfum. */
- return 715;
- }
}
}
}
10987654321098765432109876543210
xxxxxxxxxxxxxxxxxxxxxxx10100x00x
movn. */
- return 776;
+ return 948;
}
else
{
10987654321098765432109876543210
xxxxxxxxxxxxxxxxxxxxxxx10100x01x
movz. */
- return 778;
+ return 950;
}
}
else
10987654321098765432109876543210
xxxxxxxxxxxxxxxxxxxxxxx10100x1xx
movk. */
- return 780;
+ return 952;
}
}
}
10987654321098765432109876543210
xxxxxxxxxxxx00xxxxx00xxx1x10x01x
msr. */
- return 783;
+ return 955;
}
else
{
10987654321098765432109876543210
xxxxxxxxxxxx01xxxxx00xxx1x10x01x
hint. */
- return 784;
+ return 956;
}
}
else
10987654321098765432109876543210
xxxxx00xxxxx1xxxxxx00xxx1x10x01x
dsb. */
- return 792;
+ return 964;
}
else
{
10987654321098765432109876543210
xxxxx010xxxx1xxxxxx00xxx1x10x01x
clrex. */
- return 791;
+ return 963;
}
else
{
10987654321098765432109876543210
xxxxx011xxxx1xxxxxx00xxx1x10x01x
isb. */
- return 794;
+ return 966;
}
}
}
10987654321098765432109876543210
xxxxx1xxxxxx1xxxxxx00xxx1x10x01x
dmb. */
- return 793;
+ return 965;
}
}
}
10987654321098765432109876543210
xxxxxxxxxxxxxxxxxxx100xx1x10x01x
sys. */
- return 795;
+ return 967;
}
else
{
10987654321098765432109876543210
xxxxxxxxxxxxxxxxxxx101xx1x10x01x
sysl. */
- return 801;
+ return 973;
}
}
}
10987654321098765432109876543210
xxxxxxxxxxxxxxxxxxxx10xx1x10x01x
msr. */
- return 800;
+ return 972;
}
else
{
10987654321098765432109876543210
xxxxxxxxxxxxxxxxxxxx11xx1x10x01x
mrs. */
- return 802;
+ return 974;
}
}
}
10987654321098765432109876543210
xxxxxxxxxxxxxxxxxxxxxxxx0110x1xx
tbz. */
- return 803;
+ return 975;
}
}
else
10987654321098765432109876543210
xxxxxxxxxxxxxxxxxxxxxxxx1110x1xx
tbnz. */
- return 804;
+ return 976;
}
}
}
case 766: value = 768; break; /* orr --> uxtw. */
case 769: value = 770; break; /* orn --> mvn. */
case 773: value = 774; break; /* ands --> tst. */
- case 776: value = 777; break; /* movn --> mov. */
- case 778: value = 779; break; /* movz --> mov. */
- case 784: value = 790; break; /* hint --> sevl. */
- case 795: value = 799; break; /* sys --> tlbi. */
+ case 804: value = 900; break; /* ldaddb --> staddb. */
+ case 805: value = 901; break; /* ldaddh --> staddh. */
+ case 806: value = 902; break; /* ldadd --> stadd. */
+ case 808: value = 903; break; /* ldaddlb --> staddlb. */
+ case 811: value = 904; break; /* ldaddlh --> staddlh. */
+ case 814: value = 905; break; /* ldaddl --> staddl. */
+ case 816: value = 906; break; /* ldclrb --> stclrb. */
+ case 817: value = 907; break; /* ldclrh --> stclrh. */
+ case 818: value = 908; break; /* ldclr --> stclr. */
+ case 820: value = 909; break; /* ldclrlb --> stclrlb. */
+ case 823: value = 910; break; /* ldclrlh --> stclrlh. */
+ case 826: value = 911; break; /* ldclrl --> stclrl. */
+ case 828: value = 912; break; /* ldeorb --> steorb. */
+ case 829: value = 913; break; /* ldeorh --> steorh. */
+ case 830: value = 914; break; /* ldeor --> steor. */
+ case 832: value = 915; break; /* ldeorlb --> steorlb. */
+ case 835: value = 916; break; /* ldeorlh --> steorlh. */
+ case 838: value = 917; break; /* ldeorl --> steorl. */
+ case 840: value = 918; break; /* ldsetb --> stsetb. */
+ case 841: value = 919; break; /* ldseth --> stseth. */
+ case 842: value = 920; break; /* ldset --> stset. */
+ case 844: value = 921; break; /* ldsetlb --> stsetlb. */
+ case 847: value = 922; break; /* ldsetlh --> stsetlh. */
+ case 850: value = 923; break; /* ldsetl --> stsetl. */
+ case 852: value = 924; break; /* ldsmaxb --> stsmaxb. */
+ case 853: value = 925; break; /* ldsmaxh --> stsmaxh. */
+ case 854: value = 926; break; /* ldsmax --> stsmax. */
+ case 856: value = 927; break; /* ldsmaxlb --> stsmaxlb. */
+ case 859: value = 928; break; /* ldsmaxlh --> stsmaxlh. */
+ case 862: value = 929; break; /* ldsmaxl --> stsmaxl. */
+ case 864: value = 930; break; /* ldsminb --> stsminb. */
+ case 865: value = 931; break; /* ldsminh --> stsminh. */
+ case 866: value = 932; break; /* ldsmin --> stsmin. */
+ case 868: value = 933; break; /* ldsminlb --> stsminlb. */
+ case 871: value = 934; break; /* ldsminlh --> stsminlh. */
+ case 874: value = 935; break; /* ldsminl --> stsminl. */
+ case 876: value = 936; break; /* ldumaxb --> stumaxb. */
+ case 877: value = 937; break; /* ldumaxh --> stumaxh. */
+ case 878: value = 938; break; /* ldumax --> stumax. */
+ case 880: value = 939; break; /* ldumaxlb --> stumaxlb. */
+ case 883: value = 940; break; /* ldumaxlh --> stumaxlh. */
+ case 886: value = 941; break; /* ldumaxl --> stumaxl. */
+ case 888: value = 942; break; /* lduminb --> stuminb. */
+ case 889: value = 943; break; /* lduminh --> stuminh. */
+ case 890: value = 944; break; /* ldumin --> stumin. */
+ case 892: value = 945; break; /* lduminlb --> stuminlb. */
+ case 895: value = 946; break; /* lduminlh --> stuminlh. */
+ case 898: value = 947; break; /* lduminl --> stuminl. */
+ case 948: value = 949; break; /* movn --> mov. */
+ case 950: value = 951; break; /* movz --> mov. */
+ case 956: value = 962; break; /* hint --> sevl. */
+ case 967: value = 971; break; /* sys --> tlbi. */
default: return NULL;
}
case 527: value = 526; break; /* cset --> cinc. */
case 530: value = 529; break; /* csetm --> cinv. */
case 768: value = 767; break; /* uxtw --> mov. */
- case 790: value = 789; break; /* sevl --> sev. */
- case 789: value = 788; break; /* sev --> wfi. */
- case 788: value = 787; break; /* wfi --> wfe. */
- case 787: value = 786; break; /* wfe --> yield. */
- case 786: value = 785; break; /* yield --> nop. */
- case 799: value = 798; break; /* tlbi --> ic. */
- case 798: value = 797; break; /* ic --> dc. */
- case 797: value = 796; break; /* dc --> at. */
+ case 962: value = 961; break; /* sevl --> sev. */
+ case 961: value = 960; break; /* sev --> wfi. */
+ case 960: value = 959; break; /* wfi --> wfe. */
+ case 959: value = 958; break; /* wfe --> yield. */
+ case 958: value = 957; break; /* yield --> nop. */
+ case 971: value = 970; break; /* tlbi --> ic. */
+ case 970: value = 969; break; /* ic --> dc. */
+ case 969: value = 968; break; /* dc --> at. */
default: return NULL;
}
case 7:
case 9:
case 10:
- case 13:
case 14:
case 15:
case 16:
- case 18:
+ case 17:
case 19:
case 20:
case 21:
case 24:
case 25:
case 26:
- case 34:
+ case 27:
case 35:
+ case 36:
return aarch64_ext_regno (self, info, code, inst);
case 8:
return aarch64_ext_regrt_sysins (self, info, code, inst);
case 11:
- return aarch64_ext_reg_extended (self, info, code, inst);
+ return aarch64_ext_regno_pair (self, info, code, inst);
case 12:
+ return aarch64_ext_reg_extended (self, info, code, inst);
+ case 13:
return aarch64_ext_reg_shifted (self, info, code, inst);
- case 17:
+ case 18:
return aarch64_ext_ft (self, info, code, inst);
- case 27:
case 28:
case 29:
- return aarch64_ext_reglane (self, info, code, inst);
case 30:
- return aarch64_ext_reglist (self, info, code, inst);
+ return aarch64_ext_reglane (self, info, code, inst);
case 31:
- return aarch64_ext_ldst_reglist (self, info, code, inst);
+ return aarch64_ext_reglist (self, info, code, inst);
case 32:
- return aarch64_ext_ldst_reglist_r (self, info, code, inst);
+ return aarch64_ext_ldst_reglist (self, info, code, inst);
case 33:
+ return aarch64_ext_ldst_reglist_r (self, info, code, inst);
+ case 34:
return aarch64_ext_ldst_elemlist (self, info, code, inst);
- case 36:
- case 45:
+ case 37:
case 46:
case 47:
case 48:
case 55:
case 56:
case 57:
- case 65:
+ case 58:
case 66:
case 67:
case 68:
case 69:
+ case 70:
return aarch64_ext_imm (self, info, code, inst);
- case 37:
case 38:
- return aarch64_ext_advsimd_imm_shift (self, info, code, inst);
case 39:
+ return aarch64_ext_advsimd_imm_shift (self, info, code, inst);
case 40:
case 41:
- return aarch64_ext_advsimd_imm_modified (self, info, code, inst);
case 42:
+ return aarch64_ext_advsimd_imm_modified (self, info, code, inst);
+ case 43:
return aarch64_ext_shll_imm (self, info, code, inst);
- case 58:
- return aarch64_ext_limm (self, info, code, inst);
case 59:
- return aarch64_ext_aimm (self, info, code, inst);
+ return aarch64_ext_limm (self, info, code, inst);
case 60:
- return aarch64_ext_imm_half (self, info, code, inst);
+ return aarch64_ext_aimm (self, info, code, inst);
case 61:
+ return aarch64_ext_imm_half (self, info, code, inst);
+ case 62:
return aarch64_ext_fbits (self, info, code, inst);
- case 63:
case 64:
+ case 65:
return aarch64_ext_cond (self, info, code, inst);
- case 70:
- case 76:
- return aarch64_ext_addr_simple (self, info, code, inst);
case 71:
- return aarch64_ext_addr_regoff (self, info, code, inst);
+ case 77:
+ return aarch64_ext_addr_simple (self, info, code, inst);
case 72:
+ return aarch64_ext_addr_regoff (self, info, code, inst);
case 73:
case 74:
- return aarch64_ext_addr_simm (self, info, code, inst);
case 75:
+ return aarch64_ext_addr_simm (self, info, code, inst);
+ case 76:
return aarch64_ext_addr_uimm12 (self, info, code, inst);
- case 77:
- return aarch64_ext_simd_addr_post (self, info, code, inst);
case 78:
- return aarch64_ext_sysreg (self, info, code, inst);
+ return aarch64_ext_simd_addr_post (self, info, code, inst);
case 79:
- return aarch64_ext_pstatefield (self, info, code, inst);
+ return aarch64_ext_sysreg (self, info, code, inst);
case 80:
+ return aarch64_ext_pstatefield (self, info, code, inst);
case 81:
case 82:
case 83:
- return aarch64_ext_sysins_op (self, info, code, inst);
case 84:
+ return aarch64_ext_sysins_op (self, info, code, inst);
case 85:
- return aarch64_ext_barrier (self, info, code, inst);
case 86:
+ return aarch64_ext_barrier (self, info, code, inst);
+ case 87:
return aarch64_ext_prfop (self, info, code, inst);
default: assert (0); abort ();
}
return 1;
}
+int
+aarch64_ext_regno_pair (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info,
+ const aarch64_insn code ATTRIBUTE_UNUSED,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ assert (info->idx == 1
+ || info->idx ==3);
+ info->reg.regno = inst->operands[info->idx - 1].reg.regno + 1;
+ return 1;
+}
+
/* e.g. IC <ic_op>{, <Xt>}. */
int
aarch64_ext_regrt_sysins (const aarch64_operand *self, aarch64_opnd_info *info,
&& extract_field (FLD_N, inst->value, 0) != value)
return 0;
}
+ /* 'sf' field. */
+ if (inst->opcode->flags & F_LSE_SZ)
+ {
+ idx = select_operand_for_sf_field_coding (inst->opcode);
+ value = extract_field (FLD_lse_sz, inst->value, 0);
+ inst->operands[idx].qualifier = get_greg_qualifier_from_value (value);
+ }
/* size:Q fields. */
if (inst->opcode->flags & F_SIZEQ)
return decode_sizeq (inst);
const aarch64_insn, const aarch64_inst *)
AARCH64_DECL_OPD_EXTRACTOR (ext_regno);
+AARCH64_DECL_OPD_EXTRACTOR (ext_regno_pair);
AARCH64_DECL_OPD_EXTRACTOR (ext_regrt_sysins);
AARCH64_DECL_OPD_EXTRACTOR (ext_reglane);
AARCH64_DECL_OPD_EXTRACTOR (ext_reglist);
{AARCH64_OPND_CLASS_INT_REG, "Rt_SYS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"},
{AARCH64_OPND_CLASS_INT_REG, "Rd_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "an integer or stack pointer register"},
{AARCH64_OPND_CLASS_INT_REG, "Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer or stack pointer register"},
+ {AARCH64_OPND_CLASS_INT_REG, "PAIRREG", OPD_F_HAS_EXTRACTOR, {}, "the second reg of a pair"},
{AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_EXT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an integer register with optional extension"},
{AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_SFT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an integer register with optional shift"},
{AARCH64_OPND_CLASS_FP_REG, "Fd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a floating-point register"},
12,
510,
511,
- 776,
- 778,
- 780,
+ 948,
+ 950,
+ 952,
760,
- 779,
- 777,
+ 951,
+ 949,
259,
499,
509,
{ 11, 1 }, /* index: in ld/st inst deciding the pre/post-index. */
{ 24, 1 }, /* index2: in ld/st pair inst deciding the pre/post-index. */
{ 31, 1 }, /* sf: in integer data processing instructions. */
+ { 30, 1 }, /* lse_size: in LSE extension atomic instructions. */
{ 11, 1 }, /* H: in advsimd scalar x indexed element instructions. */
{ 21, 1 }, /* L: in advsimd scalar x indexed element instructions. */
{ 20, 1 }, /* M: in advsimd scalar x indexed element instructions. */
switch (aarch64_operands[type].op_class)
{
case AARCH64_OPND_CLASS_INT_REG:
+ /* Check pair reg constraints for cas* instructions. */
+ if (type == AARCH64_OPND_PAIRREG)
+ {
+ assert (idx == 1 || idx == 3);
+ if (opnds[idx - 1].reg.regno % 2 != 0)
+ {
+ set_syntax_error (mismatch_detail, idx - 1,
+ _("reg pair must start from even reg"));
+ return 0;
+ }
+ if (opnds[idx].reg.regno != opnds[idx - 1].reg.regno + 1)
+ {
+ set_syntax_error (mismatch_detail, idx,
+ _("reg pair must be contiguous"));
+ return 0;
+ }
+ break;
+ }
+
/* <Xt> may be optional in some IC and TLBI instructions. */
if (type == AARCH64_OPND_Rt_SYS)
{
case AARCH64_OPND_Rs:
case AARCH64_OPND_Ra:
case AARCH64_OPND_Rt_SYS:
+ case AARCH64_OPND_PAIRREG:
/* The optional-ness of <Xt> in e.g. IC <ic_op>{, <Xt>} is determined by
the <ic_op>, therefore we we use opnd->present to override the
generic optional-ness information. */
FLD_index,
FLD_index2,
FLD_sf,
+ FLD_lse_sz,
FLD_H,
FLD_L,
FLD_M,
QLF3(X, X, NIL), \
}
+/* e.g. CASP <Xt1>, <Xt1+1>, <Xt2>, <Xt2+1>, [<Xn|SP>{,#0}]. */
+#define QL_R4NIL \
+{ \
+ QLF5(W, W, W, W, NIL), \
+ QLF5(X, X, X, X, NIL), \
+}
+
/* e.g. STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */
#define QL_R3_LDST_EXC \
{ \
AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0);
static const aarch64_feature_set aarch64_feature_crc =
AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0);
+static const aarch64_feature_set aarch64_feature_lse =
+ AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
#define SIMD &aarch64_feature_simd
#define CRYPTO &aarch64_feature_crypto
#define CRC &aarch64_feature_crc
+#define LSE &aarch64_feature_lse
struct aarch64_opcode aarch64_opcode_table[] =
{
{"ldxrb", 0x85f7c00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
{"ldaxrb", 0x85ffc00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
{"stlrb", 0x89ffc00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
- {"ldarb", 0x8dffc00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
+ {"ldarb", 0x8dffc00, 0xffeffc00, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
{"stxrh", 0x48007c00, 0xffe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
{"stlxrh", 0x4800fc00, 0xffe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
{"ldxrh", 0x485f7c00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
{"ldaxrh", 0x485ffc00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
{"stlrh", 0x489ffc00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
- {"ldarh", 0x48dffc00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
+ {"ldarh", 0x48dffc00, 0xffeffc00, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
{"stxr", 0x88007c00, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q},
{"stlxr", 0x8800fc00, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q},
{"stxp", 0x88200000, 0xbfe08000, ldstexcl, 0, CORE, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q},
{"ldxp", 0x887f0000, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q},
{"ldaxp", 0x887f8000, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q},
{"stlr", 0x889ffc00, 0xbfe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
- {"ldar", 0x88dffc00, 0xbfe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
+ {"ldar", 0x88dffc00, 0xbfeffc00, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
/* Load/store no-allocate pair (offset). */
{"stnp", 0x28000000, 0x7fc00000, ldstnapair_offs, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
{"ldnp", 0x28400000, 0x7fc00000, ldstnapair_offs, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
{"ands", 0x6a000000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
{"tst", 0x6a00001f, 0x7f20001f, log_shift, 0, CORE, OP2 (Rn, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF},
{"bics", 0x6a200000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
+ /* LSE extension (atomic). */
+ {"casb", 0x8a07c00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"cash", 0x48a07c00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"cas", 0x88a07c00, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
+ {"casab", 0x8e07c00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"caslb", 0x8a0fc00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"casalb", 0x8e0fc00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"casah", 0x48e07c00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"caslh", 0x48a0fc00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"casalh", 0x48e0fc00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"casa", 0x88e07c00, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
+ {"casl", 0x88a0fc00, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
+ {"casal", 0x88e0fc00, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
+ {"casp", 0x8207c00, 0xbfe0fc00, lse_atomic, 0, LSE, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ},
+ {"caspa", 0x8607c00, 0xbfe0fc00, lse_atomic, 0, LSE, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ},
+ {"caspl", 0x820fc00, 0xbfe0fc00, lse_atomic, 0, LSE, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ},
+ {"caspal", 0x860fc00, 0xbfe0fc00, lse_atomic, 0, LSE, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ},
+ {"swpb", 0x38208000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"swph", 0x78208000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"swp", 0xb8208000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
+ {"swpab", 0x38a08000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"swplb", 0x38608000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"swpalb", 0x38e08000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"swpah", 0x78a08000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"swplh", 0x78608000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"swpalh", 0x78e08000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"swpa", 0xb8a08000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
+ {"swpl", 0xb8608000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
+ {"swpal", 0xb8e08000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
+ {"ldaddb", 0x38200000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"ldaddh", 0x78200000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"ldadd", 0xb8200000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
+ {"ldaddab", 0x38a00000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldaddlb", 0x38600000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"ldaddalb", 0x38e00000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldaddah", 0x78a00000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldaddlh", 0x78600000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"ldaddalh", 0x78e00000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldadda", 0xb8a00000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
+ {"ldaddl", 0xb8600000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
+ {"ldaddal", 0xb8e00000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
+ {"ldclrb", 0x38201000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"ldclrh", 0x78201000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"ldclr", 0xb8201000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
+ {"ldclrab", 0x38a01000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldclrlb", 0x38601000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"ldclralb", 0x38e01000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldclrah", 0x78a01000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldclrlh", 0x78601000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"ldclralh", 0x78e01000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldclra", 0xb8a01000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
+ {"ldclrl", 0xb8601000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
+ {"ldclral", 0xb8e01000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
+ {"ldeorb", 0x38202000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"ldeorh", 0x78202000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"ldeor", 0xb8202000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
+ {"ldeorab", 0x38a02000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldeorlb", 0x38602000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"ldeoralb", 0x38e02000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldeorah", 0x78a02000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldeorlh", 0x78602000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"ldeoralh", 0x78e02000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldeora", 0xb8a02000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
+ {"ldeorl", 0xb8602000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
+ {"ldeoral", 0xb8e02000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
+ {"ldsetb", 0x38203000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"ldseth", 0x78203000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"ldset", 0xb8203000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
+ {"ldsetab", 0x38a03000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldsetlb", 0x38603000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"ldsetalb", 0x38e03000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldsetah", 0x78a03000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldsetlh", 0x78603000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"ldsetalh", 0x78e03000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldseta", 0xb8a03000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
+ {"ldsetl", 0xb8603000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
+ {"ldsetal", 0xb8e03000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
+ {"ldsmaxb", 0x38204000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"ldsmaxh", 0x78204000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"ldsmax", 0xb8204000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
+ {"ldsmaxab", 0x38a04000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldsmaxlb", 0x38604000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"ldsmaxalb", 0x38e04000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldsmaxah", 0x78a04000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldsmaxlh", 0x78604000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"ldsmaxalh", 0x78e04000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldsmaxa", 0xb8a04000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
+ {"ldsmaxl", 0xb8604000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
+ {"ldsmaxal", 0xb8e04000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
+ {"ldsminb", 0x38205000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"ldsminh", 0x78205000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"ldsmin", 0xb8205000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
+ {"ldsminab", 0x38a05000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldsminlb", 0x38605000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"ldsminalb", 0x38e05000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldsminah", 0x78a05000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldsminlh", 0x78605000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"ldsminalh", 0x78e05000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldsmina", 0xb8a05000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
+ {"ldsminl", 0xb8605000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
+ {"ldsminal", 0xb8e05000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
+ {"ldumaxb", 0x38206000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"ldumaxh", 0x78206000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"ldumax", 0xb8206000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
+ {"ldumaxab", 0x38a06000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldumaxlb", 0x38606000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"ldumaxalb", 0x38e06000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldumaxah", 0x78a06000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldumaxlh", 0x78606000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"ldumaxalh", 0x78e06000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldumaxa", 0xb8a06000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
+ {"ldumaxl", 0xb8606000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
+ {"ldumaxal", 0xb8e06000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
+ {"lduminb", 0x38207000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"lduminh", 0x78207000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"ldumin", 0xb8207000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
+ {"lduminab", 0x38a07000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"lduminlb", 0x38607000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"lduminalb", 0x38e07000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"lduminah", 0x78a07000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"lduminlh", 0x78607000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
+ {"lduminalh", 0x78e07000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
+ {"ldumina", 0xb8a07000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
+ {"lduminl", 0xb8607000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
+ {"lduminal", 0xb8e07000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
+ {"staddb", 0x3820001f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"staddh", 0x7820001f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"stadd", 0xb820001f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
+ {"staddlb", 0x3860001f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"staddlh", 0x7860001f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"staddl", 0xb860001f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
+ {"stclrb", 0x3820101f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"stclrh", 0x7820101f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"stclr", 0xb820101f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
+ {"stclrlb", 0x3860101f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"stclrlh", 0x7860101f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"stclrl", 0xb860101f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
+ {"steorb", 0x3820201f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"steorh", 0x7820201f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"steor", 0xb820201f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
+ {"steorlb", 0x3860201f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"steorlh", 0x7860201f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"steorl", 0xb860201f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
+ {"stsetb", 0x3820301f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"stseth", 0x7820301f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"stset", 0xb820301f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
+ {"stsetlb", 0x3860301f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"stsetlh", 0x7860301f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"stsetl", 0xb860301f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
+ {"stsmaxb", 0x3820401f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"stsmaxh", 0x7820401f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"stsmax", 0xb820401f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
+ {"stsmaxlb", 0x3860401f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"stsmaxlh", 0x7860401f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"stsmaxl", 0xb860401f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
+ {"stsminb", 0x3820501f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"stsminh", 0x7820501f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"stsmin", 0xb820501f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
+ {"stsminlb", 0x3860501f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"stsminlh", 0x7860501f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"stsminl", 0xb860501f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
+ {"stumaxb", 0x3820601f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"stumaxh", 0x7820601f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"stumax", 0xb820601f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
+ {"stumaxlb", 0x3860601f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"stumaxlh", 0x7860601f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"stumaxl", 0xb860601f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
+ {"stuminb", 0x3820701f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"stuminh", 0x7820701f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"stumin", 0xb820701f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
+ {"stuminlb", 0x3860701f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"stuminlh", 0x7860701f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
+ {"stuminl", 0xb860701f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
/* Move wide (immediate). */
{"movn", 0x12800000, 0x7f800000, movewide, OP_MOVN, CORE, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS},
{"mov", 0x12800000, 0x7f800000, movewide, OP_MOV_IMM_WIDEN, CORE, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_CONV},
"an integer or stack pointer register") \
Y(INT_REG, regno, "Rn_SP", OPD_F_MAYBE_SP, F(FLD_Rn), \
"an integer or stack pointer register") \
+ X(INT_REG, 0, ext_regno_pair, "PAIRREG", 0, F(), \
+ "the second reg of a pair") \
Y(MODIFIED_REG, reg_extended, "Rm_EXT", 0, F(), \
"an integer register with optional extension") \
Y(MODIFIED_REG, reg_shifted, "Rm_SFT", 0, F(), \
projects / platform / upstream / binutils.git / commitdiff