[PORT FROM R2] atomisp: do not restart ISP from ISR when next stage is accel fw
authorDavid Cohen <david.a.cohen@intel.com>
Fri, 30 Dec 2011 20:43:30 +0000 (22:43 +0200)
committerbuildbot <buildbot@intel.com>
Thu, 19 Jan 2012 11:57:48 +0000 (03:57 -0800)
BZ: 20531

Accel fw always do memory (de)allocation when starting. For such reason,
accel stages cannot be started from atomic context.

Change-Id: Ifefb7fe6a076bb9f62430a50f8bbd80dadf2f308
Orig-Change-Id: Ibd982ea9e90363f0f9b816c57157d9b5e1ec525a
Signed-off-by: David Cohen <david.a.cohen@intel.com>
Reviewed-on: http://android.intel.com:8080/30237
Reviewed-by: Wang, Wen W <wen.w.wang@intel.com>
Reviewed-by: Koski, Anttu <anttu.koski@intel.com>
Reviewed-by: Von Oerthel, Jurgen <jurgen.von.oerthel@intel.com>
Tested-by: Koski, Anttu <anttu.koski@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>
Reviewed-on: http://android.intel.com:8080/32443
Reviewed-by: Lampila, KalleX <kallex.lampila@intel.com>
Tested-by: Lampila, KalleX <kallex.lampila@intel.com>
drivers/media/video/atomisp/atomisp_cmd.c
drivers/media/video/atomisp/css/sh_css.c
drivers/media/video/atomisp/css/sh_css.h

index 8e153ca..d335a1c 100644 (file)
@@ -321,7 +321,9 @@ irqreturn_t atomisp_isr(int irq, void *dev)
 
        /* We're fine to proceed in atomic context */
        if (irq_infos & SH_CSS_IRQ_INFO_START_NEXT_STAGE) {
-               sh_css_start_next_stage();
+               if (sh_css_next_stage_is_acc() ||
+                   sh_css_start_next_stage())
+                       goto no_frame_done;
                irq_infos &= ~SH_CSS_IRQ_INFO_START_NEXT_STAGE;
        }
 
index 6de9c31..547b321 100644 (file)
@@ -1440,6 +1440,27 @@ sh_css_terminate_firmware(void)
 #endif
 }
 
+bool
+sh_css_next_stage_is_acc(void)
+{
+       struct sh_css_pipeline_stage *stage;
+       struct sh_css_pipeline *pipeline;
+
+       if (my_css.mode == sh_css_mode_preview)
+               pipeline = &my_css.preview_settings.pipeline;
+       else if (my_css.mode == sh_css_mode_video)
+               pipeline = &my_css.video_settings.pipeline;
+       else
+               pipeline = &my_css.capture_settings.pipeline;
+
+       if (pipeline->current_stage)
+               stage = pipeline->current_stage->next;
+       else
+               stage = pipeline->stages;
+
+       return stage != NULL ? !!stage->firmware : false;
+}
+
 static enum sh_css_err
 sh_css_pipeline_start_next_stage(struct sh_css_pipeline *me)
 {
index 490c8df..468ea65 100644 (file)
@@ -85,6 +85,9 @@ sh_css_rx_clear_interrupt_info(unsigned int irq_infos);
 void
 sh_css_terminate_firmware(void);
 
+bool
+sh_css_next_stage_is_acc(void);
+
 enum sh_css_err
 sh_css_start_next_stage(void);