[RISCV][Docs] Add description about inline asm constraint for V.

Add inline asm constraint 'vr' for vector registers and 'vm' for vector
mask registers.

Differential Revision: https://reviews.llvm.org/D106633

diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index d5e4e59..d91464a 100644 (file)
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -4779,6 +4779,8 @@ RISC-V:
 - ``f``: A 32- or 64-bit floating-point register (requires F or D extension).
 - ``r``: A 32- or 64-bit general-purpose register (depending on the platform
   ``XLEN``).
+- ``vr``: A vector register. (requires V extension).
+- ``vm``: A vector mask register. (requires V extension).
 
 Sparc: