const unsigned RegisterBankInfo::DefaultMappingID = UINT_MAX;
const unsigned RegisterBankInfo::InvalidMappingID = UINT_MAX - 1;
-/// Get the size in bits of the \p OpIdx-th operand of \p MI.
+/// Get the size in bits of the \p Reg.
///
-/// \pre \p MI is part of a basic block and this basic block is part
-/// of a function.
-static unsigned getSizeInBits(const MachineInstr &MI, unsigned OpIdx) {
- unsigned Reg = MI.getOperand(OpIdx).getReg();
+/// \pre \p Reg != 0 (NoRegister).
+static unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI,
+ const TargetRegisterInfo &TRI) {
const TargetRegisterClass *RC = nullptr;
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
- const TargetSubtargetInfo &STI =
- MI.getParent()->getParent()->getSubtarget();
- const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
// The size is not directly available for physical registers.
// Instead, we need to access a register class that contains Reg and
// get the size of that register class.
RC = TRI.getMinimalPhysRegClass(Reg);
} else {
- const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
unsigned RegSize = MRI.getSize(Reg);
// If Reg is not a generic register, query the register class to
// get its size.
if (RegSize)
return RegSize;
+ // Since Reg is not a generic register, it must have a register class.
RC = MRI.getRegClass(Reg);
}
assert(RC && "Unable to deduce the register class");
// Just map the register class to a register bank.
RegisterBankInfo::InstructionMapping Mapping(DefaultMappingID, /*Cost*/ 1,
MI.getNumOperands());
- const TargetSubtargetInfo &STI =
- MI.getParent()->getParent()->getSubtarget();
+ const MachineFunction &MF = *MI.getParent()->getParent();
+ const TargetSubtargetInfo &STI = MF.getSubtarget();
const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
const TargetInstrInfo &TII = *STI.getInstrInfo();
+ const MachineRegisterInfo &MRI = MF.getRegInfo();
for (unsigned OpIdx = 0, End = MI.getNumOperands(); OpIdx != End; ++OpIdx) {
const MachineOperand &MO = MI.getOperand(OpIdx);
- if (!MO.getReg())
+ if (!MO.isReg())
+ continue;
+ unsigned Reg = MO.getReg();
+ if (!Reg)
continue;
// Since this is a target instruction, the operand must have a register
// class constraint.
// Build the value mapping.
const RegisterBank &RegBank = getRegBankFromRegClass(*RC);
- unsigned RegSize = getSizeInBits(MI, OpIdx);
+ unsigned RegSize = getSizeInBits(Reg, MRI, TRI);
assert(RegSize <= RegBank.getSize() && "Register bank too small");
// Assume the value is mapped in one register that lives in the
// register bank that covers RC.
// Check the constructor invariant.
assert(NumOperands == MI.getNumOperands() &&
"NumOperands must match, see constructor");
+ assert(MI.getParent() && MI.getParent()->getParent() &&
+ "MI must be connected to a MachineFunction");
+ const MachineFunction &MF = *MI.getParent()->getParent();
+ const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
+ const MachineRegisterInfo &MRI = MF.getRegInfo();
+
for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
const MachineOperand &MO = MI.getOperand(Idx);
const RegisterBankInfo::ValueMapping &MOMapping = getOperandMapping(Idx);
"We should not care about non-reg mapping");
continue;
}
+ unsigned Reg = MO.getReg();
+ if (!Reg)
+ continue;
// Register size in bits.
// This size must match what the mapping expects.
- unsigned RegSize = getSizeInBits(MI, Idx);
+ unsigned RegSize = getSizeInBits(Reg, MRI, TRI);
MOMapping.verify(RegSize);
}
}