drm/msm/dsi: Add support for qcm2290 dsi controller

QCM2290 MDSS includes a Qualcomm DSI controller v2.4.1. Since this
controller version is not SoC specific, and already assigned to sc7180
for auto configuration, we rely on DSI block specific compatible
string "qcom,dsi-ctrl-6g-qcm2290", and use the device's data to point
to the right dsi config handler.

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/474088/
Link: https://lore.kernel.org/r/1644853060-12222-2-git-send-email-loic.poulain@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
index e61a8ee..c12e66a 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/dsi.c
+++ b/drivers/gpu/drm/msm/dsi/dsi.c
@@ -4,6 +4,7 @@
  */
 
 #include "dsi.h"
+#include "dsi_cfg.h"
 
 struct drm_encoder *msm_dsi_get_encoder(struct msm_dsi *msm_dsi)
 {
@@ -176,6 +177,7 @@ static int dsi_dev_remove(struct platform_device *pdev)
 
 static const struct of_device_id dt_match[] = {
        { .compatible = "qcom,mdss-dsi-ctrl", .data = NULL /* autodetect cfg */ },
+       { .compatible = "qcom,dsi-ctrl-6g-qcm2290", .data = &qcm2290_dsi_cfg_handler },
        {}
 };
 

diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
index 96bbc8b..2c23324 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
@@ -213,6 +213,24 @@ static const struct msm_dsi_config sc7280_dsi_cfg = {
        .num_dsi = 1,
 };
 
+static const char * const dsi_qcm2290_bus_clk_names[] = {
+       "iface", "bus",
+};
+
+static const struct msm_dsi_config qcm2290_dsi_cfg = {
+       .io_offset = DSI_6G_REG_SHIFT,
+       .reg_cfg = {
+               .num = 1,
+               .regs = {
+                       {"vdda", 21800, 4 },    /* 1.2 V */
+               },
+       },
+       .bus_clk_names = dsi_qcm2290_bus_clk_names,
+       .num_bus_clks = ARRAY_SIZE(dsi_qcm2290_bus_clk_names),
+       .io_start = { 0x5e94000 },
+       .num_dsi = 1,
+};
+
 static const struct msm_dsi_host_cfg_ops msm_dsi_v2_host_ops = {
        .link_clk_set_rate = dsi_link_clk_set_rate_v2,
        .link_clk_enable = dsi_link_clk_enable_v2,
@@ -300,3 +318,8 @@ const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)
        return cfg_hnd;
 }
 
+/*  Non autodetect configs */
+const struct msm_dsi_cfg_handler qcm2290_dsi_cfg_handler = {
+       .cfg = &qcm2290_dsi_cfg,
+       .ops = &msm_dsi_6g_v2_host_ops,
+};

diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
index 41e99a9..fe54a99 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
@@ -60,5 +60,8 @@ struct msm_dsi_cfg_handler {
 
 const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor);
 
+/* Non autodetect configs */
+extern const struct msm_dsi_cfg_handler qcm2290_dsi_cfg_handler;
+
 #endif /* __MSM_DSI_CFG_H__ */