gcc/
authoryroux <yroux@138bc75d-0d04-0410-961f-82ee72b054a4>
Wed, 3 Sep 2014 07:23:01 +0000 (07:23 +0000)
committeryroux <yroux@138bc75d-0d04-0410-961f-82ee72b054a4>
Wed, 3 Sep 2014 07:23:01 +0000 (07:23 +0000)
2014-09-03  Yvan Roux  <yvan.roux@linaro.org>

Backport from trunk r214526.
2014-08-26  Joseph Myers  <joseph@codesourcery.com>

PR target/60606
PR target/61330
* varasm.c (make_decl_rtl): Clear DECL_ASSEMBLER_NAME and
DECL_HARD_REGISTER and return for invalid register specifications.
* cfgexpand.c (expand_one_var): If expand_one_hard_reg_var clears
DECL_HARD_REGISTER, call expand_one_error_var.
* config/arm/arm.c (arm_hard_regno_mode_ok): Do not allow
CC_REGNUM with non-MODE_CC modes.
(arm_regno_class): Return NO_REGS for PC_REGNUM.

gcc/testsuite/
2014-09-03  Yvan Roux  <yvan.roux@linaro.org>

Backport from trunk r214526.
2014-08-26  Joseph Myers  <joseph@codesourcery.com>

PR target/60606
PR target/61330
* gcc.dg/torture/pr60606-1.c, gcc.target/arm/pr60606-2.c,
gcc.target/arm/pr60606-3.c, gcc.target/arm/pr60606-4.c: New tests.

git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@214847 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog.linaro
gcc/cfgexpand.c
gcc/config/arm/arm.c
gcc/testsuite/ChangeLog.linaro
gcc/testsuite/gcc.dg/torture/pr60606-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/arm/pr60606-2.c [new file with mode: 0644]
gcc/testsuite/gcc.target/arm/pr60606-3.c [new file with mode: 0644]
gcc/testsuite/gcc.target/arm/pr60606-4.c [new file with mode: 0644]
gcc/varasm.c

index eaa88b6..9ae3b48 100644 (file)
@@ -1,5 +1,20 @@
 2014-09-03  Yvan Roux  <yvan.roux@linaro.org>
 
+       Backport from trunk r214526.
+       2014-08-26  Joseph Myers  <joseph@codesourcery.com>
+
+       PR target/60606
+       PR target/61330
+       * varasm.c (make_decl_rtl): Clear DECL_ASSEMBLER_NAME and
+       DECL_HARD_REGISTER and return for invalid register specifications.
+       * cfgexpand.c (expand_one_var): If expand_one_hard_reg_var clears
+       DECL_HARD_REGISTER, call expand_one_error_var.
+       * config/arm/arm.c (arm_hard_regno_mode_ok): Do not allow
+       CC_REGNUM with non-MODE_CC modes.
+       (arm_regno_class): Return NO_REGS for PC_REGNUM.
+
+2014-09-03  Yvan Roux  <yvan.roux@linaro.org>
+
        Backport from trunk r214503.
        2014-08-26  Evandro Menezes <e.menezes@samsung.com>
 
index 14511e1..4279753 100644 (file)
@@ -1292,7 +1292,12 @@ expand_one_var (tree var, bool toplevel, bool really_expand)
   else if (TREE_CODE (var) == VAR_DECL && DECL_HARD_REGISTER (var))
     {
       if (really_expand)
-        expand_one_hard_reg_var (var);
+       {
+         expand_one_hard_reg_var (var);
+         if (!DECL_HARD_REGISTER (var))
+           /* Invalid register specification.  */
+           expand_one_error_var (var);
+       }
     }
   else if (use_register_for_decl (var))
     {
index a9c53dc..294767d 100644 (file)
@@ -22948,6 +22948,9 @@ arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
            || (TARGET_HARD_FLOAT && TARGET_VFP
                && regno == VFPCC_REGNUM));
 
+  if (regno == CC_REGNUM && GET_MODE_CLASS (mode) != MODE_CC)
+    return false;
+
   if (TARGET_THUMB1)
     /* For the Thumb we only allow values bigger than SImode in
        registers 0 - 6, so that there is always a second low
@@ -23044,6 +23047,9 @@ arm_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
 enum reg_class
 arm_regno_class (int regno)
 {
+  if (regno == PC_REGNUM)
+    return NO_REGS;
+
   if (TARGET_THUMB1)
     {
       if (regno == STACK_POINTER_REGNUM)
index e9f7f7c..eadb377 100644 (file)
@@ -1,5 +1,15 @@
 2014-09-03  Yvan Roux  <yvan.roux@linaro.org>
 
+       Backport from trunk r214526.
+       2014-08-26  Joseph Myers  <joseph@codesourcery.com>
+
+       PR target/60606
+       PR target/61330
+       * gcc.dg/torture/pr60606-1.c, gcc.target/arm/pr60606-2.c,
+       gcc.target/arm/pr60606-3.c, gcc.target/arm/pr60606-4.c: New tests.
+
+2014-09-03  Yvan Roux  <yvan.roux@linaro.org>
+
        Backport from trunk r213659.
        2014-08-06  Alan Lawrence  <alan.lawrence@arm.com>
 
diff --git a/gcc/testsuite/gcc.dg/torture/pr60606-1.c b/gcc/testsuite/gcc.dg/torture/pr60606-1.c
new file mode 100644 (file)
index 0000000..c4afae7
--- /dev/null
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-ffat-lto-objects" } */
+
+int
+f (void)
+{
+  register unsigned int r asm ("no-such-register"); /* { dg-error "invalid register name" } */
+  return r;
+}
diff --git a/gcc/testsuite/gcc.target/arm/pr60606-2.c b/gcc/testsuite/gcc.target/arm/pr60606-2.c
new file mode 100644 (file)
index 0000000..7baf881
--- /dev/null
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+int
+f (void)
+{
+  register unsigned pc asm ("pc"); /* { dg-error "not general enough" } */
+  
+  return pc > 0x12345678;
+}
diff --git a/gcc/testsuite/gcc.target/arm/pr60606-3.c b/gcc/testsuite/gcc.target/arm/pr60606-3.c
new file mode 100644 (file)
index 0000000..60ae27d
--- /dev/null
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+int
+f (void)
+{
+  register unsigned int r asm ("cc"); /* { dg-error "not general enough|suitable for data type" } */
+  return r;
+}
diff --git a/gcc/testsuite/gcc.target/arm/pr60606-4.c b/gcc/testsuite/gcc.target/arm/pr60606-4.c
new file mode 100644 (file)
index 0000000..5288777
--- /dev/null
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+int
+f (void)
+{
+  register unsigned int r[50] asm ("r1"); /* { dg-error "suitable for a register" } */
+  return r[1];
+}
index 8e8c5f6..ad0ca94 100644 (file)
@@ -1340,6 +1340,11 @@ make_decl_rtl (tree decl)
          /* As a register variable, it has no section.  */
          return;
        }
+      /* Avoid internal errors from invalid register
+        specifications.  */
+      SET_DECL_ASSEMBLER_NAME (decl, NULL_TREE);
+      DECL_HARD_REGISTER (decl) = 0;
+      return;
     }
   /* Now handle ordinary static variables and functions (in memory).
      Also handle vars declared register invalidly.  */