drm/amd: cleanup remaining spaces and tabs v2
authorChristian König <christian.koenig@amd.com>
Tue, 3 May 2016 13:54:54 +0000 (15:54 +0200)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 11 May 2016 16:31:20 +0000 (12:31 -0400)
This is the result of running the following commands:
find drivers/gpu/drm/amd/ -name "*.h" -exec sed -i 's/[ \t]\+$//' {} \;
find drivers/gpu/drm/amd/ -name "*.c" -exec sed -i 's/[ \t]\+$//' {} \;
find drivers/gpu/drm/amd/ -name "*.h" -exec sed -i 's/ \+\t/\t/' {} \;
find drivers/gpu/drm/amd/ -name "*.c" -exec sed -i 's/ \+\t/\t/' {} \;

v2: drop changes to DAL and internal headers

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
23 files changed:
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
drivers/gpu/drm/amd/amdgpu/atom.h
drivers/gpu/drm/amd/amdgpu/ci_dpm.c
drivers/gpu/drm/amd/amdgpu/cik_ih.c
drivers/gpu/drm/amd/amdgpu/cikd.h
drivers/gpu/drm/amd/amdgpu/cz_ih.c
drivers/gpu/drm/amd/amdgpu/cz_smumgr.h
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
drivers/gpu/drm/amd/amdgpu/vid.h
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
drivers/gpu/drm/amd/scheduler/gpu_scheduler.h

index 0ab5fcc..abe62ec 100644 (file)
@@ -369,7 +369,7 @@ struct amdgpu_fence_driver {
 
 struct amdgpu_user_fence {
        /* write-back bo */
-       struct amdgpu_bo        *bo;
+       struct amdgpu_bo        *bo;
        /* write-back address offset to bo start */
        uint32_t                offset;
 };
@@ -777,7 +777,7 @@ struct amdgpu_ring {
        struct amdgpu_device            *adev;
        const struct amdgpu_ring_funcs  *funcs;
        struct amdgpu_fence_driver      fence_drv;
-       struct amd_gpu_scheduler        sched;
+       struct amd_gpu_scheduler        sched;
 
        spinlock_t              fence_lock;
        struct amdgpu_bo        *ring_obj;
@@ -1247,7 +1247,7 @@ struct amdgpu_cs_parser {
 struct amdgpu_job {
        struct amd_sched_job    base;
        struct amdgpu_device    *adev;
-       struct amdgpu_vm        *vm;
+       struct amdgpu_vm        *vm;
        struct amdgpu_ring      *ring;
        struct amdgpu_sync      sync;
        struct amdgpu_ib        *ibs;
@@ -1701,7 +1701,7 @@ struct amdgpu_sdma {
        struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
        struct amdgpu_irq_src   trap_irq;
        struct amdgpu_irq_src   illegal_inst_irq;
-       int                     num_instances;
+       int                     num_instances;
 };
 
 /*
@@ -1955,11 +1955,11 @@ struct amdgpu_device {
        bool                            shutdown;
        bool                            need_dma32;
        bool                            accel_working;
-       struct work_struct              reset_work;
+       struct work_struct              reset_work;
        struct notifier_block           acpi_nb;
        struct amdgpu_i2c_chan          *i2c_bus[AMDGPU_MAX_I2C_BUS];
        struct amdgpu_debugfs           debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
-       unsigned                        debugfs_count;
+       unsigned                        debugfs_count;
 #if defined(CONFIG_DEBUG_FS)
        struct dentry                   *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
 #endif
index eacd810..35d0856 100644 (file)
@@ -263,7 +263,7 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
                for (i = 0; i < args->in.bo_number; ++i) {
                        if (copy_from_user(&info[i], uptr, bytes))
                                goto error_free;
-                       
+
                        uptr += args->in.bo_info_size;
                }
        }
@@ -271,7 +271,7 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
        switch (args->in.operation) {
        case AMDGPU_BO_LIST_OP_CREATE:
                r = amdgpu_bo_list_create(fpriv, &list, &handle);
-               if (r) 
+               if (r)
                        goto error_free;
 
                r = amdgpu_bo_list_set(adev, filp, list, info,
@@ -281,7 +281,7 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
                        goto error_free;
 
                break;
-               
+
        case AMDGPU_BO_LIST_OP_DESTROY:
                amdgpu_bo_list_destroy(fpriv, handle);
                handle = 0;
index 7783305..0d44e6a 100644 (file)
@@ -348,7 +348,7 @@ static int amdgpu_doorbell_init(struct amdgpu_device *adev)
        adev->doorbell.base = pci_resource_start(adev->pdev, 2);
        adev->doorbell.size = pci_resource_len(adev->pdev, 2);
 
-       adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), 
+       adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
                                             AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
        if (adev->doorbell.num_doorbells == 0)
                return -EINVAL;
index c3f4e85..503d540 100644 (file)
@@ -43,7 +43,7 @@ struct amdgpu_ring;
 struct amdgpu_bo;
 
 struct amdgpu_gds_asic_info {
-       uint32_t        total_size;
+       uint32_t        total_size;
        uint32_t        gfx_partition_size;
        uint32_t        cs_partition_size;
 };
@@ -52,8 +52,8 @@ struct amdgpu_gds {
        struct amdgpu_gds_asic_info     mem;
        struct amdgpu_gds_asic_info     gws;
        struct amdgpu_gds_asic_info     oa;
-       /* At present, GDS, GWS and OA resources for gfx (graphics) 
-        * is always pre-allocated and available for graphics operation. 
+       /* At present, GDS, GWS and OA resources for gfx (graphics)
+        * is always pre-allocated and available for graphics operation.
         * Such resource is shared between all gfx clients.
         * TODO: move this operation to user space
         * */
index 81bd964..8a253aa 100644 (file)
@@ -530,7 +530,7 @@ struct amdgpu_framebuffer {
                                ((em) == ATOM_ENCODER_MODE_DP_MST))
 
 /* Driver internal use only flags of amdgpu_get_crtc_scanoutpos() */
-#define USE_REAL_VBLANKSTART           (1 << 30)
+#define USE_REAL_VBLANKSTART           (1 << 30)
 #define GET_DISTANCE_TO_VBLANKSTART    (1 << 31)
 
 void amdgpu_link_encoder_connector(struct drm_device *dev);
index 3f95375..0081cf5 100644 (file)
@@ -45,9 +45,9 @@
 /* Firmware Names */
 #ifdef CONFIG_DRM_AMDGPU_CIK
 #define FIRMWARE_BONAIRE       "radeon/bonaire_uvd.bin"
-#define FIRMWARE_KABINI        "radeon/kabini_uvd.bin"
-#define FIRMWARE_KAVERI        "radeon/kaveri_uvd.bin"
-#define FIRMWARE_HAWAII        "radeon/hawaii_uvd.bin"
+#define FIRMWARE_KABINI        "radeon/kabini_uvd.bin"
+#define FIRMWARE_KAVERI        "radeon/kaveri_uvd.bin"
+#define FIRMWARE_HAWAII        "radeon/hawaii_uvd.bin"
 #define FIRMWARE_MULLINS       "radeon/mullins_uvd.bin"
 #endif
 #define FIRMWARE_TONGA         "amdgpu/tonga_uvd.bin"
index 79ba2aa..7b7b0f6 100644 (file)
@@ -41,9 +41,9 @@
 /* Firmware Names */
 #ifdef CONFIG_DRM_AMDGPU_CIK
 #define FIRMWARE_BONAIRE       "radeon/bonaire_vce.bin"
-#define FIRMWARE_KABINI        "radeon/kabini_vce.bin"
-#define FIRMWARE_KAVERI        "radeon/kaveri_vce.bin"
-#define FIRMWARE_HAWAII        "radeon/hawaii_vce.bin"
+#define FIRMWARE_KABINI        "radeon/kabini_vce.bin"
+#define FIRMWARE_KAVERI        "radeon/kaveri_vce.bin"
+#define FIRMWARE_HAWAII        "radeon/hawaii_vce.bin"
 #define FIRMWARE_MULLINS       "radeon/mullins_vce.bin"
 #endif
 #define FIRMWARE_TONGA         "amdgpu/tonga_vce.bin"
index fece8f4..49daf6d 100644 (file)
@@ -92,7 +92,7 @@
 #define ATOM_WS_AND_MASK       0x45
 #define ATOM_WS_FB_WINDOW      0x46
 #define ATOM_WS_ATTRIBUTES     0x47
-#define ATOM_WS_REGPTR         0x48
+#define ATOM_WS_REGPTR         0x48
 
 #define ATOM_IIO_NOP           0
 #define ATOM_IIO_START         1
index 90f83b2..2f24797 100644 (file)
@@ -6363,7 +6363,7 @@ static int ci_dpm_set_interrupt_state(struct amdgpu_device *adev,
 }
 
 static int ci_dpm_process_interrupt(struct amdgpu_device *adev,
-                                   struct amdgpu_irq_src *source, 
+                                   struct amdgpu_irq_src *source,
                                    struct amdgpu_iv_entry *entry)
 {
        bool queue_thermal = false;
index f2f14fe..7e750a4 100644 (file)
@@ -243,7 +243,7 @@ static void cik_ih_decode_iv(struct amdgpu_device *adev,
        /* wptr/rptr are in bytes! */
        u32 ring_index = adev->irq.ih.rptr >> 2;
        uint32_t dw[4];
-       
+
        dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
        dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
        dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
index 60d4493..c4f6f00 100644 (file)
 #       define MACRO_TILE_ASPECT(x)                            ((x) << 4)
 #       define NUM_BANKS(x)                                    ((x) << 6)
 
-#define                MSG_ENTER_RLC_SAFE_MODE                         1
-#define                MSG_EXIT_RLC_SAFE_MODE                          0
+#define                MSG_ENTER_RLC_SAFE_MODE                 1
+#define                MSG_EXIT_RLC_SAFE_MODE                  0
 
 /*
  * PM4
index 23bd912..874b928 100644 (file)
@@ -222,7 +222,7 @@ static void cz_ih_decode_iv(struct amdgpu_device *adev,
        /* wptr/rptr are in bytes! */
        u32 ring_index = adev->irq.ih.rptr >> 2;
        uint32_t dw[4];
-       
+
        dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
        dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
        dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
index 924d355..026342f 100644 (file)
@@ -77,7 +77,7 @@ struct cz_smu_private_data {
        uint8_t         driver_buffer_length;
        uint8_t         scratch_buffer_length;
        uint16_t        toc_entry_used_count;
-       uint16_t        toc_entry_initialize_index;
+       uint16_t        toc_entry_initialize_index;
        uint16_t        toc_entry_power_profiling_index;
        uint16_t        toc_entry_aram;
        uint16_t        toc_entry_ih_register_restore_task_index;
index a82945f..4ea4b4e 100644 (file)
@@ -603,7 +603,7 @@ static const u32 stoney_golden_settings_a11[] =
        mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
        mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
        mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
-       mmTCC_CTRL, 0x00100000, 0xf31fff7f,
+       mmTCC_CTRL, 0x00100000, 0xf31fff7f,
        mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
        mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1,
        mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010,
index e1d6ae7..55b35da 100644 (file)
@@ -40,9 +40,9 @@
 
 #define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT    0x04
 #define GRBM_GFX_INDEX__VCE_INSTANCE_MASK      0x10
-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0        0x8616
-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1        0x8617
-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2        0x8618
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0        0x8616
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1        0x8617
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2        0x8618
 
 #define VCE_V3_0_FW_SIZE       (384 * 1024)
 #define VCE_V3_0_STACK_SIZE    (64 * 1024)
index ace4997..3bf7172 100644 (file)
 #define VCE_CMD_IB             0x00000002
 #define VCE_CMD_FENCE          0x00000003
 #define VCE_CMD_TRAP           0x00000004
-#define VCE_CMD_IB_AUTO        0x00000005
+#define VCE_CMD_IB_AUTO        0x00000005
 #define VCE_CMD_SEMAPHORE      0x00000006
 
 #endif
index 55e877c..d05a5e0 100644 (file)
@@ -465,14 +465,14 @@ static int fiji_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
                        table_info->vdd_dep_on_mclk;
 
        PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
-               "VDD dependency on SCLK table is missing.       \
+               "VDD dependency on SCLK table is missing.       \
                This table is mandatory", return -EINVAL);
        PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
-               "VDD dependency on SCLK table has to have is missing.   \
+               "VDD dependency on SCLK table has to have is missing.   \
                This table is mandatory", return -EINVAL);
 
        PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
-               "VDD dependency on MCLK table is missing.       \
+               "VDD dependency on MCLK table is missing.       \
                This table is mandatory", return -EINVAL);
        PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
                "VDD dependency on MCLK table has to have is missing.    \
index 010199f..dbdcc68 100644 (file)
@@ -2900,14 +2900,14 @@ static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
                                                table_info->vdd_dep_on_mclk;
 
        PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
-               "VDD dependency on SCLK table is missing.       \
+               "VDD dependency on SCLK table is missing.       \
                This table is mandatory", return -EINVAL);
        PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
-               "VDD dependency on SCLK table has to have is missing.   \
+               "VDD dependency on SCLK table has to have is missing.   \
                This table is mandatory", return -EINVAL);
 
        PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
-               "VDD dependency on MCLK table is missing.       \
+               "VDD dependency on MCLK table is missing.       \
                This table is mandatory", return -EINVAL);
        PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
                "VDD dependency on MCLK table has to have is missing.    \
@@ -4628,7 +4628,7 @@ int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr)
        data->need_long_memory_training = true;
 
 /*
- *     PPMCME_FirmwareDescriptorEntry *pfd = NULL;
+ *     PPMCME_FirmwareDescriptorEntry *pfd = NULL;
        pfd = &tonga_mcmeFirmware;
        if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN))
                polaris10_load_mc_microcode(hwmgr, pfd->dpmThreshold,
index 8ba3ad5..da9f5f1 100644 (file)
@@ -1041,10 +1041,10 @@ int atomctrl_calculate_voltage_evv_on_sclk(
 }
 
 /** atomctrl_get_voltage_evv_on_sclk gets voltage via call to ATOM COMMAND table.
- * @param hwmgr                input: pointer to hwManager
+ * @param hwmgr        input: pointer to hwManager
  * @param voltage_type            input: type of EVV voltage VDDC or VDDGFX
  * @param sclk                        input: in 10Khz unit. DPM state SCLK frequency
- *                                             which is define in PPTable SCLK/VDDC dependence
+ *             which is define in PPTable SCLK/VDDC dependence
  *                             table associated with this virtual_voltage_Id
  * @param virtual_voltage_Id      input: voltage id which match per voltage DPM state: 0xff01, 0xff02.. 0xff08
  * @param voltage                     output: real voltage level in unit of mv
index 670b628..d79af48 100644 (file)
@@ -2683,7 +2683,7 @@ static int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
 struct TONGA_DLL_SPEED_SETTING {
        uint16_t            Min;                          /* Minimum Data Rate*/
        uint16_t            Max;                          /* Maximum Data Rate*/
-       uint32_t                        dll_speed;                     /* The desired DLL_SPEED setting*/
+       uint32_t                        dll_speed;                     /* The desired DLL_SPEED setting*/
 };
 
 static int tonga_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
@@ -3316,14 +3316,14 @@ static int tonga_set_private_var_based_on_pptale(struct pp_hwmgr *hwmgr)
                pptable_info->vdd_dep_on_mclk;
 
        PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
-               "VDD dependency on SCLK table is missing.       \
+               "VDD dependency on SCLK table is missing.       \
                This table is mandatory", return -1);
        PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
-               "VDD dependency on SCLK table has to have is missing.   \
+               "VDD dependency on SCLK table has to have is missing.   \
                This table is mandatory", return -1);
 
        PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
-               "VDD dependency on MCLK table is missing.       \
+               "VDD dependency on MCLK table is missing.       \
                This table is mandatory", return -1);
        PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
                "VDD dependency on MCLK table has to have is missing.    \
index c6a6b40..573cd39 100644 (file)
@@ -74,7 +74,7 @@ struct tonga_power_state {
 };
 
 struct _phw_tonga_dpm_level {
-       bool            enabled;
+       bool            enabled;
        uint32_t    value;
        uint32_t    param1;
 };
@@ -237,20 +237,20 @@ struct tonga_hwmgr {
        irq_handler_func_t             ctf_callback;
        void                             *ctf_context;
 
-       phw_tonga_clock_registers         clock_registers;
+       phw_tonga_clock_registers         clock_registers;
        phw_tonga_voltage_smio_registers  voltage_smio_registers;
 
-       bool                            is_memory_GDDR5;
+       bool    is_memory_GDDR5;
        uint16_t                          acpi_vddc;
-       bool                            pspp_notify_required;        /* Flag to indicate if PSPP notification to SBIOS is required */
+       bool    pspp_notify_required;        /* Flag to indicate if PSPP notification to SBIOS is required */
        uint16_t                          force_pcie_gen;            /* The forced PCI-E speed if not 0xffff */
        uint16_t                          acpi_pcie_gen;             /* The PCI-E speed at ACPI time */
        uint32_t                           pcie_gen_cap;             /* The PCI-E speed capabilities bitmap from CAIL */
        uint32_t                           pcie_lane_cap;            /* The PCI-E lane capabilities bitmap from CAIL */
        uint32_t                           pcie_spc_cap;             /* Symbol Per Clock Capabilities from registry */
-       phw_tonga_leakage_voltage               vddc_leakage;            /* The Leakage VDDC supported (based on leakage ID).*/
-       phw_tonga_leakage_voltage               vddcgfx_leakage;         /* The Leakage VDDC supported (based on leakage ID). */
-       phw_tonga_leakage_voltage               vddci_leakage;           /* The Leakage VDDCI supported (based on leakage ID). */
+       phw_tonga_leakage_voltage       vddc_leakage;            /* The Leakage VDDC supported (based on leakage ID).*/
+       phw_tonga_leakage_voltage       vddcgfx_leakage;         /* The Leakage VDDC supported (based on leakage ID). */
+       phw_tonga_leakage_voltage       vddci_leakage;           /* The Leakage VDDCI supported (based on leakage ID). */
 
        uint32_t                           mvdd_control;
        uint32_t                           vddc_mask_low;
@@ -263,8 +263,8 @@ struct tonga_hwmgr {
        uint32_t                           mclk_stutter_mode_threshold;
        uint32_t                           mclk_edc_enable_threshold;
        uint32_t                           mclk_edc_wr_enable_threshold;
-       bool                            is_uvd_enabled;
-       bool                            is_xdma_enabled;
+       bool    is_uvd_enabled;
+       bool    is_xdma_enabled;
        phw_tonga_vbios_boot_state      vbios_boot_state;
 
        bool                         battery_state;
index c96e5b1..fd4ce7a 100644 (file)
@@ -500,7 +500,7 @@ struct phm_dynamic_state_info {
        struct phm_ppm_table                          *ppm_parameter_table;
        struct phm_cac_tdp_table                      *cac_dtp_table;
        struct phm_clock_voltage_dependency_table         *vdd_gfx_dependency_on_sclk;
-       struct phm_vq_budgeting_table                             *vq_budgeting_table;
+       struct phm_vq_budgeting_table                             *vq_budgeting_table;
 };
 
 struct pp_fan_info {
index 169f70f..070095a 100644 (file)
@@ -74,7 +74,7 @@ struct amd_sched_fence {
        struct amd_gpu_scheduler        *sched;
        spinlock_t                      lock;
        void                            *owner;
-       struct amd_sched_job    *s_job;
+       struct amd_sched_job    *s_job;
 };
 
 struct amd_sched_job {