arm64: dts: qcom: align SDHCI reg-names with DT schema

DT schema requires SDHCI reg names to be hc/core without "_mem" suffix,
just like TXT bindings were expecting before the conversion.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220712144245.17417-4-krzysztof.kozlowski@linaro.org

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index d53675f..251bc76 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -383,7 +383,7 @@
                sdhc_1: mmc@7824900 {
                        compatible = "qcom,sdhci-msm-v4";
                        reg = <0x7824900 0x500>, <0x7824000 0x800>;
-                       reg-names = "hc_mem", "core_mem";
+                       reg-names = "hc", "core";
 
                        interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index de741f2..a831064 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -1483,7 +1483,7 @@
                sdhc_1: mmc@7824000 {
                        compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
                        reg = <0x07824900 0x11c>, <0x07824000 0x800>;
-                       reg-names = "hc_mem", "core_mem";
+                       reg-names = "hc", "core";
 
                        interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
@@ -1501,7 +1501,7 @@
                sdhc_2: mmc@7864000 {
                        compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
                        reg = <0x07864900 0x11c>, <0x07864000 0x800>;
-                       reg-names = "hc_mem", "core_mem";
+                       reg-names = "hc", "core";
 
                        interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;

diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi
index ed05897..6b992a6 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8953.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi
@@ -799,7 +799,7 @@
                        compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
 
                        reg = <0x7824900 0x500>, <0x7824000 0x800>;
-                       reg-names = "hc_mem", "core_mem";
+                       reg-names = "hc", "core";
 
                        interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
@@ -859,7 +859,7 @@
                        compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
 
                        reg = <0x7864900 0x500>, <0x7864000 0x800>;
-                       reg-names = "hc_mem", "core_mem";
+                       reg-names = "hc", "core";
 
                        interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;

diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi
index e1fc4b3..ded5b7c 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8994.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi
@@ -459,7 +459,7 @@
                sdhc1: mmc@f9824900 {
                        compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
                        reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
-                       reg-names = "hc_mem", "core_mem";
+                       reg-names = "hc", "core";
 
                        interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
@@ -482,7 +482,7 @@
                sdhc2: mmc@f98a4900 {
                        compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
                        reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
-                       reg-names = "hc_mem", "core_mem";
+                       reg-names = "hc", "core";
 
                        interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index f3f4c32..c0a2baf 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -3023,7 +3023,7 @@
                sdhc1: mmc@7464900 {
                        compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
                        reg = <0x07464900 0x11c>, <0x07464000 0x800>;
-                       reg-names = "hc_mem", "core_mem";
+                       reg-names = "hc", "core";
 
                        interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
                                        <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
@@ -3047,7 +3047,7 @@
                sdhc2: mmc@74a4900 {
                        compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
                        reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
-                       reg-names = "hc_mem", "core_mem";
+                       reg-names = "hc", "core";
 
                        interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;

diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index 1118134..f05f16a 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -2078,7 +2078,7 @@
                sdhc2: mmc@c0a4900 {
                        compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4";
                        reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
-                       reg-names = "hc_mem", "core_mem";
+                       reg-names = "hc", "core";
 
                        interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;