bool validateIntClampSupported(const MCInst &Inst);
bool validateMIMGAtomicDMask(const MCInst &Inst);
bool validateMIMGGatherDMask(const MCInst &Inst);
+ bool validateMovrels(const MCInst &Inst);
bool validateMIMGDataSize(const MCInst &Inst);
bool validateMIMGAddrSize(const MCInst &Inst);
bool validateMIMGD16(const MCInst &Inst);
return DMask == 0x1 || DMask == 0x2 || DMask == 0x4 || DMask == 0x8;
}
+static bool IsMovrelsSDWAOpcode(const unsigned Opcode)
+{
+ switch (Opcode) {
+ case AMDGPU::V_MOVRELS_B32_sdwa_gfx10:
+ case AMDGPU::V_MOVRELSD_B32_sdwa_gfx10:
+ case AMDGPU::V_MOVRELSD_2_B32_sdwa_gfx10:
+ return true;
+ default:
+ return false;
+ }
+}
+
+// movrels* opcodes should only allow VGPRS as src0.
+// This is specified in .td description for vop1/vop3,
+// but sdwa is handled differently. See isSDWAOperand.
+bool AMDGPUAsmParser::validateMovrels(const MCInst &Inst) {
+
+ const unsigned Opc = Inst.getOpcode();
+ const MCInstrDesc &Desc = MII.get(Opc);
+
+ if ((Desc.TSFlags & SIInstrFlags::SDWA) == 0 || !IsMovrelsSDWAOpcode(Opc))
+ return true;
+
+ const int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
+ assert(Src0Idx != -1);
+
+ const MCOperand &Src0 = Inst.getOperand(Src0Idx);
+ if (!Src0.isReg())
+ return false;
+
+ auto Reg = Src0.getReg();
+ const MCRegisterInfo *TRI = getContext().getRegisterInfo();
+ return !isSGPR(mc2PseudoReg(Reg), TRI);
+}
+
bool AMDGPUAsmParser::validateMIMGD16(const MCInst &Inst) {
const unsigned Opc = Inst.getOpcode();
"invalid image_gather dmask: only one bit must be set");
return false;
}
+ if (!validateMovrels(Inst)) {
+ Error(IDLoc, "source operand must be a VGPR");
+ return false;
+ }
if (!validateFlatOffset(Inst, Operands)) {
return false;
}
}
// Restrict src0 to be VGPR
-def VOP_I32_VI32_NO_EXT : VOPProfile<[i32, i32, untyped, untyped]> {
+def VOP_MOVRELS : VOPProfile<[i32, i32, untyped, untyped]> {
let Src0RC32 = VRegSrc_32;
let Src0RC64 = VRegSrc_32;
-
- let HasExt = 0;
- let HasExtDPP = 0;
- let HasExtSDWA = 0;
- let HasExtSDWA9 = 0;
}
// Special case because there are no true output operands. Hack vdst
let Outs = (outs);
let Ins32 = (ins Src0RC32:$vdst, Src1RC:$src0);
let Ins64 = (ins Src0RC64:$vdst, Src1RC:$src0);
- let InsDPP = (ins DstRC:$vdst, DstRC:$old, Src0RC32:$src0,
- dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
- bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
- let InsDPP16 = !con(InsDPP, (ins FI:$fi));
+ let Asm32 = getAsm32<1, 1>.ret;
+ let Asm64 = getAsm64<1, 1, 0, 0, 1>.ret;
- let InsSDWA = (ins Src0RC32:$vdst, Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
- clampmod:$clamp, omod:$omod, dst_sel:$dst_sel, dst_unused:$dst_unused,
+ let OutsSDWA = (outs Src0RC32:$vdst);
+ let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
+ clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused,
src0_sel:$src0_sel);
+ let AsmSDWA9 = getAsmSDWA9<1, 0, 1>.ret;
- let Asm32 = getAsm32<1, 1>.ret;
- let Asm64 = getAsm64<1, 1, 0, 0, 1>.ret;
- let AsmDPP = getAsmDPP<1, 1, 0>.ret;
+ let OutsDPP = (outs Src0RC32:$vdst);
+ let InsDPP16 = (ins Src0RC32:$old, Src0RC32:$src0,
+ dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
+ bank_mask:$bank_mask, bound_ctrl:$bound_ctrl, FI:$fi);
let AsmDPP16 = getAsmDPP16<1, 1, 0>.ret;
- let AsmSDWA = getAsmSDWA<1, 1>.ret;
- let AsmSDWA9 = getAsmSDWA9<1, 0, 1>.ret;
- let HasExt = 0;
- let HasExtDPP = 0;
- let HasExtSDWA = 0;
- let HasExtSDWA9 = 0;
+ let OutsDPP8 = (outs Src0RC32:$vdst);
+ let InsDPP8 = (ins Src0RC32:$old, Src0RC32:$src0, dpp8:$dpp8, FI:$fi);
+ let AsmDPP8 = getAsmDPP8<1, 1, 0>.ret;
let HasDst = 0;
let EmitDst = 1; // force vdst emission
def VOP_MOVRELSD : VOP_MOVREL<VRegSrc_32>;
let SubtargetPredicate = HasMovrel, Uses = [M0, EXEC] in {
-// v_movreld_b32 is a special case because the destination output
+ // v_movreld_b32 is a special case because the destination output
// register is really a source. It isn't actually read (but may be
// written), and is only to provide the base register to start
// indexing from. Tablegen seems to not let you define an implicit
// virtual register output for the super register being written into,
// so this must have an implicit def of the register added to it.
defm V_MOVRELD_B32 : VOP1Inst <"v_movreld_b32", VOP_MOVRELD>;
-defm V_MOVRELS_B32 : VOP1Inst <"v_movrels_b32", VOP_I32_VI32_NO_EXT>;
+defm V_MOVRELS_B32 : VOP1Inst <"v_movrels_b32", VOP_MOVRELS>;
defm V_MOVRELSD_B32 : VOP1Inst <"v_movrelsd_b32", VOP_MOVRELSD>;
} // End Uses = [M0, EXEC]
}
} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
-multiclass VOP1_Real_gfx10_no_dpp<bits<9> op> :
- VOP1_Real_e32_gfx10<op>, VOP1_Real_e64_gfx10<op>,
- VOP1_Real_sdwa_gfx10<op>;
-
-multiclass VOP1_Real_gfx10_no_dpp8<bits<9> op> :
- VOP1_Real_e32_gfx10<op>, VOP1_Real_e64_gfx10<op>,
- VOP1_Real_sdwa_gfx10<op>, VOP1_Real_dpp_gfx10<op>;
-
multiclass VOP1_Real_gfx10<bits<9> op> :
- VOP1_Real_gfx10_no_dpp8<op>, VOP1_Real_dpp8_gfx10<op>;
+ VOP1_Real_e32_gfx10<op>, VOP1_Real_e64_gfx10<op>,
+ VOP1_Real_sdwa_gfx10<op>, VOP1_Real_dpp_gfx10<op>,
+ VOP1_Real_dpp8_gfx10<op>;
defm V_PIPEFLUSH : VOP1_Real_gfx10<0x01b>;
defm V_MOVRELSD_2_B32 : VOP1_Real_gfx10<0x048>;
multiclass VOP1_Real_gfx6_gfx7_gfx10<bits<9> op> :
VOP1_Real_gfx6_gfx7<op>, VOP1_Real_gfx10<op>;
-multiclass VOP1_Real_gfx6_gfx7_gfx10_no_dpp8<bits<9> op> :
- VOP1_Real_gfx6_gfx7<op>, VOP1_Real_gfx10_no_dpp8<op>;
-
-multiclass VOP1_Real_gfx6_gfx7_gfx10_no_dpp<bits<9> op> :
- VOP1_Real_gfx6_gfx7<op>, VOP1_Real_gfx10_no_dpp<op>;
-
defm V_LOG_CLAMP_F32 : VOP1_Real_gfx6_gfx7<0x026>;
defm V_RCP_CLAMP_F32 : VOP1_Real_gfx6_gfx7<0x028>;
defm V_RCP_LEGACY_F32 : VOP1_Real_gfx6_gfx7<0x029>;
defm V_FREXP_EXP_I32_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x03f>;
defm V_FREXP_MANT_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x040>;
defm V_CLREXCP : VOP1_Real_gfx6_gfx7_gfx10<0x041>;
-defm V_MOVRELD_B32 : VOP1_Real_gfx6_gfx7_gfx10_no_dpp<0x042>;
-defm V_MOVRELS_B32 : VOP1_Real_gfx6_gfx7_gfx10_no_dpp8<0x043>;
-defm V_MOVRELSD_B32 : VOP1_Real_gfx6_gfx7_gfx10_no_dpp8<0x044>;
+defm V_MOVRELD_B32 : VOP1_Real_gfx6_gfx7_gfx10<0x042>;
+defm V_MOVRELS_B32 : VOP1_Real_gfx6_gfx7_gfx10<0x043>;
+defm V_MOVRELSD_B32 : VOP1_Real_gfx6_gfx7_gfx10<0x044>;
//===----------------------------------------------------------------------===//
// GFX8, GFX9 (VI).
v_movreld_b32_e64 v5, -4.0
// GFX10: encoding: [0x05,0x00,0xc2,0xd5,0xf7,0x00,0x00,0x00]
+v_movreld_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x84,0x00,0x7e,0x02,0x06,0x06,0x00]
+
+v_movreld_b32_sdwa v0, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x84,0x00,0x7e,0x02,0x06,0x86,0x00]
+
+v_movreld_b32_sdwa v0, 64 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x84,0x00,0x7e,0xc0,0x06,0x86,0x00]
+
+v_movreld_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x84,0x00,0x7e,0x00,0x06,0x0e,0x00]
+
v_movrels_b32 v5, v1
// GFX10: encoding: [0x01,0x87,0x0a,0x7e]
v_movrels_b32_e64 v5, v255
// GFX10: encoding: [0x05,0x00,0xc3,0xd5,0xff,0x01,0x00,0x00]
+v_movrels_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x86,0x00,0x7e,0x02,0x06,0x06,0x00]
+
+v_movrels_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x86,0x00,0x7e,0x00,0x06,0x0e,0x00]
+
+v_movrels_b32_e32 v5, s1
+// GFX10-ERR: error: invalid operand for instruction
+
+v_movrels_b32_e32 v5, 1
+// GFX10-ERR: error: invalid operand for instruction
+
+v_movrels_b32_e64 v5, s1
+// GFX10-ERR: error: invalid operand for instruction
+
+v_movrels_b32_e64 v5, 1
+// GFX10-ERR: error: invalid operand for instruction
+
+v_movrels_b32_sdwa v0, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10-ERR: error: source operand must be a VGPR
+
+v_movrels_b32_sdwa v0, 1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10-ERR: error: source operand must be a VGPR
+
v_movrelsd_b32 v5, v1
// GFX10: encoding: [0x01,0x89,0x0a,0x7e]
v_movrelsd_b32_e64 v5, v255
// GFX10: encoding: [0x05,0x00,0xc4,0xd5,0xff,0x01,0x00,0x00]
-v_movrelsd_b32 v5, s1
+v_movrelsd_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x88,0x00,0x7e,0x02,0x06,0x06,0x00]
+
+v_movrelsd_b32_sdwa v0, v0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x88,0x00,0x7e,0x00,0x06,0x06,0x00]
+
+v_movrelsd_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x88,0x00,0x7e,0x00,0x06,0x0e,0x00]
+
+v_movrelsd_b32_e32 v5, s1
// GFX10-ERR: error: invalid operand for instruction
+v_movrelsd_b32_e32 v5, 1
+// GFX10-ERR: error: invalid operand for instruction
+
+v_movrelsd_b32_e64 v5, s1
+// GFX10-ERR: error: invalid operand for instruction
+
+v_movrelsd_b32_e64 v5, 1
+// GFX10-ERR: error: invalid operand for instruction
+
+v_movrelsd_b32_sdwa v0, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10-ERR: error: source operand must be a VGPR
+
+v_movrelsd_b32_sdwa v0, 1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10-ERR: error: source operand must be a VGPR
+
v_movrelsd_2_b32 v5, v1
// GFX10: encoding: [0x01,0x91,0x0a,0x7e]
v_movrelsd_2_b32_e64 v5, v255
// GFX10: encoding: [0x05,0x00,0xc8,0xd5,0xff,0x01,0x00,0x00]
-v_movrelsd_2_b32 v5, s1
+v_movrelsd_2_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x90,0x00,0x7e,0x02,0x06,0x06,0x00]
+
+v_movrelsd_2_b32_sdwa v0, v0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x90,0x00,0x7e,0x00,0x06,0x06,0x00]
+
+v_movrelsd_2_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x90,0x00,0x7e,0x00,0x06,0x0e,0x00]
+
+v_movrelsd_2_b32_e32 v5, s1
// GFX10-ERR: error: invalid operand for instruction
+v_movrelsd_2_b32_e32 v5, 1
+// GFX10-ERR: error: invalid operand for instruction
+
+v_movrelsd_2_b32_e64 v5, s1
+// GFX10-ERR: error: invalid operand for instruction
+
+v_movrelsd_2_b32_e64 v5, 1
+// GFX10-ERR: error: invalid operand for instruction
+
+v_movrelsd_2_b32_sdwa v0, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10-ERR: error: source operand must be a VGPR
+
+v_movrelsd_2_b32_sdwa v0, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10-ERR: error: source operand must be a VGPR
+
+v_movrelsd_2_b32_sdwa v0, null dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10-ERR: error: source operand must be a VGPR
+
v_cvt_f16_u16_e32 v5, v1
// GFX10: encoding: [0x01,0xa1,0x0a,0x7e]
v_subrev_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
// GFX10: [0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x04,0x00]
+
+v_movreld_b32_dpp v1, v0 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: [0xfa,0x84,0x02,0x7e,0x00,0x1b,0x00,0x00]
+
+v_movrels_b32_dpp v1, v0 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
+// GFX10: [0xfa,0x86,0x02,0x7e,0x00,0x1b,0x04,0x00]
+
+v_movrelsd_2_b32_dpp v0, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: [0xfa,0x90,0x00,0x7e,0x02,0x1b,0x00,0x00]
+
+v_movrelsd_b32_dpp v0, v255 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: [0xfa,0x88,0x00,0x7e,0xff,0x1b,0x00,0x00]
v_mac_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
// GFX10: v_mac_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x3e,0x01,0x77,0x39,0x05]
+
+v_movreld_b32 v0, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX10: [0xea,0x84,0x00,0x7e,0x01,0x77,0x39,0x05]
+
+v_movrels_b32 v0, v2 dpp8:[0,0,0,0,0,0,0,0]
+// GFX10: [0xe9,0x86,0x00,0x7e,0x02,0x00,0x00,0x00]
+
+v_movrelsd_2_b32 v0, v255 dpp8:[7,6,5,4,3,2,1,0]
+// GFX10: [0xe9,0x90,0x00,0x7e,0xff,0x77,0x39,0x05]
+
+v_movrelsd_b32 v0, v2 dpp8:[7,6,5,4,3,2,1,0]
+// GFX10: [0xe9,0x88,0x00,0x7e,0x02,0x77,0x39,0x05]
# GFX10: v_movreld_b32_e64 v5, v255 ; encoding: [0x05,0x00,0xc2,0xd5,0xff,0x01,0x00,0x00]
0x05,0x00,0xc2,0xd5,0xff,0x01,0x00,0x00
+# GFX10: v_movreld_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x84,0x00,0x7e,0x02,0x06,0x06,0x00]
+0xf9,0x84,0x00,0x7e,0x02,0x06,0x06,0x00
+
+# GFX10: v_movreld_b32_sdwa v0, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x84,0x00,0x7e,0x02,0x06,0x86,0x00]
+0xf9,0x84,0x00,0x7e,0x02,0x06,0x86,0x00
+
+# GFX10: v_movreld_b32_sdwa v0, 64 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x84,0x00,0x7e,0xc0,0x06,0x86,0x00]
+0xf9,0x84,0x00,0x7e,0xc0,0x06,0x86,0x00
+
+# GFX10: v_movreld_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x84,0x00,0x7e,0x00,0x06,0x0e,0x00]
+0xf9,0x84,0x00,0x7e,0x00,0x06,0x0e,0x00
+
# GFX10: v_movrels_b32_e32 v255, v1 ; encoding: [0x01,0x87,0xfe,0x7f]
0x01,0x87,0xfe,0x7f
# GFX10: v_movrels_b32_e64 v5, v255 ; encoding: [0x05,0x00,0xc3,0xd5,0xff,0x01,0x00,0x00]
0x05,0x00,0xc3,0xd5,0xff,0x01,0x00,0x00
+# GFX10: v_movrels_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x86,0x00,0x7e,0x02,0x06,0x06,0x00]
+0xf9,0x86,0x00,0x7e,0x02,0x06,0x06,0x00
+
+# GFX10: v_movrels_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x86,0x00,0x7e,0x00,0x06,0x0e,0x00]
+0xf9,0x86,0x00,0x7e,0x00,0x06,0x0e,0x00
+
# GFX10: v_movrelsd_2_b32_e32 v255, v1 ; encoding: [0x01,0x91,0xfe,0x7f]
0x01,0x91,0xfe,0x7f
# GFX10: v_movrelsd_2_b32_e64 v5, v255 ; encoding: [0x05,0x00,0xc8,0xd5,0xff,0x01,0x00,0x00]
0x05,0x00,0xc8,0xd5,0xff,0x01,0x00,0x00
+# GFX10: v_movrelsd_2_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x90,0x00,0x7e,0x02,0x06,0x06,0x00]
+0xf9,0x90,0x00,0x7e,0x02,0x06,0x06,0x00
+
+# GFX10: v_movrelsd_2_b32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x90,0x00,0x7e,0x00,0x06,0x06,0x00]
+0xf9,0x90,0x00,0x7e,0x00,0x06,0x06,0x00
+
+# GFX10: v_movrelsd_2_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x90,0x00,0x7e,0x00,0x06,0x0e,0x00]
+0xf9,0x90,0x00,0x7e,0x00,0x06,0x0e,0x00
+
# GFX10: v_movrelsd_b32_e32 v255, v1 ; encoding: [0x01,0x89,0xfe,0x7f]
0x01,0x89,0xfe,0x7f
# GFX10: v_movrelsd_b32_e64 v5, v255 ; encoding: [0x05,0x00,0xc4,0xd5,0xff,0x01,0x00,0x00]
0x05,0x00,0xc4,0xd5,0xff,0x01,0x00,0x00
+# GFX10: v_movrelsd_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x88,0x00,0x7e,0x02,0x06,0x06,0x00]
+0xf9,0x88,0x00,0x7e,0x02,0x06,0x06,0x00
+
+# GFX10: v_movrelsd_b32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x88,0x00,0x7e,0x00,0x06,0x06,0x00]
+0xf9,0x88,0x00,0x7e,0x00,0x06,0x06,0x00
+
+# GFX10: v_movrelsd_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x88,0x00,0x7e,0x00,0x06,0x0e,0x00]
+0xf9,0x88,0x00,0x7e,0x00,0x06,0x0e,0x00
+
# GFX10: v_mqsad_pk_u16_u8 v[254:255], v[1:2], v2, v[3:4] ; encoding: [0xfe,0x00,0x73,0xd5,0x01,0x05,0x0e,0x04]
0xfe,0x00,0x73,0xd5,0x01,0x05,0x0e,0x04
# GFX10: v_subrev_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x04,0x00]
0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x04,0x00
+
+# GFX10: v_movreld_b32_dpp v1, v0 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x84,0x02,0x7e,0x00,0x1b,0x00,0x00]
+0xfa,0x84,0x02,0x7e,0x00,0x1b,0x00,0x00
+
+# GFX10: v_movrels_b32_dpp v1, v0 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0xfa,0x86,0x02,0x7e,0x00,0x1b,0x04,0x00]
+0xfa,0x86,0x02,0x7e,0x00,0x1b,0x04,0x00
+
+# GFX10: v_movrelsd_2_b32_dpp v0, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x90,0x00,0x7e,0x02,0x1b,0x00,0x00]
+0xfa,0x90,0x00,0x7e,0x02,0x1b,0x00,0x00
+
+# GFX10: v_movrelsd_b32_dpp v0, v255 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x88,0x00,0x7e,0xff,0x1b,0x00,0x00]
+0xfa,0x88,0x00,0x7e,0xff,0x1b,0x00,0x00
# GFX10: v_mac_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x3e,0x01,0x77,0x39,0x05]
0xea,0x04,0x0a,0x3e,0x01,0x77,0x39,0x05
+
+# GFX10: v_movreld_b32_dpp v0, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x84,0x00,0x7e,0x01,0x77,0x39,0x05]
+0xea,0x84,0x00,0x7e,0x01,0x77,0x39,0x05
+
+# GFX10: v_movrels_b32_dpp v0, v2 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0x86,0x00,0x7e,0x02,0x00,0x00,0x00]
+0xe9,0x86,0x00,0x7e,0x02,0x00,0x00,0x00
+
+# GFX10: v_movrelsd_2_b32_dpp v0, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x90,0x00,0x7e,0xff,0x77,0x39,0x05]
+0xe9,0x90,0x00,0x7e,0xff,0x77,0x39,0x05
+
+# GFX10: v_movrelsd_b32_dpp v0, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x88,0x00,0x7e,0x02,0x77,0x39,0x05]
+0xe9,0x88,0x00,0x7e,0x02,0x77,0x39,0x05