;
binaryop: MUL | MAC | MACH | LINE | SAD2 | SADA2 | DP4 | DPH | DP3 | DP2
+;
binaryaccinstruction:
predicate binaryaccop conditionalmodifier saturate execsize
;
triinstruction: sendinstruction
+;
sendinstruction: predicate SEND execsize INTEGER post_dst payload msgtarget
MSGLEN INTEGER RETURNLEN INTEGER instoptions
$$.bits3.generic.end_of_thread =
$12.bits3.generic.end_of_thread;
}
+;
branchloopop: IF | IFF | WHILE
;
breakop: BREAK | CONT | WAIT
+;
maskpushop: MSAVE | PUSH
;
bzero(&$$, sizeof($$));
$$.header.opcode = $1;
}
+;
/* XXX! */
payload: directsrcoperand
math_signed: /* empty */ { $$ = 0; }
| SIGNED { $$ = 1; }
+;
math_scalar: /* empty */ { $$ = 0; }
| SCALAR { $$ = 1; }
+;
/* 1.4.2: Destination register */
dst: dstoperand | dstoperandex
;
-/* XXX: dstregion writemask */
+/* XXX: writemask */
dstoperand: dstreg dstregion regtype
{
/* Returns an instruction with just the destination register
dstoperandex_typed: accreg | flagreg | addrreg | maskreg
;
-/* XXX: indirectgenreg, directmsgreg, indirectmsgreg */
+/* XXX: indirectgenreg, indirectmsgreg */
dstreg: directgenreg
{
$$.bits1.da1.dest_reg_file = $1.reg_file;
;
srcimm: directsrcoperand | imm32reg
+;
imm32reg: imm32 srcimmtype
{
| srcarchoperandex
;
+/* 1.4.5: Register files and register numbers */
subregnum: DOT INTEGER
{
$$ = $2;
}
;
-/* 1.4.5: Register files and register numbers */
directgenreg: GENREG subregnum
{
$$.reg_file = BRW_GENERAL_REGISTER_FILE;
$$.reg_nr = $1;
$$.subreg_nr = $2;
}
+;
directmsgreg: MSGREG subregnum
{
| TYPE_W { $$ = BRW_REGISTER_TYPE_W; }
| TYPE_UB { $$ = BRW_REGISTER_TYPE_UB; }
| TYPE_B { $$ = BRW_REGISTER_TYPE_B; }
+;
+
/* XXX: Add TYPE_VF and TYPE_HF */
srcimmtype: regtype
;
-/* 1.4.11: */
+/* 1.4.11: Immediate values */
imm32: INTEGER { $$ = $1; }
| NUMBER { $$ = $1; }
+;
/* 1.4.12: Predication and modifiers */
/* XXX: do the predicate */
negate: /* empty */ { $$ = 0; }
| MINUS { $$ = 1; }
+;
abs: /* empty */ { $$ = 0; }
| ABS { $$ = 1; }
+;
execsize: LPAREN INTEGER RPAREN
{