drm/amdgpu/gfx10: drop old bring up code

No longer used.  Remove it.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 8bd07ff..25be448 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -6423,55 +6423,6 @@ static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
        return 0;
 }
 
-#ifdef BRING_UP_DEBUG
-static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
-{
-       struct amdgpu_device *adev = ring->adev;
-       struct v10_gfx_mqd *mqd = ring->mqd_ptr;
-
-       /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
-       WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
-       WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
-
-       /* set GFX_MQD_BASE */
-       WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
-       WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
-
-       /* set GFX_MQD_CONTROL */
-       WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
-
-       /* set GFX_HQD_VMID to 0 */
-       WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
-
-       WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
-                       mqd->cp_gfx_hqd_queue_priority);
-       WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
-
-       /* set GFX_HQD_BASE, similar as CP_RB_BASE */
-       WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
-       WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
-
-       /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
-       WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
-       WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
-
-       /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
-       WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
-
-       /* set RB_WPTR_POLL_ADDR */
-       WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
-       WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
-
-       /* set RB_DOORBELL_CONTROL */
-       WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
-
-       /* active the queue */
-       WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
-
-       return 0;
-}
-#endif
-
 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
 {
        struct amdgpu_device *adev = ring->adev;
@@ -6492,9 +6443,6 @@ static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
                if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
                        gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
 
-#ifdef BRING_UP_DEBUG
-               gfx_v10_0_gfx_queue_init_register(ring);
-#endif
                nv_grbm_select(adev, 0, 0, 0, 0);
                mutex_unlock(&adev->srbm_mutex);
                if (adev->gfx.me.mqd_backup[mqd_idx])
@@ -6507,13 +6455,6 @@ static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
                ring->wptr = 0;
                *ring->wptr_cpu_addr = 0;
                amdgpu_ring_clear_ring(ring);
-#ifdef BRING_UP_DEBUG
-               mutex_lock(&adev->srbm_mutex);
-               nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
-               gfx_v10_0_gfx_queue_init_register(ring);
-               nv_grbm_select(adev, 0, 0, 0, 0);
-               mutex_unlock(&adev->srbm_mutex);
-#endif
        } else {
                amdgpu_ring_clear_ring(ring);
        }
@@ -6521,7 +6462,6 @@ static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
        return 0;
 }
 
-#ifndef BRING_UP_DEBUG
 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
 {
        struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
@@ -6543,7 +6483,6 @@ static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
 
        return amdgpu_ring_test_helper(kiq_ring);
 }
-#endif
 
 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
 {
@@ -6567,11 +6506,11 @@ static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
                if (r)
                        goto done;
        }
-#ifndef BRING_UP_DEBUG
+
        r = gfx_v10_0_kiq_enable_kgq(adev);
        if (r)
                goto done;
-#endif
+
        r = gfx_v10_0_cp_gfx_start(adev);
        if (r)
                goto done;
@@ -7239,7 +7178,6 @@ static int gfx_v10_0_hw_init(void *handle)
        return r;
 }
 
-#ifndef BRING_UP_DEBUG
 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
 {
        struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
@@ -7261,7 +7199,6 @@ static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
        else
                return 0;
 }
-#endif
 
 static int gfx_v10_0_hw_fini(void *handle)
 {
@@ -7272,13 +7209,12 @@ static int gfx_v10_0_hw_fini(void *handle)
        amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
 
        if (!adev->no_hw_access) {
-#ifndef BRING_UP_DEBUG
                if (amdgpu_async_gfx_ring) {
                        r = gfx_v10_0_kiq_disable_kgq(adev);
                        if (r)
                                DRM_ERROR("KGQ disable failed\n");
                }
-#endif
+
                if (amdgpu_gfx_disable_kcq(adev, 0))
                        DRM_ERROR("KCQ disable failed\n");
        }