2000-03-17 Michael Hayes <m.hayes@elec.canterbury.ac.nz>
+ * config/c4x/c4x.h (ASM_SPEC, CPP_SPEC, LINK_SPEC): Support C33.
+ (C33_FLAG, TARGET_C3X): Add macros.
+ (TARGET_SWITCHES): Add -m33 option.
+ * config/c4x/c4x.c (c4x_override_options): Test for TARGET_C33.
+
+2000-03-17 Michael Hayes <m.hayes@elec.canterbury.ac.nz>
+
* config/c4x/c4x.h (PARALLEL_INSN_FLAG): Add.
(PARALLEL_PACK_FLAG): Delete.
(TARGET_SWITCHES): Update.
const char *c4x_rpts_cycles_string;
int c4x_rpts_cycles = 0; /* Max. cycles for RPTS. */
const char *c4x_cpu_version_string;
-int c4x_cpu_version = 40; /* CPU version C30/31/32/40/44. */
+int c4x_cpu_version = 40; /* CPU version C30/31/32/33/40/44. */
/* Pragma definitions. */
c4x_cpu_version = 31;
else if (TARGET_C32)
c4x_cpu_version = 32;
+ else if (TARGET_C33)
+ c4x_cpu_version = 33;
else if (TARGET_C40)
c4x_cpu_version = 40;
else if (TARGET_C44)
c4x_cpu_version = atoi (p);
}
- target_flags &= ~(C30_FLAG | C31_FLAG | C32_FLAG | C40_FLAG | C44_FLAG);
+ target_flags &= ~(C30_FLAG | C31_FLAG | C32_FLAG | C33_FLAG |
+ C40_FLAG | C44_FLAG);
switch (c4x_cpu_version)
{
case 30: target_flags |= C30_FLAG; break;
case 31: target_flags |= C31_FLAG; break;
case 32: target_flags |= C32_FLAG; break;
+ case 33: target_flags |= C33_FLAG; break;
case 40: target_flags |= C40_FLAG; break;
case 44: target_flags |= C44_FLAG; break;
default:
target_flags |= C40_FLAG;
}
- if (TARGET_C30 || TARGET_C31 || TARGET_C32)
+ if (TARGET_C30 || TARGET_C31 || TARGET_C32 || TARGET_C33)
target_flags |= C3X_FLAG;
else
target_flags &= ~C3X_FLAG;
/* Define assembler options. */
#define ASM_SPEC "\
-%{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=40:%{!mcpu=44:\
-%{!m30:%{!m40:-m40}}}}}}} \
+%{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=33:%{!mcpu=40:%{!mcpu=44:\
+%{!m30:%{!m40:-m40}}}}}}}} \
%{mcpu=30:-m30} \
%{mcpu=31:-m31} \
%{mcpu=32:-m32} \
+%{mcpu=33:-m33} \
%{mcpu=40:-m40} \
%{mcpu=44:-m44} \
%{m30:-m30} \
%{m31:-m31} \
%{m32:-m32} \
+%{m33:-m33} \
%{m40:-m40} \
%{m44:-m44} \
%{mmemparm:-p} %{mregparm:-r} \
%{m30:--architecture c3x} \
%{m31:--architecture c3x} \
%{m32:--architecture c3x} \
+%{m33:--architecture c3x} \
%{mcpu=30:--architecture c3x} \
%{mcpu=31:--architecture c3x} \
-%{mcpu=32:--architecture c3x}"
+%{mcpu=32:--architecture c3x} \
+%{mcpu=33:--architecture c3x}"
/* Define C preprocessor options. */
#define CPP_SPEC "\
-%{!m30:%{!m31:%{!m32:%{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=40:%{!mcpu=44:\
- %{!m40:%{!m44:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40 }}}}}}}}}} \
+%{!m30:%{!m31:%{!m32:%{!m33:%{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=33:\
+%{!mcpu=40:%{!mcpu=44:%{\
+ !m40:%{!m44:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40}}}}}}}}}} \
%{mcpu=30:-D_TMS320C3x -D_C3x -D_TMS320C30 -D_C30 } \
%{m30:-D_TMS320C3x -D_C3x -D_TMS320C30 -D_C30 } \
%{mcpu=31:-D_TMS320C3x -D_C3x -D_TMS320C31 -D_C31 } \
%{m31:-D_TMS320C3x -D_C3x -D_TMS320C31 -D_C31 } \
%{mcpu=32:-D_TMS320C3x -D_C3x -D_TMS320C32 -D_C32 } \
%{m32:-D_TMS320C3x -D_C3x -D_TMS320C32 -D_C32 } \
+%{mcpu=33:-D_TMS320C3x -D_C3x -D_TMS320C33 -D_C33 } \
+%{m33:-D_TMS320C3x -D_C3x -D_TMS320C33 -D_C33 } \
%{mcpu=40:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40 } \
%{m40:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40 } \
%{mcpu=44:-D_TMS320C4x -D_C4x -D_TMS320C44 -D_C44 } \
#define C30_FLAG 0x0100000 /* Emit C30 code. */
#define C31_FLAG 0x0200000 /* Emit C31 code. */
#define C32_FLAG 0x0400000 /* Emit C32 code. */
+#define C33_FLAG 0x0400000 /* Emit C33 code. */
#define C40_FLAG 0x1000000 /* Emit C40 code. */
#define C44_FLAG 0x2000000 /* Emit C44 code. */
"Generate code for C31 CPU"}, \
{ "32", C32_FLAG, \
"Generate code for C32 CPU"}, \
+ { "33", C33_FLAG, \
+ "Generate code for C33 CPU"}, \
{ "40", C40_FLAG, \
"Generate code for C40 CPU"}, \
{ "44", C44_FLAG, \
#define TARGET_C30 (target_flags & C30_FLAG)
#define TARGET_C31 (target_flags & C31_FLAG)
#define TARGET_C32 (target_flags & C32_FLAG)
+#define TARGET_C33 (target_flags & C33_FLAG)
#define TARGET_C40 (target_flags & C40_FLAG)
#define TARGET_C44 (target_flags & C44_FLAG)