#define DCON_REG_ID 0
#define DCON_REG_MODE 1
-#define MODE_PASSTHRU (1<<0)
-#define MODE_SLEEP (1<<1)
-#define MODE_SLEEP_AUTO (1<<2)
-#define MODE_BL_ENABLE (1<<3)
-#define MODE_BLANK (1<<4)
-#define MODE_CSWIZZLE (1<<5)
-#define MODE_COL_AA (1<<6)
-#define MODE_MONO_LUMA (1<<7)
-#define MODE_SCAN_INT (1<<8)
-#define MODE_CLOCKDIV (1<<9)
-#define MODE_DEBUG (1<<14)
-#define MODE_SELFTEST (1<<15)
+#define MODE_PASSTHRU bit(0)
+#define MODE_SLEEP bit(1)
+#define MODE_SLEEP_AUTO bit(2)
+#define MODE_BL_ENABLE bit(3)
+#define MODE_BLANK bit(4)
+#define MODE_CSWIZZLE bit(5)
+#define MODE_COL_AA bit(6)
+#define MODE_MONO_LUMA bit(7)
+#define MODE_SCAN_INT bit(8)
+#define MODE_CLOCKDIV bit(9)
+#define MODE_DEBUG bit(14)
+#define MODE_SELFTEST bit(15)
#define DCON_REG_HRES 0x2
#define DCON_REG_HTOTAL 0x3
#define DCON_REG_MEM_OPT_B 0x42
/* Load Delay Locked Loop (DLL) settings for clock delay */
-#define MEM_DLL_CLOCK_DELAY (1<<0)
+#define MEM_DLL_CLOCK_DELAY bit(0)
/* Memory controller power down function */
-#define MEM_POWER_DOWN (1<<8)
+#define MEM_POWER_DOWN bit(8)
/* Memory controller software reset */
-#define MEM_SOFT_RESET (1<<0)
+#define MEM_SOFT_RESET bit(0)
/* Status values */