ram: rk3399: Add ddrtimingC0
authorJagan Teki <jagan@amarulasolutions.com>
Tue, 16 Jul 2019 11:57:05 +0000 (17:27 +0530)
committerKever Yang <kever.yang@rock-chips.com>
Sat, 20 Jul 2019 15:59:44 +0000 (23:59 +0800)
Add DdrTimingC0 structure with associated bit fields.

These would help to reconfigure sdram capabilities during
lpddr4 setup related configs.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
drivers/ram/rockchip/sdram_rk3399.c

index 471702f..7f41a67 100644 (file)
@@ -18,6 +18,16 @@ struct rk3399_ddr_pi_regs {
        u32 denali_pi[200];
 };
 
+union noc_ddrtimingc0 {
+       u32 d32;
+       struct {
+               unsigned burstpenalty : 4;
+               unsigned reserved0 : 4;
+               unsigned wrtomwr : 6;
+               unsigned reserved1 : 18;
+       } b;
+};
+
 struct rk3399_msch_regs {
        u32 coreid;
        u32 revisionid;
@@ -36,7 +46,7 @@ struct rk3399_msch_regs {
 struct rk3399_msch_timings {
        u32 ddrtiminga0;
        u32 ddrtimingb0;
-       u32 ddrtimingc0;
+       union noc_ddrtimingc0 ddrtimingc0;
        u32 devtodev0;
        u32 ddrmode;
        u32 agingx0;
index 7502199..d47e290 100644 (file)
@@ -1110,7 +1110,7 @@ static void dram_all_config(struct dram_info *dram,
                       &ddr_msch_regs->ddrtiminga0);
                writel(noc_timing->ddrtimingb0,
                       &ddr_msch_regs->ddrtimingb0);
-               writel(noc_timing->ddrtimingc0,
+               writel(noc_timing->ddrtimingc0.d32,
                       &ddr_msch_regs->ddrtimingc0);
                writel(noc_timing->devtodev0,
                       &ddr_msch_regs->devtodev0);