[REBASED on main (r3branch)from r2-stable branch]audio:ensure msic pll enabled during...

BZ: 17975

Race condition might occur when disabling the vibra and enabling the
audio path.  If vibra is already active and playback starts, msic pll
will be enabled immediately, otherwise it will be enabled during
vaud power on sequence.  In corner cases, vaud will be switched off
after pll is enabled and there after pll is not enabled. This causes
no audio on the sinks.

Enable the msic pll while powering up the vaud rail, irrespective
of it's previous state. This makes sure that pll is enabled all
the time while powering up the vaud for audio stream use cases.

Change-Id: I9964c009b4aff6a455aa2d49afdb4e1c044d4aa5
Old-Change-Id: I02e0aacca19d2b0dee5d1d8f528cdcd9ba651575
Signed-off-by: Ramesh Babu K V <ramesh.babu@intel.com>
Reviewed-on: http://android.intel.com:8080/29541
Reviewed-by: M, Arulselvan <arulselvan.m@intel.com>
Tested-by: M, Arulselvan <arulselvan.m@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>

diff --git a/sound/soc/codecs/sn95031.c b/sound/soc/codecs/sn95031.c
index b83aa44..8a79f1c 100644 (file)
--- a/sound/soc/codecs/sn95031.c
+++ b/sound/soc/codecs/sn95031.c
@@ -184,7 +184,10 @@ static int sn95031_set_vaud_bias(struct snd_soc_codec *codec,
                break;
 
        case SND_SOC_BIAS_PREPARE:
-               if (sn95031_ctx->pll_state == PLL_ENABLE_PENDING) {
+               pr_debug("bias_prepare\n");
+               /* enable msic pll only when any codec dai is active,
+                       not other use cases like static vibra etc */
+               if (codec->active) {
                        pr_debug("vaud_bias powering up pll\n");
                        intel_sst_set_pll(true, SST_PLL_MSIC);
                        /* allow few ms to stabilize the clock before