}
}
- if ((stat & DRQ_STAT) && rq_data_dir(rq) == READ && hwif->err_stops_fifo == 0)
+ if ((stat & DRQ_STAT) && rq_data_dir(rq) == READ &&
+ (hwif->host_flags & IDE_HFLAG_ERROR_STOPS_FIFO) == 0)
try_to_flush_leftover_data(drive);
if (rq->errors >= ERROR_MAX || blk_noretry_request(rq)) {
hwif->quirkproc = &pdcnew_quirkproc;
hwif->resetproc = &pdcnew_reset;
- hwif->err_stops_fifo = 1;
-
hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
if (hwif->dma_base == 0)
.init_chipset = init_chipset_pdcnew, \
.init_hwif = init_hwif_pdc202new, \
.host_flags = IDE_HFLAG_POST_SET_MODE | \
+ IDE_HFLAG_ERROR_STOPS_FIFO | \
IDE_HFLAG_OFF_BOARD, \
.pio_mask = ATA_PIO4, \
.mwdma_mask = ATA_MWDMA2, \
if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
hwif->resetproc = &pdc202xx_reset;
- hwif->err_stops_fifo = 1;
-
hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
if (hwif->dma_base == 0)
.init_hwif = init_hwif_pdc202xx, \
.init_dma = init_dma_pdc202xx, \
.extra = 48, \
- .host_flags = IDE_HFLAG_OFF_BOARD, \
+ .host_flags = IDE_HFLAG_ERROR_STOPS_FIFO | \
+ IDE_HFLAG_OFF_BOARD, \
.pio_mask = ATA_PIO4, \
.mwdma_mask = ATA_MWDMA2, \
.udma_mask = udma, \
.init_hwif = init_hwif_pdc202xx,
.init_dma = init_dma_pdc202xx,
.extra = 16,
- .host_flags = IDE_HFLAG_OFF_BOARD,
+ .host_flags = IDE_HFLAG_ERROR_STOPS_FIFO |
+ IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4,
.mwdma_mask = ATA_MWDMA2,
.udma_mask = ATA_UDMA2,
unsigned auto_poll : 1; /* supports nop auto-poll */
unsigned sg_mapped : 1; /* sg_table and sg_nents are ready */
unsigned no_io_32bit : 1; /* 1 = can not do 32-bit IO ops */
- unsigned err_stops_fifo : 1; /* 1=data FIFO is cleared by an error */
unsigned mmio : 1; /* host uses MMIO */
struct device gendev;
IDE_HFLAG_NO_LBA48 = (1 << 17),
/* no LBA48 DMA */
IDE_HFLAG_NO_LBA48_DMA = (1 << 18),
+ /* data FIFO is cleared by an error */
+ IDE_HFLAG_ERROR_STOPS_FIFO = (1 << 19),
};
#ifdef CONFIG_BLK_DEV_OFFBOARD