KVM: arm/arm64: vgic-new: Add SGIPENDR register handlers

As this register is v2 specific, its implementation lives entirely
in vgic-mmio-v2.c.
This register allows setting the source mask of an IPI.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>

diff --git a/virt/kvm/arm/vgic/vgic-mmio-v2.c b/virt/kvm/arm/vgic/vgic-mmio-v2.c
index c884e9b..3925d4c 100644 (file)
--- a/virt/kvm/arm/vgic/vgic-mmio-v2.c
+++ b/virt/kvm/arm/vgic/vgic-mmio-v2.c
@@ -146,6 +146,64 @@ static void vgic_mmio_write_target(struct kvm_vcpu *vcpu,
        }
 }
 
+static unsigned long vgic_mmio_read_sgipend(struct kvm_vcpu *vcpu,
+                                           gpa_t addr, unsigned int len)
+{
+       u32 intid = addr & 0x0f;
+       int i;
+       u64 val = 0;
+
+       for (i = 0; i < len; i++) {
+               struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
+
+               val |= (u64)irq->source << (i * 8);
+       }
+       return val;
+}
+
+static void vgic_mmio_write_sgipendc(struct kvm_vcpu *vcpu,
+                                    gpa_t addr, unsigned int len,
+                                    unsigned long val)
+{
+       u32 intid = addr & 0x0f;
+       int i;
+
+       for (i = 0; i < len; i++) {
+               struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
+
+               spin_lock(&irq->irq_lock);
+
+               irq->source &= ~((val >> (i * 8)) & 0xff);
+               if (!irq->source)
+                       irq->pending = false;
+
+               spin_unlock(&irq->irq_lock);
+       }
+}
+
+static void vgic_mmio_write_sgipends(struct kvm_vcpu *vcpu,
+                                    gpa_t addr, unsigned int len,
+                                    unsigned long val)
+{
+       u32 intid = addr & 0x0f;
+       int i;
+
+       for (i = 0; i < len; i++) {
+               struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
+
+               spin_lock(&irq->irq_lock);
+
+               irq->source |= (val >> (i * 8)) & 0xff;
+
+               if (irq->source) {
+                       irq->pending = true;
+                       vgic_queue_irq_unlock(vcpu->kvm, irq);
+               } else {
+                       spin_unlock(&irq->irq_lock);
+               }
+       }
+}
+
 static const struct vgic_register_region vgic_v2_dist_registers[] = {
        REGISTER_DESC_WITH_LENGTH(GIC_DIST_CTRL,
                vgic_mmio_read_v2_misc, vgic_mmio_write_v2_misc, 12,
@@ -184,10 +242,10 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = {
                vgic_mmio_read_raz, vgic_mmio_write_sgir, 4,
                VGIC_ACCESS_32bit),
        REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_CLEAR,
-               vgic_mmio_read_raz, vgic_mmio_write_wi, 16,
+               vgic_mmio_read_sgipend, vgic_mmio_write_sgipendc, 16,
                VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
        REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_SET,
-               vgic_mmio_read_raz, vgic_mmio_write_wi, 16,
+               vgic_mmio_read_sgipend, vgic_mmio_write_sgipends, 16,
                VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 };