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ARM: dts: imx6qdl-sabreauto: Allow HDMI and LVDS to work simultaneously
author
Fabio Estevam
<fabio.estevam@freescale.com>
Mon, 13 Jul 2015 16:03:05 +0000
(13:03 -0300)
committer
Shawn Guo
<shawnguo@kernel.org>
Tue, 11 Aug 2015 15:15:15 +0000
(23:15 +0800)
Currently it is not possible to have HDMI and LVDS working simultaneously,
because both ports try to use PLL5.
Move the LVDS clock parent to PLL3_USB_OTG, so that HDMI and LVDS can be
driven from independent sources.
With this change the LDB pixel clock goes to 68.57 MHz, which is still
within the valid range for the HSD100PXN1 LVDS panel.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
patch
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diff --git
a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index
6b17b85
..
8d52481
100644
(file)
--- a/
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@
-93,9
+93,13
@@
&clks {
assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
<&clks IMX6QDL_PLL4_BYPASS>,
- <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
+ <&clks IMX6QDL_CLK_PLL4_POST_DIV>,
+ <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
- <&clks IMX6QDL_PLL4_BYPASS_SRC>;
+ <&clks IMX6QDL_PLL4_BYPASS_SRC>,
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
assigned-clock-rates = <0>, <0>, <24576000>;
};