"regalloc-model", cl::Hidden,
cl::desc("The model being trained for register allocation eviction"));
+extern cl::opt<unsigned> EvictInterferenceCutoff;
+
#endif // #ifdef LLVM_HAVE_TF_API
/// The score injection pass.
LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
// Different from the default heuristic, we don't make any assumptions about
// what having more than 10 results in the query may mean.
- const auto &IFIntervals = Q.interferingVRegs();
+ const auto &IFIntervals = Q.interferingVRegs(EvictInterferenceCutoff);
if (IFIntervals.empty() && InterferingIntervals.empty())
continue;
+ if (IFIntervals.size() >= EvictInterferenceCutoff)
+ return false;
InterferingIntervals.append(IFIntervals.begin(), IFIntervals.end());
for (LiveInterval *Intf : reverse(IFIntervals)) {
assert(Register::isVirtualRegister(Intf->reg()) &&
"may be compile time intensive"),
cl::init(false));
+cl::opt<unsigned> EvictInterferenceCutoff(
+ "regalloc-eviction-max-interference-cutoff", cl::Hidden,
+ cl::desc("Number of interferences after which we declare "
+ "an interference unevictable and bail out. This "
+ "is a compilation cost-saving consideration. To "
+ "disable, pass a very large number."),
+ cl::init(10));
+
#define DEBUG_TYPE "regalloc"
#ifdef LLVM_HAVE_TF_AOT_REGALLOCEVICTMODEL
#define LLVM_HAVE_TF_AOT
for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
// If there is 10 or more interferences, chances are one is heavier.
- const auto &Interferences = Q.interferingVRegs(10);
- if (Interferences.size() >= 10)
+ const auto &Interferences = Q.interferingVRegs(EvictInterferenceCutoff);
+ if (Interferences.size() >= EvictInterferenceCutoff)
return false;
// Check if any interfering live range is heavier than MaxWeight.