crypto: hisilicon/hpre - add two RAS correctable errors processing

1.One CE error is detecting timeout of generating a random number.
2.Another is detecting timeout of SVA prefetching address.

Signed-off-by: Hui Tang <tanghui20@huawei.com>
Reviewed-by: Zaibo Xu <xuzaibo@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/hisilicon/hpre/hpre_main.c b/drivers/crypto/hisilicon/hpre/hpre_main.c
index bf1fa08..d46086e 100644 (file)
--- a/drivers/crypto/hisilicon/hpre/hpre_main.c
+++ b/drivers/crypto/hisilicon/hpre/hpre_main.c
@@ -45,7 +45,7 @@
 #define HPRE_CORE_IS_SCHD_OFFSET       0x90
 
 #define HPRE_RAS_CE_ENB                        0x301410
-#define HPRE_HAC_RAS_CE_ENABLE         0x1
+#define HPRE_HAC_RAS_CE_ENABLE         (BIT(0) | BIT(22) | BIT(23))
 #define HPRE_RAS_NFE_ENB               0x301414
 #define HPRE_HAC_RAS_NFE_ENABLE                0x3ffffe
 #define HPRE_RAS_FE_ENB                        0x301418
@@ -129,7 +129,11 @@ static const struct hpre_hw_error hpre_hw_errors[] = {
        { .int_msk = BIT(9), .msg = "cluster4_shb_timeout_int_set" },
        { .int_msk = GENMASK(15, 10), .msg = "ooo_rdrsp_err_int_set" },
        { .int_msk = GENMASK(21, 16), .msg = "ooo_wrrsp_err_int_set" },
-       { /* sentinel */ }
+       { .int_msk = BIT(22), .msg = "pt_rng_timeout_int_set"},
+       { .int_msk = BIT(23), .msg = "sva_fsm_timeout_int_set"},
+       {
+               /* sentinel */
+       }
 };
 
 static const u64 hpre_cluster_offsets[] = {