Merge branch 'next/cleanup' into HEAD
authorOlof Johansson <olof@lixom.net>
Mon, 1 Oct 2012 21:15:02 +0000 (14:15 -0700)
committerOlof Johansson <olof@lixom.net>
Mon, 1 Oct 2012 21:15:02 +0000 (14:15 -0700)
Conflicts:
drivers/staging/tidspbridge/core/wdt.c
drivers/usb/host/Kconfig
drivers/w1/masters/omap_hdq.c

623 files changed:
Documentation/arm/Samsung-S3C24XX/GPIO.txt
Documentation/arm/Samsung/GPIO.txt
Documentation/arm/memory.txt
Documentation/devicetree/bindings/arm/pmu.txt
MAINTAINERS
arch/arm/Kconfig
arch/arm/Makefile
arch/arm/boot/dts/imx27-phytec-phycore.dts
arch/arm/boot/dts/tegra20-harmony.dts
arch/arm/configs/pnx4008_defconfig [deleted file]
arch/arm/configs/prima2_defconfig
arch/arm/configs/tegra_defconfig
arch/arm/include/asm/hardware/iop3xx.h
arch/arm/include/asm/io.h
arch/arm/include/asm/mach/map.h
arch/arm/include/asm/mach/pci.h
arch/arm/include/asm/perf_event.h
arch/arm/include/asm/pmu.h
arch/arm/kernel/Makefile
arch/arm/kernel/bios32.c
arch/arm/kernel/perf_event.c
arch/arm/kernel/perf_event_cpu.c [new file with mode: 0644]
arch/arm/kernel/perf_event_v6.c
arch/arm/kernel/perf_event_v7.c
arch/arm/kernel/perf_event_xscale.c
arch/arm/kernel/pmu.c [deleted file]
arch/arm/mach-at91/at91x40.c
arch/arm/mach-at91/at91x40_time.c
arch/arm/mach-at91/include/mach/hardware.h
arch/arm/mach-at91/include/mach/uncompress.h
arch/arm/mach-at91/setup.c
arch/arm/mach-bcmring/arch.c
arch/arm/mach-bcmring/core.c
arch/arm/mach-bcmring/csp/chipc/chipcHw.c
arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
arch/arm/mach-bcmring/csp/dmac/dmacHw.c
arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
arch/arm/mach-bcmring/csp/tmr/tmrHw.c
arch/arm/mach-bcmring/include/cfg_global.h [deleted file]
arch/arm/mach-bcmring/include/csp/cache.h [deleted file]
arch/arm/mach-bcmring/include/csp/delay.h [deleted file]
arch/arm/mach-bcmring/include/csp/errno.h [deleted file]
arch/arm/mach-bcmring/include/csp/intcHw.h [deleted file]
arch/arm/mach-bcmring/include/csp/module.h [deleted file]
arch/arm/mach-bcmring/include/csp/secHw.h [deleted file]
arch/arm/mach-bcmring/include/csp/stdint.h [deleted file]
arch/arm/mach-bcmring/include/csp/string.h [deleted file]
arch/arm/mach-bcmring/include/mach/cfg_global.h [moved from arch/arm/mach-bcmring/include/cfg_global_defines.h with 74% similarity]
arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
arch/arm/mach-bcmring/include/mach/csp/dmacHw.h [moved from arch/arm/mach-bcmring/include/csp/dmacHw.h with 99% similarity]
arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
arch/arm/mach-bcmring/include/mach/csp/mm_io.h
arch/arm/mach-bcmring/include/mach/csp/reg.h [moved from arch/arm/mach-bcmring/include/csp/reg.h with 81% similarity]
arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
arch/arm/mach-bcmring/include/mach/csp/tmrHw.h [moved from arch/arm/mach-bcmring/include/csp/tmrHw.h with 99% similarity]
arch/arm/mach-bcmring/include/mach/dma.h
arch/arm/mach-bcmring/include/mach/hardware.h
arch/arm/mach-bcmring/include/mach/reg_nand.h
arch/arm/mach-bcmring/include/mach/reg_umi.h
arch/arm/mach-bcmring/mm.c
arch/arm/mach-bcmring/timer.c
arch/arm/mach-dove/common.c
arch/arm/mach-dove/include/mach/dove.h
arch/arm/mach-dove/include/mach/io.h [deleted file]
arch/arm/mach-dove/pcie.c
arch/arm/mach-ebsa110/core.c
arch/arm/mach-ebsa110/core.h
arch/arm/mach-exynos/clock-exynos5.c
arch/arm/mach-exynos/include/mach/map.h
arch/arm/mach-footbridge/common.c
arch/arm/mach-footbridge/dc21285.c
arch/arm/mach-footbridge/include/mach/debug-macro.S
arch/arm/mach-footbridge/include/mach/io.h
arch/arm/mach-imx/Makefile
arch/arm/mach-imx/clk-imx21.c
arch/arm/mach-imx/clk-imx51-imx53.c
arch/arm/mach-imx/clk-pllv1.c
arch/arm/mach-imx/clk.c [new file with mode: 0644]
arch/arm/mach-imx/clk.h
arch/arm/mach-imx/mach-kzm_arm11_01.c
arch/arm/mach-imx/mach-mx31ads.c
arch/arm/mach-imx/mach-mx31lite.c
arch/arm/mach-integrator/core.c
arch/arm/mach-integrator/cpu.c
arch/arm/mach-integrator/include/mach/io.h [deleted file]
arch/arm/mach-integrator/include/mach/platform.h
arch/arm/mach-integrator/integrator_ap.c
arch/arm/mach-integrator/integrator_cp.c
arch/arm/mach-integrator/pci_v3.c
arch/arm/mach-iop13xx/include/mach/io.h [deleted file]
arch/arm/mach-iop13xx/include/mach/iop13xx.h
arch/arm/mach-iop13xx/include/mach/memory.h
arch/arm/mach-iop13xx/io.c
arch/arm/mach-iop13xx/pci.c
arch/arm/mach-iop13xx/pci.h
arch/arm/mach-iop13xx/setup.c
arch/arm/mach-iop32x/glantank.c
arch/arm/mach-iop32x/include/mach/io.h [deleted file]
arch/arm/mach-iop33x/include/mach/io.h [deleted file]
arch/arm/mach-ixp4xx/common.c
arch/arm/mach-ixp4xx/include/mach/cpu.h
arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
arch/arm/mach-kirkwood/common.c
arch/arm/mach-kirkwood/include/mach/io.h [deleted file]
arch/arm/mach-kirkwood/include/mach/kirkwood.h
arch/arm/mach-kirkwood/pcie.c
arch/arm/mach-ks8695/cpu.c
arch/arm/mach-ks8695/include/mach/hardware.h
arch/arm/mach-ks8695/include/mach/regs-timer.h [deleted file]
arch/arm/mach-ks8695/include/mach/uncompress.h
arch/arm/mach-ks8695/time.c
arch/arm/mach-lpc32xx/common.c
arch/arm/mach-lpc32xx/include/mach/hardware.h
arch/arm/mach-mmp/Makefile
arch/arm/mach-mmp/clock-mmp2.c [new file with mode: 0644]
arch/arm/mach-mmp/clock-pxa168.c [new file with mode: 0644]
arch/arm/mach-mmp/clock-pxa910.c [new file with mode: 0644]
arch/arm/mach-mmp/common.h
arch/arm/mach-mmp/include/mach/regs-apbc.h
arch/arm/mach-mmp/include/mach/regs-apmu.h
arch/arm/mach-mmp/irq.c
arch/arm/mach-mmp/mmp2.c
arch/arm/mach-mmp/pxa168.c
arch/arm/mach-mmp/pxa910.c
arch/arm/mach-msm/Makefile
arch/arm/mach-msm/acpuclock-arm11.c [deleted file]
arch/arm/mach-msm/acpuclock.h [deleted file]
arch/arm/mach-msm/board-mahimahi.c
arch/arm/mach-msm/board-msm7x27.c [deleted file]
arch/arm/mach-msm/board-sapphire.c
arch/arm/mach-msm/clock-pcom.c
arch/arm/mach-msm/dma.c
arch/arm/mach-msm/idle.c [deleted file]
arch/arm/mach-msm/include/mach/board.h
arch/arm/mach-msm/include/mach/system.h [deleted file]
arch/arm/mach-msm/io.c
arch/arm/mach-msm/proc_comm.c
arch/arm/mach-msm/smd.c
arch/arm/mach-msm/timer.c
arch/arm/mach-mv78xx0/addr-map.c
arch/arm/mach-mv78xx0/common.c
arch/arm/mach-mv78xx0/include/mach/io.h [deleted file]
arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
arch/arm/mach-mv78xx0/pcie.c
arch/arm/mach-nomadik/include/mach/hardware.h
arch/arm/mach-nomadik/include/mach/uncompress.h
arch/arm/mach-omap1/ams-delta-fiq-handler.S
arch/arm/mach-omap1/ams-delta-fiq.c
arch/arm/mach-omap1/board-ams-delta.c
arch/arm/mach-omap1/board-fsample.c
arch/arm/mach-omap1/board-generic.c
arch/arm/mach-omap1/board-h2.c
arch/arm/mach-omap1/board-h3.c
arch/arm/mach-omap1/board-htcherald.c
arch/arm/mach-omap1/board-innovator.c
arch/arm/mach-omap1/board-nokia770.c
arch/arm/mach-omap1/board-osk.c
arch/arm/mach-omap1/board-palmte.c
arch/arm/mach-omap1/board-palmtt.c
arch/arm/mach-omap1/board-palmz71.c
arch/arm/mach-omap1/board-perseus2.c
arch/arm/mach-omap1/board-sx1-mmc.c
arch/arm/mach-omap1/board-sx1.c
arch/arm/mach-omap1/board-voiceblue.c
arch/arm/mach-omap1/clock.c
arch/arm/mach-omap1/clock_data.c
arch/arm/mach-omap1/devices.c
arch/arm/mach-omap1/dma.c
arch/arm/mach-omap1/flash.c
arch/arm/mach-omap1/gpio15xx.c
arch/arm/mach-omap1/gpio16xx.c
arch/arm/mach-omap1/gpio7xx.c
arch/arm/mach-omap1/i2c.c
arch/arm/mach-omap1/include/mach/ams-delta-fiq.h
arch/arm/mach-omap1/include/mach/board-ams-delta.h [moved from arch/arm/plat-omap/include/plat/board-ams-delta.h with 100% similarity]
arch/arm/mach-omap1/include/mach/board-sx1.h [moved from arch/arm/plat-omap/include/plat/board-sx1.h with 100% similarity]
arch/arm/mach-omap1/include/mach/board-voiceblue.h [moved from arch/arm/plat-omap/include/plat/board-voiceblue.h with 100% similarity]
arch/arm/mach-omap1/include/mach/flash.h [moved from arch/arm/plat-omap/include/plat/flash.h with 100% similarity]
arch/arm/mach-omap1/include/mach/gpio.h
arch/arm/mach-omap1/include/mach/hardware.h
arch/arm/mach-omap1/include/mach/irda.h [moved from arch/arm/plat-omap/include/plat/irda.h with 100% similarity]
arch/arm/mach-omap1/include/mach/irqs.h
arch/arm/mach-omap1/include/mach/mux.h [moved from arch/arm/plat-omap/include/plat/mux.h with 100% similarity]
arch/arm/mach-omap1/include/mach/omap1510.h [moved from arch/arm/plat-omap/include/plat/omap1510.h with 97% similarity]
arch/arm/mach-omap1/include/mach/omap16xx.h [moved from arch/arm/plat-omap/include/plat/omap16xx.h with 99% similarity]
arch/arm/mach-omap1/include/mach/omap7xx.h [moved from arch/arm/plat-omap/include/plat/omap7xx.h with 98% similarity]
arch/arm/mach-omap1/include/mach/smp.h [deleted file]
arch/arm/mach-omap1/io.c
arch/arm/mach-omap1/lcd_dma.c
arch/arm/mach-omap1/leds-h2p2-debug.c
arch/arm/mach-omap1/leds.c
arch/arm/mach-omap1/mcbsp.c
arch/arm/mach-omap1/mux.c
arch/arm/mach-omap1/pm.c
arch/arm/mach-omap1/serial.c
arch/arm/mach-omap1/usb.c
arch/arm/mach-omap2/Makefile
arch/arm/mach-omap2/am33xx.h [moved from arch/arm/plat-omap/include/plat/am33xx.h with 100% similarity]
arch/arm/mach-omap2/am35xx-emac.c
arch/arm/mach-omap2/am35xx.h [moved from arch/arm/mach-omap2/include/mach/am35xx.h with 100% similarity]
arch/arm/mach-omap2/board-2430sdp.c
arch/arm/mach-omap2/board-3430sdp.c
arch/arm/mach-omap2/board-3630sdp.c
arch/arm/mach-omap2/board-4430sdp.c
arch/arm/mach-omap2/board-am3517crane.c
arch/arm/mach-omap2/board-am3517evm.c
arch/arm/mach-omap2/board-apollon.c
arch/arm/mach-omap2/board-cm-t35.c
arch/arm/mach-omap2/board-cm-t3517.c
arch/arm/mach-omap2/board-devkit8000.c
arch/arm/mach-omap2/board-flash.c
arch/arm/mach-omap2/board-generic.c
arch/arm/mach-omap2/board-h4.c
arch/arm/mach-omap2/board-igep0020.c
arch/arm/mach-omap2/board-ldp.c
arch/arm/mach-omap2/board-n8x0.c
arch/arm/mach-omap2/board-omap3beagle.c
arch/arm/mach-omap2/board-omap3evm.c
arch/arm/mach-omap2/board-omap3logic.c
arch/arm/mach-omap2/board-omap3pandora.c
arch/arm/mach-omap2/board-omap3stalker.c
arch/arm/mach-omap2/board-omap3touchbook.c
arch/arm/mach-omap2/board-omap4panda.c
arch/arm/mach-omap2/board-overo.c
arch/arm/mach-omap2/board-rm680.c
arch/arm/mach-omap2/board-rx51-peripherals.c
arch/arm/mach-omap2/board-rx51-video.c
arch/arm/mach-omap2/board-rx51.c
arch/arm/mach-omap2/board-rx51.h [moved from arch/arm/mach-omap2/include/mach/board-rx51.h with 100% similarity]
arch/arm/mach-omap2/board-ti8168evm.c
arch/arm/mach-omap2/board-zoom-debugboard.c
arch/arm/mach-omap2/board-zoom-display.c
arch/arm/mach-omap2/board-zoom-peripherals.c
arch/arm/mach-omap2/board-zoom.c
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
arch/arm/mach-omap2/clkt34xx_dpll3m2.c
arch/arm/mach-omap2/clkt_clksel.c
arch/arm/mach-omap2/clkt_dpll.c
arch/arm/mach-omap2/clock.c
arch/arm/mach-omap2/clock2420_data.c
arch/arm/mach-omap2/clock2430.c
arch/arm/mach-omap2/clock2430_data.c
arch/arm/mach-omap2/clock2xxx.c
arch/arm/mach-omap2/clock33xx_data.c
arch/arm/mach-omap2/clock3xxx.c
arch/arm/mach-omap2/clock3xxx_data.c
arch/arm/mach-omap2/clock44xx_data.c
arch/arm/mach-omap2/clockdomain.c
arch/arm/mach-omap2/cm2xxx_3xxx.c
arch/arm/mach-omap2/common-board-devices.c
arch/arm/mach-omap2/common.c
arch/arm/mach-omap2/common.h
arch/arm/mach-omap2/control.c
arch/arm/mach-omap2/control.h
arch/arm/mach-omap2/cpuidle34xx.c
arch/arm/mach-omap2/ctrl_module_core_44xx.h [moved from arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h with 100% similarity]
arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h [moved from arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h with 100% similarity]
arch/arm/mach-omap2/ctrl_module_pad_wkup_44xx.h [moved from arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h with 100% similarity]
arch/arm/mach-omap2/ctrl_module_wkup_44xx.h [moved from arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h with 100% similarity]
arch/arm/mach-omap2/debug-devices.h [new file with mode: 0644]
arch/arm/mach-omap2/devices.c
arch/arm/mach-omap2/dpll3xxx.c
arch/arm/mach-omap2/dpll44xx.c
arch/arm/mach-omap2/dsp.c
arch/arm/mach-omap2/emu.c
arch/arm/mach-omap2/gpio.c
arch/arm/mach-omap2/gpmc-nand.c
arch/arm/mach-omap2/gpmc-onenand.c
arch/arm/mach-omap2/gpmc-smc91x.c
arch/arm/mach-omap2/gpmc-smc91x.h [moved from arch/arm/plat-omap/include/plat/gpmc-smc91x.h with 100% similarity]
arch/arm/mach-omap2/gpmc-smsc911x.c
arch/arm/mach-omap2/gpmc-smsc911x.h [moved from arch/arm/plat-omap/include/plat/gpmc-smsc911x.h with 100% similarity]
arch/arm/mach-omap2/gpmc.c
arch/arm/mach-omap2/hdq1w.c
arch/arm/mach-omap2/hdq1w.h [moved from arch/arm/plat-omap/include/plat/hdq1w.h with 100% similarity]
arch/arm/mach-omap2/hsmmc.c
arch/arm/mach-omap2/i2c.c
arch/arm/mach-omap2/id.c
arch/arm/mach-omap2/id.h [moved from arch/arm/mach-omap2/include/mach/id.h with 100% similarity]
arch/arm/mach-omap2/include/mach/gpio.h
arch/arm/mach-omap2/include/mach/hardware.h
arch/arm/mach-omap2/include/mach/irqs.h
arch/arm/mach-omap2/include/mach/smp.h [deleted file]
arch/arm/mach-omap2/io.c
arch/arm/mach-omap2/irq.c
arch/arm/mach-omap2/l3_2xxx.h [moved from arch/arm/plat-omap/include/plat/l3_2xxx.h with 100% similarity]
arch/arm/mach-omap2/l3_3xxx.h [moved from arch/arm/plat-omap/include/plat/l3_3xxx.h with 100% similarity]
arch/arm/mach-omap2/l4_2xxx.h [moved from arch/arm/plat-omap/include/plat/l4_2xxx.h with 100% similarity]
arch/arm/mach-omap2/l4_3xxx.h [moved from arch/arm/plat-omap/include/plat/l4_3xxx.h with 100% similarity]
arch/arm/mach-omap2/mailbox.c
arch/arm/mach-omap2/mcbsp.c
arch/arm/mach-omap2/msdi.c
arch/arm/mach-omap2/omap-hotplug.c
arch/arm/mach-omap2/omap-iommu.c
arch/arm/mach-omap2/omap-mpuss-lowpower.c
arch/arm/mach-omap2/omap-secure.c
arch/arm/mach-omap2/omap-secure.h [moved from arch/arm/mach-omap2/include/mach/omap-secure.h with 100% similarity]
arch/arm/mach-omap2/omap-smp.c
arch/arm/mach-omap2/omap-wakeupgen.c
arch/arm/mach-omap2/omap-wakeupgen.h [moved from arch/arm/mach-omap2/include/mach/omap-wakeupgen.h with 100% similarity]
arch/arm/mach-omap2/omap24xx.h [moved from arch/arm/plat-omap/include/plat/omap24xx.h with 98% similarity]
arch/arm/mach-omap2/omap34xx.h [moved from arch/arm/plat-omap/include/plat/omap34xx.h with 98% similarity]
arch/arm/mach-omap2/omap4-common.c
arch/arm/mach-omap2/omap4-keypad.h [moved from arch/arm/plat-omap/include/plat/omap4-keypad.h with 87% similarity]
arch/arm/mach-omap2/omap44xx.h [moved from arch/arm/plat-omap/include/plat/omap44xx.h with 97% similarity]
arch/arm/mach-omap2/omap54xx.h [moved from arch/arm/plat-omap/include/plat/omap54xx.h with 100% similarity]
arch/arm/mach-omap2/omap_hwmod.c
arch/arm/mach-omap2/omap_hwmod_2420_data.c
arch/arm/mach-omap2/omap_hwmod_2430_data.c
arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
arch/arm/mach-omap2/omap_hwmod_common_data.h
arch/arm/mach-omap2/omap_l3_noc.c
arch/arm/mach-omap2/omap_phy_internal.c
arch/arm/mach-omap2/opp.c
arch/arm/mach-omap2/opp2420_data.c
arch/arm/mach-omap2/opp2430_data.c
arch/arm/mach-omap2/opp3xxx_data.c
arch/arm/mach-omap2/opp4xxx_data.c
arch/arm/mach-omap2/pm-debug.c
arch/arm/mach-omap2/pm.c
arch/arm/mach-omap2/pm24xx.c
arch/arm/mach-omap2/pm34xx.c
arch/arm/mach-omap2/pm44xx.c
arch/arm/mach-omap2/powerdomain.c
arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
arch/arm/mach-omap2/powerdomain44xx.c
arch/arm/mach-omap2/powerdomains3xxx_data.c
arch/arm/mach-omap2/prcm.c
arch/arm/mach-omap2/prm2xxx_3xxx.c
arch/arm/mach-omap2/prm44xx.c
arch/arm/mach-omap2/prm_common.c
arch/arm/mach-omap2/sdrc2xxx.c
arch/arm/mach-omap2/serial.c
arch/arm/mach-omap2/sleep24xx.S
arch/arm/mach-omap2/sleep34xx.S
arch/arm/mach-omap2/sleep44xx.S
arch/arm/mach-omap2/soc.h [new file with mode: 0644]
arch/arm/mach-omap2/sr_device.c
arch/arm/mach-omap2/sram242x.S
arch/arm/mach-omap2/sram243x.S
arch/arm/mach-omap2/sram34xx.S
arch/arm/mach-omap2/ti81xx.h [moved from arch/arm/plat-omap/include/plat/ti81xx.h with 100% similarity]
arch/arm/mach-omap2/timer.c
arch/arm/mach-omap2/twl-common.c
arch/arm/mach-omap2/twl-common.h
arch/arm/mach-omap2/usb-host.c
arch/arm/mach-omap2/usb-musb.c
arch/arm/mach-omap2/vc.c
arch/arm/mach-omap2/voltage.c
arch/arm/mach-omap2/voltage.h
arch/arm/mach-omap2/voltagedomains3xxx_data.c
arch/arm/mach-omap2/vp.c
arch/arm/mach-orion5x/common.c
arch/arm/mach-orion5x/include/mach/io.h [deleted file]
arch/arm/mach-orion5x/include/mach/orion5x.h
arch/arm/mach-orion5x/pci.c
arch/arm/mach-pnx4008/Makefile [deleted file]
arch/arm/mach-pnx4008/Makefile.boot [deleted file]
arch/arm/mach-pnx4008/clock.c [deleted file]
arch/arm/mach-pnx4008/clock.h [deleted file]
arch/arm/mach-pnx4008/core.c [deleted file]
arch/arm/mach-pnx4008/dma.c [deleted file]
arch/arm/mach-pnx4008/gpio.c [deleted file]
arch/arm/mach-pnx4008/i2c.c [deleted file]
arch/arm/mach-pnx4008/include/mach/clock.h [deleted file]
arch/arm/mach-pnx4008/include/mach/debug-macro.S [deleted file]
arch/arm/mach-pnx4008/include/mach/dma.h [deleted file]
arch/arm/mach-pnx4008/include/mach/entry-macro.S [deleted file]
arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h [deleted file]
arch/arm/mach-pnx4008/include/mach/hardware.h [deleted file]
arch/arm/mach-pnx4008/include/mach/irq.h [deleted file]
arch/arm/mach-pnx4008/include/mach/irqs.h [deleted file]
arch/arm/mach-pnx4008/include/mach/param.h [deleted file]
arch/arm/mach-pnx4008/include/mach/platform.h [deleted file]
arch/arm/mach-pnx4008/include/mach/pm.h [deleted file]
arch/arm/mach-pnx4008/include/mach/timex.h [deleted file]
arch/arm/mach-pnx4008/include/mach/uncompress.h [deleted file]
arch/arm/mach-pnx4008/irq.c [deleted file]
arch/arm/mach-pnx4008/pm.c [deleted file]
arch/arm/mach-pnx4008/serial.c [deleted file]
arch/arm/mach-pnx4008/sleep.S [deleted file]
arch/arm/mach-pnx4008/time.c [deleted file]
arch/arm/mach-pnx4008/time.h [deleted file]
arch/arm/mach-prima2/Kconfig [new file with mode: 0644]
arch/arm/mach-prima2/Makefile
arch/arm/mach-prima2/common.c [moved from arch/arm/mach-prima2/prima2.c with 81% similarity]
arch/arm/mach-prima2/include/mach/uncompress.h
arch/arm/mach-prima2/irq.c
arch/arm/mach-pxa/devices.c
arch/arm/mach-realview/realview_eb.c
arch/arm/mach-realview/realview_pb1176.c
arch/arm/mach-realview/realview_pb11mp.c
arch/arm/mach-realview/realview_pba8.c
arch/arm/mach-realview/realview_pbx.c
arch/arm/mach-s3c24xx/h1940-bluetooth.c
arch/arm/mach-s3c24xx/mach-anubis.c
arch/arm/mach-s3c24xx/mach-jive.c
arch/arm/mach-s3c24xx/mach-mini2440.c
arch/arm/mach-s3c24xx/mach-nexcoder.c
arch/arm/mach-s3c24xx/mach-osiris-dvs.c
arch/arm/mach-s3c24xx/mach-osiris.c
arch/arm/mach-sa1100/include/mach/simpad.h
arch/arm/mach-sa1100/simpad.c
arch/arm/mach-shark/core.c
arch/arm/mach-shark/include/mach/debug-macro.S
arch/arm/mach-shark/include/mach/entry-macro.S
arch/arm/mach-shark/include/mach/io.h [deleted file]
arch/arm/mach-shark/pci.c
arch/arm/mach-shmobile/board-ag5evm.c
arch/arm/mach-shmobile/board-ap4evb.c
arch/arm/mach-shmobile/board-armadillo800eva.c
arch/arm/mach-shmobile/board-bonito.c
arch/arm/mach-shmobile/board-g3evm.c
arch/arm/mach-shmobile/board-g4evm.c
arch/arm/mach-shmobile/board-kzm9g.c
arch/arm/mach-shmobile/board-mackerel.c
arch/arm/mach-shmobile/clock-r8a7740.c
arch/arm/mach-shmobile/clock-sh7367.c
arch/arm/mach-shmobile/clock-sh7372.c
arch/arm/mach-shmobile/clock-sh7377.c
arch/arm/mach-shmobile/clock-sh73a0.c
arch/arm/mach-shmobile/include/mach/gpio.h
arch/arm/mach-shmobile/intc-r8a7779.c
arch/arm/mach-shmobile/intc-sh7372.c
arch/arm/mach-shmobile/intc-sh73a0.c
arch/arm/mach-shmobile/pm-rmobile.c
arch/arm/mach-shmobile/pm-sh7372.c
arch/arm/mach-shmobile/setup-sh7367.c
arch/arm/mach-shmobile/setup-sh7377.c
arch/arm/mach-shmobile/setup-sh73a0.c
arch/arm/mach-spear13xx/include/mach/spear.h
arch/arm/mach-spear13xx/spear13xx.c
arch/arm/mach-tegra/Kconfig
arch/arm/mach-tegra/Makefile
arch/arm/mach-tegra/apbio.c
arch/arm/mach-tegra/board-dt-tegra20.c
arch/arm/mach-tegra/board-harmony-pcie.c
arch/arm/mach-tegra/board-harmony-pinmux.c [deleted file]
arch/arm/mach-tegra/board-harmony-power.c [deleted file]
arch/arm/mach-tegra/board-harmony.c [deleted file]
arch/arm/mach-tegra/board-harmony.h [deleted file]
arch/arm/mach-tegra/board-paz00-pinmux.c [deleted file]
arch/arm/mach-tegra/board-paz00.c
arch/arm/mach-tegra/board-paz00.h
arch/arm/mach-tegra/board-trimslice-pinmux.c [deleted file]
arch/arm/mach-tegra/board-trimslice.c [deleted file]
arch/arm/mach-tegra/board-trimslice.h [deleted file]
arch/arm/mach-tegra/devices.c
arch/arm/mach-tegra/dma.c [deleted file]
arch/arm/mach-tegra/fuse.c
arch/arm/mach-tegra/include/mach/dma.h
arch/arm/mach-tegra/include/mach/io.h [deleted file]
arch/arm/mach-tegra/include/mach/iomap.h
arch/arm/mach-tegra/pcie.c
arch/arm/mach-u300/Kconfig
arch/arm/mach-u300/Makefile
arch/arm/mach-u300/core.c
arch/arm/mach-u300/dma_channels.h [moved from arch/arm/mach-u300/include/mach/dma_channels.h with 88% similarity]
arch/arm/mach-u300/i2c.c
arch/arm/mach-u300/include/mach/clkdev.h [deleted file]
arch/arm/mach-u300/include/mach/irqs.h
arch/arm/mach-u300/include/mach/platform.h [deleted file]
arch/arm/mach-u300/include/mach/syscon.h
arch/arm/mach-u300/include/mach/u300-regs.h
arch/arm/mach-u300/spi.c
arch/arm/mach-u300/timer.c
arch/arm/mach-u300/timer.h [new file with mode: 0644]
arch/arm/mach-u300/u300-gpio.h
arch/arm/mach-u300/u300.c [deleted file]
arch/arm/mach-ux500/cpu-db8500.c
arch/arm/mach-versatile/core.c
arch/arm/mach-versatile/include/mach/hardware.h
arch/arm/mach-versatile/include/mach/io.h [deleted file]
arch/arm/mach-versatile/pci.c
arch/arm/mach-vexpress/ct-ca9x4.c
arch/arm/mm/ioremap.c
arch/arm/mm/mmu.c
arch/arm/plat-iop/pci.c
arch/arm/plat-iop/pmu.c
arch/arm/plat-iop/setup.c
arch/arm/plat-mxc/Makefile
arch/arm/plat-mxc/clock.c [deleted file]
arch/arm/plat-mxc/cpufreq.c
arch/arm/plat-mxc/devices/platform-imx-uart.c
arch/arm/plat-mxc/include/mach/clock.h [deleted file]
arch/arm/plat-mxc/include/mach/mx2_cam.h
arch/arm/plat-mxc/include/mach/mx31.h
arch/arm/plat-mxc/system.c
arch/arm/plat-omap/Kconfig
arch/arm/plat-omap/Makefile
arch/arm/plat-omap/common.c
arch/arm/plat-omap/counter_32k.c
arch/arm/plat-omap/debug-devices.c
arch/arm/plat-omap/debug-leds.c
arch/arm/plat-omap/devices.c [deleted file]
arch/arm/plat-omap/dma.c
arch/arm/plat-omap/fb.c
arch/arm/plat-omap/i2c.c
arch/arm/plat-omap/include/plat/board.h [deleted file]
arch/arm/plat-omap/include/plat/cpu.h
arch/arm/plat-omap/include/plat/dma.h
arch/arm/plat-omap/include/plat/gpio-switch.h [deleted file]
arch/arm/plat-omap/include/plat/gpmc.h
arch/arm/plat-omap/include/plat/hardware.h [deleted file]
arch/arm/plat-omap/include/plat/irqs-44xx.h [deleted file]
arch/arm/plat-omap/include/plat/irqs.h [deleted file]
arch/arm/plat-omap/include/plat/mmc.h
arch/arm/plat-omap/include/plat/omap-serial.h
arch/arm/plat-omap/include/plat/param.h [deleted file]
arch/arm/plat-omap/include/plat/usb.h
arch/arm/plat-omap/mux.c [deleted file]
arch/arm/plat-omap/omap-pm-noop.c
arch/arm/plat-omap/omap_device.c
arch/arm/plat-omap/sram.c
arch/arm/plat-samsung/devs.c
arch/arm/plat-samsung/include/plat/gpio-fns.h
arch/arm/plat-samsung/s5p-irq-gpioint.c
arch/arm/tools/mach-types
drivers/dma/omap-dma.c
drivers/gpio/gpio-omap.c
drivers/gpio/gpio-samsung.c
drivers/gpio/gpio-tegra.c
drivers/gpio/gpio-twl4030.c
drivers/i2c/busses/Kconfig
drivers/i2c/busses/i2c-iop3xx.c
drivers/input/keyboard/Kconfig
drivers/input/keyboard/omap-keypad.c
drivers/input/mouse/rpcmouse.c
drivers/input/serio/ams_delta_serio.c
drivers/media/video/omap/omap_vout.c
drivers/media/video/omap3isp/isp.c
drivers/mfd/twl-core.c
drivers/mmc/host/omap.c
drivers/mmc/host/omap_hsmmc.c
drivers/mmc/host/sdhci-tegra.c
drivers/mtd/nand/ams-delta.c
drivers/mtd/nand/bcm_umi_nand.c
drivers/mtd/nand/nand_bcm_umi.h
drivers/mtd/nand/omap2.c
drivers/mtd/onenand/omap2.c
drivers/net/ethernet/seeq/ether3.c
drivers/pcmcia/omap_cf.c
drivers/pinctrl/pinctrl-coh901.c
drivers/power/avs/smartreflex.c
drivers/remoteproc/omap_remoteproc.c
drivers/scsi/arm/eesox.c
drivers/spi/Kconfig
drivers/spi/spi-omap-uwire.c
drivers/spi/spi-omap2-mcspi.c
drivers/spi/spi-tegra.c
drivers/staging/tidspbridge/core/dsp-clock.c
drivers/staging/tidspbridge/core/tiomap3430.c
drivers/staging/tidspbridge/core/tiomap3430_pwr.c
drivers/staging/tidspbridge/core/tiomap_io.c
drivers/staging/tidspbridge/core/wdt.c
drivers/staging/tidspbridge/rmgr/drv_interface.c
drivers/tty/serial/serial_ks8695.c
drivers/usb/Kconfig
drivers/usb/host/Kconfig
drivers/usb/host/ohci-hcd.c
drivers/usb/host/ohci-nxp.c
drivers/usb/host/ohci-omap.c
drivers/usb/musb/tusb6010_omap.c
drivers/usb/otg/isp1301_omap.c
drivers/video/backlight/omap1_bl.c
drivers/video/da8xx-fb.c
drivers/video/omap/lcd_ams_delta.c
drivers/video/omap/lcd_mipid.c
drivers/video/omap/lcd_osk.c
drivers/video/omap2/dss/dispc.c
drivers/video/omap2/omapfb/omapfb-main.c
drivers/watchdog/Kconfig
drivers/watchdog/ks8695_wdt.c
drivers/watchdog/omap_wdt.c
include/linux/i2c/twl.h
include/linux/mfd/twl6040.h
include/linux/omapfb.h
include/linux/platform_data/asoc-ti-mcbsp.h [moved from arch/arm/plat-omap/include/plat/mcbsp.h with 100% similarity]
include/linux/platform_data/dsp-omap.h [moved from arch/arm/plat-omap/include/plat/dsp.h with 100% similarity]
include/linux/platform_data/gpio-omap.h [moved from arch/arm/plat-omap/include/plat/gpio.h with 94% similarity]
include/linux/platform_data/keypad-omap.h [moved from arch/arm/plat-omap/include/plat/keypad.h with 100% similarity]
include/linux/platform_data/lcd-mipid.h [moved from arch/arm/plat-omap/include/plat/lcd_mipid.h with 100% similarity]
include/linux/platform_data/mtd-nand-omap2.h [moved from arch/arm/plat-omap/include/plat/nand.h with 96% similarity]
include/linux/platform_data/mtd-onenand-omap2.h [moved from arch/arm/plat-omap/include/plat/onenand.h with 100% similarity]
include/linux/platform_data/omap1_bl.h [new file with mode: 0644]
include/linux/platform_data/pinctrl-coh901.h [moved from arch/arm/mach-u300/include/mach/gpio-u300.h with 72% similarity]
include/linux/platform_data/remoteproc-omap.h [moved from arch/arm/plat-omap/include/plat/remoteproc.h with 100% similarity]
include/linux/platform_data/spi-omap2-mcspi.h [moved from arch/arm/plat-omap/include/plat/mcspi.h with 100% similarity]
include/linux/platform_data/voltage-omap.h [moved from arch/arm/plat-omap/include/plat/voltage.h with 100% similarity]
include/linux/power/smartreflex.h
sound/soc/omap/am3517evm.c
sound/soc/omap/ams-delta.c
sound/soc/omap/igep0020.c
sound/soc/omap/mcbsp.c
sound/soc/omap/n810.c
sound/soc/omap/omap-abe-twl6040.c
sound/soc/omap/omap-mcbsp.c
sound/soc/omap/omap-mcpdm.c
sound/soc/omap/omap-pcm.c
sound/soc/omap/omap3beagle.c
sound/soc/omap/omap3evm.c
sound/soc/omap/omap3pandora.c
sound/soc/omap/osk5912.c
sound/soc/omap/overo.c
sound/soc/omap/rx51.c
sound/soc/omap/sdp3430.c
sound/soc/omap/zoom2.c
sound/soc/tegra/Kconfig
sound/soc/tegra/tegra_pcm.c
sound/soc/tegra/tegra_pcm.h

index 816d607..8b46c79 100644 (file)
@@ -1,4 +1,4 @@
-                       S3C2410 GPIO Control
+                       S3C24XX GPIO Control
                        ====================
 
 Introduction
@@ -12,7 +12,7 @@ Introduction
   of the s3c2410 GPIO system, please read the Samsung provided
   data-sheet/users manual to find out the complete list.
 
-  See Documentation/arm/Samsung/GPIO.txt for the core implemetation.
+  See Documentation/arm/Samsung/GPIO.txt for the core implementation.
 
 
 GPIOLIB
@@ -41,8 +41,8 @@ GPIOLIB
 GPIOLIB conversion
 ------------------
 
-If you need to convert your board or driver to use gpiolib from the exiting
-s3c2410 api, then here are some notes on the process.
+If you need to convert your board or driver to use gpiolib from the phased
+out s3c2410 API, then here are some notes on the process.
 
 1) If your board is exclusively using an GPIO, say to control peripheral
    power, then it will require to claim the gpio with gpio_request() before
@@ -55,7 +55,7 @@ s3c2410 api, then here are some notes on the process.
    as they have the same arguments, and can either take the pin specific
    values, or the more generic special-function-number arguments.
 
-3) s3c2410_gpio_pullup() changs have the problem that whilst the 
+3) s3c2410_gpio_pullup() changes have the problem that whilst the
    s3c2410_gpio_pullup(x, 1) can be easily translated to the
    s3c_gpio_setpull(x, S3C_GPIO_PULL_NONE), the s3c2410_gpio_pullup(x, 0)
    are not so easy.
@@ -74,7 +74,7 @@ s3c2410 api, then here are some notes on the process.
    when using gpio_get_value() on an output pin (s3c2410_gpio_getpin
    would return the value the pin is supposed to be outputting).
 
-6) s3c2410_gpio_getirq() should be directly replacable with the
+6) s3c2410_gpio_getirq() should be directly replaceable with the
    gpio_to_irq() call.
 
 The s3c2410_gpio and gpio_ calls have always operated on the same gpio
@@ -105,7 +105,7 @@ PIN Numbers
 -----------
 
   Each pin has an unique number associated with it in regs-gpio.h,
-  eg S3C2410_GPA(0) or S3C2410_GPF(1). These defines are used to tell
+  e.g. S3C2410_GPA(0) or S3C2410_GPF(1). These defines are used to tell
   the GPIO functions which pin is to be used.
 
   With the conversion to gpiolib, there is no longer a direct conversion
@@ -120,31 +120,27 @@ Configuring a pin
   The following function allows the configuration of a given pin to
   be changed.
 
-    void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
+    void s3c_gpio_cfgpin(unsigned int pin, unsigned int function);
 
-  Eg:
+  e.g.:
 
-     s3c2410_gpio_cfgpin(S3C2410_GPA(0), S3C2410_GPA0_ADDR0);
-     s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1);
+     s3c_gpio_cfgpin(S3C2410_GPA(0), S3C_GPIO_SFN(1));
+     s3c_gpio_cfgpin(S3C2410_GPE(8), S3C_GPIO_SFN(2));
 
    which would turn GPA(0) into the lowest Address line A0, and set
    GPE(8) to be connected to the SDIO/MMC controller's SDDAT1 line.
 
-   The s3c_gpio_cfgpin() call is a functional replacement for this call.
-
 
 Reading the current configuration
 ---------------------------------
 
-  The current configuration of a pin can be read by using:
+  The current configuration of a pin can be read by using standard
+  gpiolib function:
 
-  s3c2410_gpio_getcfg(unsigned int pin);
+  s3c_gpio_getcfg(unsigned int pin);
 
   The return value will be from the same set of values which can be
-  passed to s3c2410_gpio_cfgpin().
-
-  The s3c_gpio_getcfg() call should be a functional replacement for
-  this call.
+  passed to s3c_gpio_cfgpin().
 
 
 Configuring a pull-up resistor
@@ -154,61 +150,33 @@ Configuring a pull-up resistor
   pull-up resistors enabled. This can be configured by the following
   function:
 
-    void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
-
-  Where the to value is zero to set the pull-up off, and 1 to enable
-  the specified pull-up. Any other values are currently undefined.
-
-  The s3c_gpio_setpull() offers similar functionality, but with the
-  ability to encode whether the pull is up or down. Currently there
-  is no 'just on' state, so up or down must be selected.
-
-
-Getting the state of a PIN
---------------------------
-
-  The state of a pin can be read by using the function:
-
-    unsigned int s3c2410_gpio_getpin(unsigned int pin);
+    void s3c_gpio_setpull(unsigned int pin, unsigned int to);
 
-  This will return either zero or non-zero. Do not count on this
-  function returning 1 if the pin is set.
+  Where the to value is S3C_GPIO_PULL_NONE to set the pull-up off,
+  and S3C_GPIO_PULL_UP to enable the specified pull-up. Any other
+  values are currently undefined.
 
-  This call is now implemented by the relevant gpiolib calls, convert
-  your board or driver to use gpiolib.
-
-
-Setting the state of a PIN
---------------------------
-
-  The value an pin is outputing can be modified by using the following:
 
-    void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
+Getting and setting the state of a PIN
+--------------------------------------
 
-  Which sets the given pin to the value. Use 0 to write 0, and 1 to
-  set the output to 1.
-
-  This call is now implemented by the relevant gpiolib calls, convert
+  These calls are now implemented by the relevant gpiolib calls, convert
   your board or driver to use gpiolib.
 
 
 Getting the IRQ number associated with a PIN
 --------------------------------------------
 
-  The following function can map the given pin number to an IRQ
+  A standard gpiolib function can map the given pin number to an IRQ
   number to pass to the IRQ system.
 
-   int s3c2410_gpio_getirq(unsigned int pin);
+   int gpio_to_irq(unsigned int pin);
 
   Note, not all pins have an IRQ.
 
-  This call is now implemented by the relevant gpiolib calls, convert
-  your board or driver to use gpiolib.
-
 
-Authour
+Author
 -------
 
-
 Ben Dooks, 03 October 2004
 Copyright 2004 Ben Dooks, Simtec Electronics
index 513f256..795adfd 100644 (file)
@@ -5,14 +5,14 @@ Introduction
 ------------
 
 This outlines the Samsung GPIO implementation and the architecture
-specific calls provided alongisde the drivers/gpio core.
+specific calls provided alongside the drivers/gpio core.
 
 
 S3C24XX (Legacy)
 ----------------
 
 See Documentation/arm/Samsung-S3C24XX/GPIO.txt for more information
-about these devices. Their implementation is being brought into line
+about these devices. Their implementation has been brought into line
 with the core samsung implementation described in this document.
 
 
@@ -29,7 +29,7 @@ GPIO numbering is synchronised between the Samsung and gpiolib system.
 PIN configuration
 -----------------
 
-Pin configuration is specific to the Samsung architecutre, with each SoC
+Pin configuration is specific to the Samsung architecture, with each SoC
 registering the necessary information for the core gpio configuration
 implementation to configure pins as necessary.
 
@@ -38,5 +38,3 @@ driver or machine to change gpio configuration.
 
 See arch/arm/plat-samsung/include/plat/gpio-cfg.h for more information
 on these functions.
-
-
index 208a2d4..4bfb9ff 100644 (file)
@@ -51,6 +51,9 @@ ffc00000      ffefffff        DMA memory mapping region.  Memory returned
 ff000000       ffbfffff        Reserved for future expansion of DMA
                                mapping region.
 
+fee00000       feffffff        Mapping of PCI I/O space. This is a static
+                               mapping within the vmalloc space.
+
 VMALLOC_START  VMALLOC_END-1   vmalloc() / ioremap() space.
                                Memory returned by vmalloc/ioremap will
                                be dynamically placed in this region.
index 1c044eb..343781b 100644 (file)
@@ -7,8 +7,12 @@ representation in the device tree should be done as under:-
 Required properties:
 
 - compatible : should be one of
+       "arm,cortex-a15-pmu"
        "arm,cortex-a9-pmu"
        "arm,cortex-a8-pmu"
+       "arm,cortex-a7-pmu"
+       "arm,cortex-a5-pmu"
+       "arm,arm11mpcore-pmu"
        "arm,arm1176-pmu"
        "arm,arm1136-pmu"
 - interrupts : 1 combined interrupt or 1 per core.
index 0318e62..a9f1ac2 100644 (file)
@@ -595,7 +595,6 @@ M:  Will Deacon <will.deacon@arm.com>
 S:     Maintained
 F:     arch/arm/kernel/perf_event*
 F:     arch/arm/oprofile/common.c
-F:     arch/arm/kernel/pmu.c
 F:     arch/arm/include/asm/pmu.h
 F:     arch/arm/kernel/hw_breakpoint.c
 F:     arch/arm/include/asm/hw_breakpoint.h
index 4c428dc..884768c 100644 (file)
@@ -279,7 +279,6 @@ config ARCH_INTEGRATOR
        select GENERIC_CLOCKEVENTS
        select PLAT_VERSATILE
        select PLAT_VERSATILE_FPGA_IRQ
-       select NEED_MACH_IO_H
        select NEED_MACH_MEMORY_H
        select SPARSE_IRQ
        select MULTI_IRQ_HANDLER
@@ -311,7 +310,6 @@ config ARCH_VERSATILE
        select ICST
        select GENERIC_CLOCKEVENTS
        select ARCH_WANT_OPTIONAL_GPIOLIB
-       select NEED_MACH_IO_H if PCI
        select PLAT_VERSATILE
        select PLAT_VERSATILE_CLOCK
        select PLAT_VERSATILE_CLCD
@@ -406,9 +404,8 @@ config ARCH_GEMINI
        help
          Support for the Cortina Systems Gemini family SoCs
 
-config ARCH_PRIMA2
-       bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
-       select CPU_V7
+config ARCH_SIRF
+       bool "CSR SiRF"
        select NO_IOPORT
        select ARCH_REQUIRE_GPIOLIB
        select GENERIC_CLOCKEVENTS
@@ -418,9 +415,8 @@ config ARCH_PRIMA2
        select PINCTRL
        select PINCTRL_SIRF
        select USE_OF
-       select ZONE_DMA
        help
-          Support for CSR SiRFSoC ARM Cortex A9 Platform
+         Support for CSR SiRFprimaII/Marco/Polo platforms
 
 config ARCH_EBSA110
        bool "EBSA-110"
@@ -455,7 +451,7 @@ config ARCH_FOOTBRIDGE
        select FOOTBRIDGE
        select GENERIC_CLOCKEVENTS
        select HAVE_IDE
-       select NEED_MACH_IO_H
+       select NEED_MACH_IO_H if !MMU
        select NEED_MACH_MEMORY_H
        help
          Support for systems based on the DC21285 companion chip
@@ -512,7 +508,6 @@ config ARCH_IOP13XX
        select PCI
        select ARCH_SUPPORTS_MSI
        select VMSPLIT_1G
-       select NEED_MACH_IO_H
        select NEED_MACH_MEMORY_H
        select NEED_RET_TO_USER
        help
@@ -522,7 +517,6 @@ config ARCH_IOP32X
        bool "IOP32x-based"
        depends on MMU
        select CPU_XSCALE
-       select NEED_MACH_IO_H
        select NEED_RET_TO_USER
        select PLAT_IOP
        select PCI
@@ -535,7 +529,6 @@ config ARCH_IOP33X
        bool "IOP33x-based"
        depends on MMU
        select CPU_XSCALE
-       select NEED_MACH_IO_H
        select NEED_RET_TO_USER
        select PLAT_IOP
        select PCI
@@ -575,7 +568,6 @@ config ARCH_DOVE
        select PCI
        select ARCH_REQUIRE_GPIOLIB
        select GENERIC_CLOCKEVENTS
-       select NEED_MACH_IO_H
        select PLAT_ORION
        help
          Support for the Marvell Dove SoC 88AP510
@@ -586,7 +578,6 @@ config ARCH_KIRKWOOD
        select PCI
        select ARCH_REQUIRE_GPIOLIB
        select GENERIC_CLOCKEVENTS
-       select NEED_MACH_IO_H
        select PLAT_ORION
        help
          Support for the following Marvell Kirkwood series SoCs:
@@ -613,7 +604,6 @@ config ARCH_MV78XX0
        select PCI
        select ARCH_REQUIRE_GPIOLIB
        select GENERIC_CLOCKEVENTS
-       select NEED_MACH_IO_H
        select PLAT_ORION
        help
          Support for the following Marvell MV78xx0 series SoCs:
@@ -626,7 +616,6 @@ config ARCH_ORION5X
        select PCI
        select ARCH_REQUIRE_GPIOLIB
        select GENERIC_CLOCKEVENTS
-       select NEED_MACH_IO_H
        select PLAT_ORION
        help
          Support for the following Marvell Orion 5x series SoCs:
@@ -651,8 +640,9 @@ config ARCH_KS8695
        bool "Micrel/Kendin KS8695"
        select CPU_ARM922T
        select ARCH_REQUIRE_GPIOLIB
-       select ARCH_USES_GETTIMEOFFSET
        select NEED_MACH_MEMORY_H
+       select CLKSRC_MMIO
+       select GENERIC_CLOCKEVENTS
        help
          Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
          System-on-Chip devices.
@@ -682,7 +672,6 @@ config ARCH_TEGRA
        select HAVE_CLK
        select HAVE_SMP
        select MIGHT_HAVE_CACHE_L2X0
-       select NEED_MACH_IO_H if PCI
        select ARCH_HAS_CPUFREQ
        select USE_OF
        help
@@ -708,14 +697,6 @@ config ARCH_PICOXCELL
          family of Femtocell devices.  The picoxcell support requires device tree
          for all boards.
 
-config ARCH_PNX4008
-       bool "Philips Nexperia PNX4008 Mobile"
-       select CPU_ARM926T
-       select CLKDEV_LOOKUP
-       select ARCH_USES_GETTIMEOFFSET
-       help
-         This enables support for Philips PNX4008 mobile platform.
-
 config ARCH_PXA
        bool "PXA2xx/PXA3xx-based"
        depends on MMU
@@ -911,7 +892,6 @@ config ARCH_SHARK
        select PCI
        select ARCH_USES_GETTIMEOFFSET
        select NEED_MACH_MEMORY_H
-       select NEED_MACH_IO_H
        help
          Support for the StrongARM based Digital DNARD machine, also known
          as "Shark" (<http://www.shark-linux.de/shark.html>).
@@ -930,6 +910,7 @@ config ARCH_U300
        select COMMON_CLK
        select GENERIC_GPIO
        select ARCH_REQUIRE_GPIOLIB
+       select SPARSE_IRQ
        help
          Support for ST-Ericsson U300 series mobile platforms.
 
@@ -1117,6 +1098,8 @@ source "arch/arm/mach-exynos/Kconfig"
 
 source "arch/arm/mach-shmobile/Kconfig"
 
+source "arch/arm/mach-prima2/Kconfig"
+
 source "arch/arm/mach-tegra/Kconfig"
 
 source "arch/arm/mach-u300/Kconfig"
@@ -1178,12 +1161,6 @@ config XSCALE_PMU
        depends on CPU_XSCALE
        default y
 
-config CPU_HAS_PMU
-       depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
-                  (!ARCH_OMAP3 || OMAP3_EMU)
-       default y
-       bool
-
 config MULTI_IRQ_HANDLER
        bool
        help
@@ -1756,7 +1733,7 @@ config HIGHPTE
 
 config HW_PERF_EVENTS
        bool "Enable hardware performance counter support for perf events"
-       depends on PERF_EVENTS && CPU_HAS_PMU
+       depends on PERF_EVENTS
        default y
        help
          Enable hardware performance counter support for perf events. If
index a051dfb..74381a3 100644 (file)
@@ -167,7 +167,6 @@ machine-$(CONFIG_ARCH_OMAP1)                := omap1
 machine-$(CONFIG_ARCH_OMAP2PLUS)       := omap2
 machine-$(CONFIG_ARCH_ORION5X)         := orion5x
 machine-$(CONFIG_ARCH_PICOXCELL)       := picoxcell
-machine-$(CONFIG_ARCH_PNX4008)         := pnx4008
 machine-$(CONFIG_ARCH_PRIMA2)          := prima2
 machine-$(CONFIG_ARCH_PXA)             := pxa
 machine-$(CONFIG_ARCH_REALVIEW)                := realview
index 2b0ff60..2acc86c 100644 (file)
@@ -49,7 +49,7 @@
                        i2c@1001d000 {
                                clock-frequency = <400000>;
                                status = "okay";
-                               at24@4c {
+                               at24@52 {
                                        compatible = "at,24c32";
                                        pagesize = <32>;
                                        reg = <0x52>;
index f146dbf..c3ef1ad 100644 (file)
        i2c@7000d000 {
                status = "okay";
                clock-frequency = <400000>;
+
+               pmic: tps6586x@34 {
+                       compatible = "ti,tps6586x";
+                       reg = <0x34>;
+                       interrupts = <0 86 0x4>;
+
+                       ti,system-power-controller;
+
+                       #gpio-cells = <2>;
+                       gpio-controller;
+
+                       sys-supply = <&vdd_5v0_reg>;
+                       vin-sm0-supply = <&sys_reg>;
+                       vin-sm1-supply = <&sys_reg>;
+                       vin-sm2-supply = <&sys_reg>;
+                       vinldo01-supply = <&sm2_reg>;
+                       vinldo23-supply = <&sm2_reg>;
+                       vinldo4-supply = <&sm2_reg>;
+                       vinldo678-supply = <&sm2_reg>;
+                       vinldo9-supply = <&sm2_reg>;
+
+                       regulators {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               sys_reg: regulator@0 {
+                                       reg = <0>;
+                                       regulator-compatible = "sys";
+                                       regulator-name = "vdd_sys";
+                                       regulator-always-on;
+                               };
+
+                               regulator@1 {
+                                       reg = <1>;
+                                       regulator-compatible = "sm0";
+                                       regulator-name = "vdd_sm0,vdd_core";
+                                       regulator-min-microvolt = <1200000>;
+                                       regulator-max-microvolt = <1200000>;
+                                       regulator-always-on;
+                               };
+
+                               regulator@2 {
+                                       reg = <2>;
+                                       regulator-compatible = "sm1";
+                                       regulator-name = "vdd_sm1,vdd_cpu";
+                                       regulator-min-microvolt = <1000000>;
+                                       regulator-max-microvolt = <1000000>;
+                                       regulator-always-on;
+                               };
+
+                               sm2_reg: regulator@3 {
+                                       reg = <3>;
+                                       regulator-compatible = "sm2";
+                                       regulator-name = "vdd_sm2,vin_ldo*";
+                                       regulator-min-microvolt = <3700000>;
+                                       regulator-max-microvolt = <3700000>;
+                                       regulator-always-on;
+                               };
+
+                               regulator@4 {
+                                       reg = <4>;
+                                       regulator-compatible = "ldo0";
+                                       regulator-name = "vdd_ldo0,vddio_pex_clk";
+                                       regulator-min-microvolt = <3300000>;
+                                       regulator-max-microvolt = <3300000>;
+                               };
+
+                               regulator@5 {
+                                       reg = <5>;
+                                       regulator-compatible = "ldo1";
+                                       regulator-name = "vdd_ldo1,avdd_pll*";
+                                       regulator-min-microvolt = <1100000>;
+                                       regulator-max-microvolt = <1100000>;
+                                       regulator-always-on;
+                               };
+
+                               regulator@6 {
+                                       reg = <6>;
+                                       regulator-compatible = "ldo2";
+                                       regulator-name = "vdd_ldo2,vdd_rtc";
+                                       regulator-min-microvolt = <1200000>;
+                                       regulator-max-microvolt = <1200000>;
+                               };
+
+                               regulator@7 {
+                                       reg = <7>;
+                                       regulator-compatible = "ldo3";
+                                       regulator-name = "vdd_ldo3,avdd_usb*";
+                                       regulator-min-microvolt = <3300000>;
+                                       regulator-max-microvolt = <3300000>;
+                                       regulator-always-on;
+                               };
+
+                               regulator@8 {
+                                       reg = <8>;
+                                       regulator-compatible = "ldo4";
+                                       regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+                                       regulator-min-microvolt = <1800000>;
+                                       regulator-max-microvolt = <1800000>;
+                                       regulator-always-on;
+                               };
+
+                               regulator@9 {
+                                       reg = <9>;
+                                       regulator-compatible = "ldo5";
+                                       regulator-name = "vdd_ldo5,vcore_mmc";
+                                       regulator-min-microvolt = <2850000>;
+                                       regulator-max-microvolt = <2850000>;
+                                       regulator-always-on;
+                               };
+
+                               regulator@10 {
+                                       reg = <10>;
+                                       regulator-compatible = "ldo6";
+                                       regulator-name = "vdd_ldo6,avdd_vdac";
+                                       regulator-min-microvolt = <1800000>;
+                                       regulator-max-microvolt = <1800000>;
+                               };
+
+                               regulator@11 {
+                                       reg = <11>;
+                                       regulator-compatible = "ldo7";
+                                       regulator-name = "vdd_ldo7,avdd_hdmi";
+                                       regulator-min-microvolt = <3300000>;
+                                       regulator-max-microvolt = <3300000>;
+                               };
+
+                               regulator@12 {
+                                       reg = <12>;
+                                       regulator-compatible = "ldo8";
+                                       regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+                                       regulator-min-microvolt = <1800000>;
+                                       regulator-max-microvolt = <1800000>;
+                               };
+
+                               regulator@13 {
+                                       reg = <13>;
+                                       regulator-compatible = "ldo9";
+                                       regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+                                       regulator-min-microvolt = <2850000>;
+                                       regulator-max-microvolt = <2850000>;
+                                       regulator-always-on;
+                               };
+
+                               regulator@14 {
+                                       reg = <14>;
+                                       regulator-compatible = "ldo_rtc";
+                                       regulator-name = "vdd_rtc_out,vdd_cell";
+                                       regulator-min-microvolt = <3300000>;
+                                       regulator-max-microvolt = <3300000>;
+                                       regulator-always-on;
+                               };
+                       };
+               };
        };
 
        pmc {
                bus-width = <8>;
        };
 
+       regulators {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               vdd_5v0_reg: regulator@0 {
+                       compatible = "regulator-fixed";
+                       reg = <0>;
+                       regulator-name = "vdd_5v0";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+                       regulator-always-on;
+               };
+
+               regulator@1 {
+                       compatible = "regulator-fixed";
+                       reg = <1>;
+                       regulator-name = "vdd_1v5";
+                       regulator-min-microvolt = <1500000>;
+                       regulator-max-microvolt = <1500000>;
+                       gpio = <&pmic 0 0>;
+               };
+
+               regulator@2 {
+                       compatible = "regulator-fixed";
+                       reg = <2>;
+                       regulator-name = "vdd_1v2";
+                       regulator-min-microvolt = <1200000>;
+                       regulator-max-microvolt = <1200000>;
+                       gpio = <&pmic 1 0>;
+                       enable-active-high;
+               };
+
+               regulator@3 {
+                       compatible = "regulator-fixed";
+                       reg = <3>;
+                       regulator-name = "vdd_1v05";
+                       regulator-min-microvolt = <1050000>;
+                       regulator-max-microvolt = <1050000>;
+                       gpio = <&pmic 2 0>;
+                       enable-active-high;
+                       /* Hack until board-harmony-pcie.c is removed */
+                       status = "disabled";
+               };
+
+               regulator@4 {
+                       compatible = "regulator-fixed";
+                       reg = <4>;
+                       regulator-name = "vdd_pnl";
+                       regulator-min-microvolt = <2800000>;
+                       regulator-max-microvolt = <2800000>;
+                       gpio = <&gpio 22 0>; /* gpio PC6 */
+                       enable-active-high;
+               };
+
+               regulator@5 {
+                       compatible = "regulator-fixed";
+                       reg = <5>;
+                       regulator-name = "vdd_bl";
+                       regulator-min-microvolt = <2800000>;
+                       regulator-max-microvolt = <2800000>;
+                       gpio = <&gpio 176 0>; /* gpio PW0 */
+                       enable-active-high;
+               };
+       };
+
        sound {
                compatible = "nvidia,tegra-audio-wm8903-harmony",
                             "nvidia,tegra-audio-wm8903";
diff --git a/arch/arm/configs/pnx4008_defconfig b/arch/arm/configs/pnx4008_defconfig
deleted file mode 100644 (file)
index 35a31cc..0000000
+++ /dev/null
@@ -1,472 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_AUDIT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_ARCH_PNX4008=y
-CONFIG_PREEMPT=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=64M console=ttyS0,115200"
-CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_AOUT=m
-CONFIG_BINFMT_MISC=m
-CONFIG_PM=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_ROUTE_MULTIPATH=y
-CONFIG_IP_ROUTE_VERBOSE=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_MROUTE=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-CONFIG_SYN_COOKIES=y
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_IPCOMP=m
-CONFIG_IPV6_PRIVACY=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_TUNNEL=m
-CONFIG_NETFILTER=y
-CONFIG_IP_VS=m
-CONFIG_IP_VS_PROTO_TCP=y
-CONFIG_IP_VS_PROTO_UDP=y
-CONFIG_IP_VS_PROTO_ESP=y
-CONFIG_IP_VS_PROTO_AH=y
-CONFIG_IP_VS_RR=m
-CONFIG_IP_VS_WRR=m
-CONFIG_IP_VS_LC=m
-CONFIG_IP_VS_WLC=m
-CONFIG_IP_VS_LBLC=m
-CONFIG_IP_VS_LBLCR=m
-CONFIG_IP_VS_DH=m
-CONFIG_IP_VS_SH=m
-CONFIG_IP_VS_SED=m
-CONFIG_IP_VS_NQ=m
-CONFIG_IP_VS_FTP=m
-CONFIG_IP_NF_QUEUE=m
-CONFIG_IP6_NF_QUEUE=m
-CONFIG_DECNET_NF_GRABULATOR=m
-CONFIG_BRIDGE_NF_EBTABLES=m
-CONFIG_BRIDGE_EBT_BROUTE=m
-CONFIG_BRIDGE_EBT_T_FILTER=m
-CONFIG_BRIDGE_EBT_T_NAT=m
-CONFIG_BRIDGE_EBT_802_3=m
-CONFIG_BRIDGE_EBT_AMONG=m
-CONFIG_BRIDGE_EBT_ARP=m
-CONFIG_BRIDGE_EBT_IP=m
-CONFIG_BRIDGE_EBT_LIMIT=m
-CONFIG_BRIDGE_EBT_MARK=m
-CONFIG_BRIDGE_EBT_PKTTYPE=m
-CONFIG_BRIDGE_EBT_STP=m
-CONFIG_BRIDGE_EBT_VLAN=m
-CONFIG_BRIDGE_EBT_ARPREPLY=m
-CONFIG_BRIDGE_EBT_DNAT=m
-CONFIG_BRIDGE_EBT_MARK_T=m
-CONFIG_BRIDGE_EBT_REDIRECT=m
-CONFIG_BRIDGE_EBT_SNAT=m
-CONFIG_BRIDGE_EBT_LOG=m
-CONFIG_IP_SCTP=m
-CONFIG_ATM=y
-CONFIG_ATM_CLIP=y
-CONFIG_ATM_LANE=m
-CONFIG_ATM_MPOA=m
-CONFIG_ATM_BR2684=m
-CONFIG_BRIDGE=m
-CONFIG_VLAN_8021Q=m
-CONFIG_DECNET=m
-CONFIG_LLC2=m
-CONFIG_IPX=m
-CONFIG_ATALK=m
-CONFIG_DEV_APPLETALK=m
-CONFIG_IPDDP=m
-CONFIG_IPDDP_ENCAP=y
-CONFIG_IPDDP_DECAP=y
-CONFIG_X25=m
-CONFIG_LAPB=m
-CONFIG_ECONET=m
-CONFIG_ECONET_AUNUDP=y
-CONFIG_ECONET_NATIVE=y
-CONFIG_WAN_ROUTER=m
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_CBQ=m
-CONFIG_NET_SCH_HTB=m
-CONFIG_NET_SCH_HFSC=m
-CONFIG_NET_SCH_ATM=m
-CONFIG_NET_SCH_PRIO=m
-CONFIG_NET_SCH_RED=m
-CONFIG_NET_SCH_SFQ=m
-CONFIG_NET_SCH_TEQL=m
-CONFIG_NET_SCH_TBF=m
-CONFIG_NET_SCH_GRED=m
-CONFIG_NET_SCH_DSMARK=m
-CONFIG_NET_SCH_NETEM=m
-CONFIG_NET_CLS_TCINDEX=m
-CONFIG_NET_CLS_ROUTE4=m
-CONFIG_NET_CLS_FW=m
-CONFIG_NET_CLS_U32=m
-CONFIG_NET_CLS_RSVP=m
-CONFIG_NET_CLS_RSVP6=m
-CONFIG_NET_PKTGEN=m
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_SLRAM=m
-CONFIG_MTD_PHRAM=m
-CONFIG_MTD_MTDRAM=m
-CONFIG_MTD_DOC2000=m
-CONFIG_MTD_DOC2001=m
-CONFIG_MTD_DOC2001PLUS=m
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_NANDSIM=m
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_EEPROM_LEGACY=m
-CONFIG_SCSI=m
-CONFIG_BLK_DEV_SD=m
-CONFIG_CHR_DEV_ST=m
-CONFIG_CHR_DEV_OSST=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_CHR_DEV_SCH=m
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_SPI_ATTRS=m
-CONFIG_SCSI_FC_ATTRS=m
-CONFIG_SCSI_DEBUG=m
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-CONFIG_BONDING=m
-CONFIG_EQUALIZER=m
-CONFIG_TUN=m
-CONFIG_NET_ETHERNET=y
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-CONFIG_USB_USBNET=m
-# CONFIG_USB_NET_CDC_SUBSET is not set
-CONFIG_WAN=y
-CONFIG_HDLC=m
-CONFIG_HDLC_RAW=m
-CONFIG_HDLC_RAW_ETH=m
-CONFIG_HDLC_CISCO=m
-CONFIG_HDLC_FR=m
-CONFIG_HDLC_PPP=m
-CONFIG_HDLC_X25=m
-CONFIG_DLCI=m
-CONFIG_WAN_ROUTER_DRIVERS=m
-CONFIG_LAPBETHER=m
-CONFIG_X25_ASY=m
-CONFIG_ATM_TCP=m
-CONFIG_PPP=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPP_MPPE=m
-CONFIG_PPPOE=m
-CONFIG_PPPOATM=m
-CONFIG_SLIP=m
-CONFIG_SLIP_COMPRESSED=y
-CONFIG_SLIP_SMART=y
-CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_NETCONSOLE=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_JOYDEV=m
-CONFIG_INPUT_EVDEV=m
-CONFIG_INPUT_EVBUG=m
-CONFIG_KEYBOARD_LKKBD=m
-CONFIG_KEYBOARD_NEWTON=m
-CONFIG_KEYBOARD_SUNKBD=m
-CONFIG_KEYBOARD_XTKBD=m
-CONFIG_MOUSE_PS2=m
-CONFIG_MOUSE_SERIAL=m
-CONFIG_MOUSE_VSXXXAA=m
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_ANALOG=m
-CONFIG_JOYSTICK_A3D=m
-CONFIG_JOYSTICK_ADI=m
-CONFIG_JOYSTICK_COBRA=m
-CONFIG_JOYSTICK_GF2K=m
-CONFIG_JOYSTICK_GRIP=m
-CONFIG_JOYSTICK_GRIP_MP=m
-CONFIG_JOYSTICK_GUILLEMOT=m
-CONFIG_JOYSTICK_INTERACT=m
-CONFIG_JOYSTICK_SIDEWINDER=m
-CONFIG_JOYSTICK_TMDC=m
-CONFIG_JOYSTICK_IFORCE=m
-CONFIG_JOYSTICK_IFORCE_USB=y
-CONFIG_JOYSTICK_IFORCE_232=y
-CONFIG_JOYSTICK_WARRIOR=m
-CONFIG_JOYSTICK_MAGELLAN=m
-CONFIG_JOYSTICK_SPACEORB=m
-CONFIG_JOYSTICK_SPACEBALL=m
-CONFIG_JOYSTICK_STINGER=m
-CONFIG_JOYSTICK_JOYDUMP=m
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GUNZE=m
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=m
-CONFIG_SERIO_SERPORT=m
-CONFIG_SERIO_RAW=m
-CONFIG_GAMEPORT_NS558=m
-CONFIG_GAMEPORT_L4=m
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_SOFT_WATCHDOG=m
-CONFIG_USBPCWATCHDOG=m
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_SEQUENCER=m
-CONFIG_SND_SEQ_DUMMY=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_SEQUENCER_OSS=y
-CONFIG_SND_DUMMY=m
-CONFIG_SND_VIRMIDI=m
-CONFIG_SND_MTPAV=m
-CONFIG_SND_SERIAL_U16550=m
-CONFIG_SND_MPU401=m
-CONFIG_SND_USB_AUDIO=m
-CONFIG_SOUND_PRIME=m
-CONFIG_USB_HID=m
-CONFIG_USB_HIDDEV=y
-CONFIG_USB_KBD=m
-CONFIG_USB_MOUSE=m
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_MON=y
-CONFIG_USB_SL811_HCD=m
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-CONFIG_USB_STORAGE=m
-CONFIG_USB_STORAGE_DATAFAB=m
-CONFIG_USB_STORAGE_FREECOM=m
-CONFIG_USB_STORAGE_USBAT=m
-CONFIG_USB_STORAGE_SDDR09=m
-CONFIG_USB_STORAGE_SDDR55=m
-CONFIG_USB_STORAGE_JUMPSHOT=m
-CONFIG_USB_MDC800=m
-CONFIG_USB_MICROTEK=m
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_BELKIN=m
-CONFIG_USB_SERIAL_WHITEHEAT=m
-CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-CONFIG_USB_SERIAL_CYPRESS_M8=m
-CONFIG_USB_SERIAL_EMPEG=m
-CONFIG_USB_SERIAL_FTDI_SIO=m
-CONFIG_USB_SERIAL_VISOR=m
-CONFIG_USB_SERIAL_IPAQ=m
-CONFIG_USB_SERIAL_IR=m
-CONFIG_USB_SERIAL_EDGEPORT=m
-CONFIG_USB_SERIAL_EDGEPORT_TI=m
-CONFIG_USB_SERIAL_IPW=m
-CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-CONFIG_USB_SERIAL_KEYSPAN=m
-CONFIG_USB_SERIAL_KLSI=m
-CONFIG_USB_SERIAL_KOBIL_SCT=m
-CONFIG_USB_SERIAL_MCT_U232=m
-CONFIG_USB_SERIAL_PL2303=m
-CONFIG_USB_SERIAL_SAFE=m
-CONFIG_USB_SERIAL_CYBERJACK=m
-CONFIG_USB_SERIAL_XIRCOM=m
-CONFIG_USB_SERIAL_OMNINET=m
-CONFIG_USB_RIO500=m
-CONFIG_USB_LEGOTOWER=m
-CONFIG_USB_LCD=m
-CONFIG_USB_LED=m
-CONFIG_USB_CYTHERM=m
-CONFIG_USB_TEST=m
-CONFIG_USB_ATM=m
-CONFIG_USB_SPEEDTOUCH=m
-CONFIG_USB_GADGET=m
-CONFIG_USB_GADGET_DUMMY_HCD=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_MMC=m
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT3_FS=m
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_REISERFS_FS=m
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
-CONFIG_JFS_FS=m
-CONFIG_JFS_POSIX_ACL=y
-CONFIG_JFS_STATISTICS=y
-CONFIG_XFS_FS=m
-CONFIG_XFS_QUOTA=y
-CONFIG_XFS_POSIX_ACL=y
-CONFIG_XFS_RT=y
-CONFIG_INOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QFMT_V1=m
-CONFIG_QFMT_V2=m
-CONFIG_AUTOFS_FS=m
-CONFIG_AUTOFS4_FS=m
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_NTFS_FS=m
-CONFIG_TMPFS=y
-CONFIG_ADFS_FS=m
-CONFIG_AFFS_FS=m
-CONFIG_HFS_FS=m
-CONFIG_HFSPLUS_FS=m
-CONFIG_BEFS_FS=m
-CONFIG_BFS_FS=m
-CONFIG_EFS_FS=m
-CONFIG_JFFS2_FS=m
-CONFIG_CRAMFS=y
-CONFIG_VXFS_FS=m
-CONFIG_MINIX_FS=m
-CONFIG_HPFS_FS=m
-CONFIG_QNX4FS_FS=m
-CONFIG_ROMFS_FS=m
-CONFIG_SYSV_FS=m
-CONFIG_UFS_FS=m
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V4=y
-CONFIG_RPCSEC_GSS_SPKM3=m
-CONFIG_SMB_FS=m
-CONFIG_CIFS=m
-CONFIG_NCP_FS=m
-CONFIG_NCPFS_PACKET_SIGNING=y
-CONFIG_NCPFS_IOCTL_LOCKING=y
-CONFIG_NCPFS_STRONG=y
-CONFIG_NCPFS_NFS_NS=y
-CONFIG_NCPFS_OS2_NS=y
-CONFIG_NCPFS_NLS=y
-CONFIG_NCPFS_EXTRAS=y
-CONFIG_CODA_FS=m
-CONFIG_AFS_FS=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_ACORN_PARTITION=y
-CONFIG_ACORN_PARTITION_ICS=y
-CONFIG_ACORN_PARTITION_RISCIX=y
-CONFIG_OSF_PARTITION=y
-CONFIG_AMIGA_PARTITION=y
-CONFIG_ATARI_PARTITION=y
-CONFIG_MAC_PARTITION=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_MINIX_SUBPARTITION=y
-CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_UNIXWARE_DISKLABEL=y
-CONFIG_LDM_PARTITION=y
-CONFIG_SGI_PARTITION=y
-CONFIG_ULTRIX_PARTITION=y
-CONFIG_SUN_PARTITION=y
-CONFIG_NLS_DEFAULT="cp437"
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_SECURITY=y
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRC16=m
index c328ac6..807d4e2 100644 (file)
@@ -1,4 +1,6 @@
 CONFIG_EXPERIMENTAL=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_RELAY=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_KALLSYMS_ALL=y
@@ -8,9 +10,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_BSD_DISKLABEL=y
 CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_ARCH_PRIMA2=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
+CONFIG_ARCH_SIRF=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_KEXEC=y
@@ -36,7 +36,6 @@ CONFIG_SPI=y
 CONFIG_SPI_SIRF=y
 CONFIG_SPI_SPIDEV=y
 # CONFIG_HWMON is not set
-# CONFIG_HID_SUPPORT is not set
 CONFIG_USB_GADGET=y
 CONFIG_USB_FILE_STORAGE=m
 CONFIG_USB_MASS_STORAGE=m
index db22453..0d6bb73 100644 (file)
@@ -145,6 +145,8 @@ CONFIG_MMC_SDHCI_TEGRA=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_EM3027=y
 CONFIG_RTC_DRV_TEGRA=y
+CONFIG_DMADEVICES=y
+CONFIG_TEGRA20_APB_DMA=y
 CONFIG_STAGING=y
 CONFIG_SENSORS_ISL29018=y
 CONFIG_SENSORS_ISL29028=y
index 2ff2c75..02fe2fb 100644 (file)
@@ -217,18 +217,8 @@ extern int iop3xx_get_init_atu(void);
 #define IOP3XX_PCI_LOWER_MEM_PA        0x80000000
 #define IOP3XX_PCI_MEM_WINDOW_SIZE     0x08000000
 
-#define IOP3XX_PCI_IO_WINDOW_SIZE      0x00010000
 #define IOP3XX_PCI_LOWER_IO_PA         0x90000000
-#define IOP3XX_PCI_LOWER_IO_VA         0xfe000000
-#define IOP3XX_PCI_LOWER_IO_BA         0x90000000
-#define IOP3XX_PCI_UPPER_IO_PA         (IOP3XX_PCI_LOWER_IO_PA +\
-                                       IOP3XX_PCI_IO_WINDOW_SIZE - 1)
-#define IOP3XX_PCI_UPPER_IO_VA         (IOP3XX_PCI_LOWER_IO_VA +\
-                                       IOP3XX_PCI_IO_WINDOW_SIZE - 1)
-#define IOP3XX_PCI_IO_PHYS_TO_VIRT(addr) (((u32) (addr) -\
-                                       IOP3XX_PCI_LOWER_IO_PA) +\
-                                       IOP3XX_PCI_LOWER_IO_VA)
-
+#define IOP3XX_PCI_LOWER_IO_BA         0x00000000
 
 #ifndef __ASSEMBLY__
 
index 815c669..8f4db67 100644 (file)
@@ -113,11 +113,19 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
 #define __iowmb()              do { } while (0)
 #endif
 
+/* PCI fixed i/o mapping */
+#define PCI_IO_VIRT_BASE       0xfee00000
+
+extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr);
+
 /*
  * Now, pick up the machine-defined IO definitions
  */
 #ifdef CONFIG_NEED_MACH_IO_H
 #include <mach/io.h>
+#elif defined(CONFIG_PCI)
+#define IO_SPACE_LIMIT ((resource_size_t)0xfffff)
+#define __io(a)                __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT))
 #else
 #define __io(a)                __typesafe_io((a) & IO_SPACE_LIMIT)
 #endif
index a6efcdd..195ac2f 100644 (file)
@@ -9,6 +9,9 @@
  *
  *  Page table mapping constructs and function prototypes
  */
+#ifndef __ASM_MACH_MAP_H
+#define __ASM_MACH_MAP_H
+
 #include <asm/io.h>
 
 struct map_desc {
@@ -34,6 +37,8 @@ struct map_desc {
 
 #ifdef CONFIG_MMU
 extern void iotable_init(struct map_desc *, int);
+extern void vm_reserve_area_early(unsigned long addr, unsigned long size,
+                                 void *caller);
 
 struct mem_type;
 extern const struct mem_type *get_mem_type(unsigned int type);
@@ -44,4 +49,7 @@ extern int ioremap_page(unsigned long virt, unsigned long phys,
                        const struct mem_type *mtype);
 #else
 #define iotable_init(map,num)  do { } while (0)
+#define vm_reserve_area_early(a,s,c)   do { } while (0)
+#endif
+
 #endif
index 26c511f..db9fedb 100644 (file)
@@ -11,6 +11,8 @@
 #ifndef __ASM_MACH_PCI_H
 #define __ASM_MACH_PCI_H
 
+#include <linux/ioport.h>
+
 struct pci_sys_data;
 struct pci_ops;
 struct pci_bus;
@@ -42,6 +44,8 @@ struct pci_sys_data {
        unsigned long   io_offset;      /* bus->cpu IO mapping offset           */
        struct pci_bus  *bus;           /* PCI bus                              */
        struct list_head resources;     /* root bus resources (apertures)       */
+       struct resource io_res;
+       char            io_res_name[12];
                                        /* Bridge swizzling                     */
        u8              (*swizzle)(struct pci_dev *, u8 *);
                                        /* IRQ mapping                          */
@@ -55,6 +59,15 @@ struct pci_sys_data {
 void pci_common_init(struct hw_pci *);
 
 /*
+ * Setup early fixed I/O mapping.
+ */
+#if defined(CONFIG_PCI)
+extern void pci_map_io_early(unsigned long pfn);
+#else
+static inline void pci_map_io_early(unsigned long pfn) {}
+#endif
+
+/*
  * PCI controllers
  */
 extern struct pci_ops iop3xx_ops;
index e074948..625cd62 100644 (file)
 #ifndef __ARM_PERF_EVENT_H__
 #define __ARM_PERF_EVENT_H__
 
-/* Nothing to see here... */
+/*
+ * The ARMv7 CPU PMU supports up to 32 event counters.
+ */
+#define ARMPMU_MAX_HWEVENTS            32
+
+#define HW_OP_UNSUPPORTED              0xFFFF
+#define C(_x)                          PERF_COUNT_HW_CACHE_##_x
+#define CACHE_OP_UNSUPPORTED           0xFFFF
 
 #endif /* __ARM_PERF_EVENT_H__ */
index 4432305..a26170d 100644 (file)
 #include <linux/perf_event.h>
 
 /*
- * Types of PMUs that can be accessed directly and require mutual
- * exclusion between profiling tools.
- */
-enum arm_pmu_type {
-       ARM_PMU_DEVICE_CPU      = 0,
-       ARM_NUM_PMU_DEVICES,
-};
-
-/*
  * struct arm_pmu_platdata - ARM PMU platform data
  *
  * @handle_irq: an optional handler which will be called from the
  *     interrupt and passed the address of the low level handler,
  *     and can be used to implement any platform specific handling
  *     before or after calling it.
- * @enable_irq: an optional handler which will be called after
- *     request_irq and be used to handle some platform specific
- *     irq enablement
- * @disable_irq: an optional handler which will be called before
- *     free_irq and be used to handle some platform specific
- *     irq disablement
+ * @runtime_resume: an optional handler which will be called by the
+ *     runtime PM framework following a call to pm_runtime_get().
+ *     Note that if pm_runtime_get() is called more than once in
+ *     succession this handler will only be called once.
+ * @runtime_suspend: an optional handler which will be called by the
+ *     runtime PM framework following a call to pm_runtime_put().
+ *     Note that if pm_runtime_get() is called more than once in
+ *     succession this handler will only be called following the
+ *     final call to pm_runtime_put() that actually disables the
+ *     hardware.
  */
 struct arm_pmu_platdata {
        irqreturn_t (*handle_irq)(int irq, void *dev,
                                  irq_handler_t pmu_handler);
-       void (*enable_irq)(int irq);
-       void (*disable_irq)(int irq);
+       int (*runtime_resume)(struct device *dev);
+       int (*runtime_suspend)(struct device *dev);
 };
 
-#ifdef CONFIG_CPU_HAS_PMU
-
-/**
- * reserve_pmu() - reserve the hardware performance counters
- *
- * Reserve the hardware performance counters in the system for exclusive use.
- * Returns 0 on success or -EBUSY if the lock is already held.
- */
-extern int
-reserve_pmu(enum arm_pmu_type type);
-
-/**
- * release_pmu() - Relinquish control of the performance counters
- *
- * Release the performance counters and allow someone else to use them.
- */
-extern void
-release_pmu(enum arm_pmu_type type);
-
-#else /* CONFIG_CPU_HAS_PMU */
-
-#include <linux/err.h>
-
-static inline int
-reserve_pmu(enum arm_pmu_type type)
-{
-       return -ENODEV;
-}
-
-static inline void
-release_pmu(enum arm_pmu_type type)    { }
-
-#endif /* CONFIG_CPU_HAS_PMU */
-
 #ifdef CONFIG_HW_PERF_EVENTS
 
 /* The events for a given PMU register set. */
@@ -103,7 +64,6 @@ struct pmu_hw_events {
 
 struct arm_pmu {
        struct pmu      pmu;
-       enum arm_pmu_type type;
        cpumask_t       active_irqs;
        char            *name;
        irqreturn_t     (*handle_irq)(int irq_num, void *dev);
@@ -118,6 +78,8 @@ struct arm_pmu {
        void            (*start)(void);
        void            (*stop)(void);
        void            (*reset)(void *);
+       int             (*request_irq)(irq_handler_t handler);
+       void            (*free_irq)(void);
        int             (*map_event)(struct perf_event *event);
        int             num_events;
        atomic_t        active_events;
@@ -129,7 +91,9 @@ struct arm_pmu {
 
 #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
 
-int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type);
+extern const struct dev_pm_ops armpmu_dev_pm_ops;
+
+int armpmu_register(struct arm_pmu *armpmu, char *name, int type);
 
 u64 armpmu_event_update(struct perf_event *event,
                        struct hw_perf_event *hwc,
@@ -139,6 +103,13 @@ int armpmu_event_set_period(struct perf_event *event,
                            struct hw_perf_event *hwc,
                            int idx);
 
+int armpmu_map_event(struct perf_event *event,
+                    const unsigned (*event_map)[PERF_COUNT_HW_MAX],
+                    const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
+                                               [PERF_COUNT_HW_CACHE_OP_MAX]
+                                               [PERF_COUNT_HW_CACHE_RESULT_MAX],
+                    u32 raw_event_mask);
+
 #endif /* CONFIG_HW_PERF_EVENTS */
 
 #endif /* __ARM_PMU_H__ */
index 7ad2d5c..1c43214 100644 (file)
@@ -69,8 +69,7 @@ obj-$(CONFIG_CPU_XSC3)                += xscale-cp0.o
 obj-$(CONFIG_CPU_MOHAWK)       += xscale-cp0.o
 obj-$(CONFIG_CPU_PJ4)          += pj4-cp0.o
 obj-$(CONFIG_IWMMXT)           += iwmmxt.o
-obj-$(CONFIG_CPU_HAS_PMU)      += pmu.o
-obj-$(CONFIG_HW_PERF_EVENTS)   += perf_event.o
+obj-$(CONFIG_HW_PERF_EVENTS)   += perf_event.o perf_event_cpu.o
 AFLAGS_iwmmxt.o                        := -Wa,-mcpu=iwmmxt
 obj-$(CONFIG_ARM_CPU_TOPOLOGY)  += topology.o
 
index 9cf16b8..9b72261 100644 (file)
@@ -13,6 +13,7 @@
 #include <linux/io.h>
 
 #include <asm/mach-types.h>
+#include <asm/mach/map.h>
 #include <asm/mach/pci.h>
 
 static int debug_pci;
@@ -414,6 +415,38 @@ static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
        return irq;
 }
 
+static int __init pcibios_init_resources(int busnr, struct pci_sys_data *sys)
+{
+       int ret;
+       struct pci_host_bridge_window *window;
+
+       if (list_empty(&sys->resources)) {
+               pci_add_resource_offset(&sys->resources,
+                        &iomem_resource, sys->mem_offset);
+       }
+
+       list_for_each_entry(window, &sys->resources, list) {
+               if (resource_type(window->res) == IORESOURCE_IO)
+                       return 0;
+       }
+
+       sys->io_res.start = (busnr * SZ_64K) ?  : pcibios_min_io;
+       sys->io_res.end = (busnr + 1) * SZ_64K - 1;
+       sys->io_res.flags = IORESOURCE_IO;
+       sys->io_res.name = sys->io_res_name;
+       sprintf(sys->io_res_name, "PCI%d I/O", busnr);
+
+       ret = request_resource(&ioport_resource, &sys->io_res);
+       if (ret) {
+               pr_err("PCI: unable to allocate I/O port region (%d)\n", ret);
+               return ret;
+       }
+       pci_add_resource_offset(&sys->resources, &sys->io_res,
+                               sys->io_offset);
+
+       return 0;
+}
+
 static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
 {
        struct pci_sys_data *sys = NULL;
@@ -436,11 +469,10 @@ static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
                ret = hw->setup(nr, sys);
 
                if (ret > 0) {
-                       if (list_empty(&sys->resources)) {
-                               pci_add_resource_offset(&sys->resources,
-                                        &ioport_resource, sys->io_offset);
-                               pci_add_resource_offset(&sys->resources,
-                                        &iomem_resource, sys->mem_offset);
+                       ret = pcibios_init_resources(nr, sys);
+                       if (ret)  {
+                               kfree(sys);
+                               break;
                        }
 
                        if (hw->scan)
@@ -618,3 +650,15 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 
        return 0;
 }
+
+void __init pci_map_io_early(unsigned long pfn)
+{
+       struct map_desc pci_io_desc = {
+               .virtual        = PCI_IO_VIRT_BASE,
+               .type           = MT_DEVICE,
+               .length         = SZ_64K,
+       };
+
+       pci_io_desc.pfn = pfn;
+       iotable_init(&pci_io_desc, 1);
+}
index ab243b8..93971b1 100644 (file)
  */
 #define pr_fmt(fmt) "hw perfevents: " fmt
 
-#include <linux/bitmap.h>
-#include <linux/interrupt.h>
 #include <linux/kernel.h>
-#include <linux/export.h>
-#include <linux/perf_event.h>
 #include <linux/platform_device.h>
-#include <linux/spinlock.h>
+#include <linux/pm_runtime.h>
 #include <linux/uaccess.h>
 
-#include <asm/cputype.h>
-#include <asm/irq.h>
 #include <asm/irq_regs.h>
 #include <asm/pmu.h>
 #include <asm/stacktrace.h>
 
-/*
- * ARMv6 supports a maximum of 3 events, starting from index 0. If we add
- * another platform that supports more, we need to increase this to be the
- * largest of all platforms.
- *
- * ARMv7 supports up to 32 events:
- *  cycle counter CCNT + 31 events counters CNT0..30.
- *  Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
- */
-#define ARMPMU_MAX_HWEVENTS            32
-
-static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
-static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
-static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
-
-#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
-
-/* Set at runtime when we know what CPU type we are. */
-static struct arm_pmu *cpu_pmu;
-
-const char *perf_pmu_name(void)
-{
-       if (!cpu_pmu)
-               return NULL;
-
-       return cpu_pmu->pmu.name;
-}
-EXPORT_SYMBOL_GPL(perf_pmu_name);
-
-int perf_num_counters(void)
-{
-       int max_events = 0;
-
-       if (cpu_pmu != NULL)
-               max_events = cpu_pmu->num_events;
-
-       return max_events;
-}
-EXPORT_SYMBOL_GPL(perf_num_counters);
-
-#define HW_OP_UNSUPPORTED              0xFFFF
-
-#define C(_x) \
-       PERF_COUNT_HW_CACHE_##_x
-
-#define CACHE_OP_UNSUPPORTED           0xFFFF
-
 static int
 armpmu_map_cache_event(const unsigned (*cache_map)
                                      [PERF_COUNT_HW_CACHE_MAX]
@@ -104,7 +51,7 @@ armpmu_map_cache_event(const unsigned (*cache_map)
 }
 
 static int
-armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
+armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
 {
        int mapping = (*event_map)[config];
        return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
@@ -116,19 +63,20 @@ armpmu_map_raw_event(u32 raw_event_mask, u64 config)
        return (int)(config & raw_event_mask);
 }
 
-static int map_cpu_event(struct perf_event *event,
-                        const unsigned (*event_map)[PERF_COUNT_HW_MAX],
-                        const unsigned (*cache_map)
-                                       [PERF_COUNT_HW_CACHE_MAX]
-                                       [PERF_COUNT_HW_CACHE_OP_MAX]
-                                       [PERF_COUNT_HW_CACHE_RESULT_MAX],
-                        u32 raw_event_mask)
+int
+armpmu_map_event(struct perf_event *event,
+                const unsigned (*event_map)[PERF_COUNT_HW_MAX],
+                const unsigned (*cache_map)
+                               [PERF_COUNT_HW_CACHE_MAX]
+                               [PERF_COUNT_HW_CACHE_OP_MAX]
+                               [PERF_COUNT_HW_CACHE_RESULT_MAX],
+                u32 raw_event_mask)
 {
        u64 config = event->attr.config;
 
        switch (event->attr.type) {
        case PERF_TYPE_HARDWARE:
-               return armpmu_map_event(event_map, config);
+               return armpmu_map_hw_event(event_map, config);
        case PERF_TYPE_HW_CACHE:
                return armpmu_map_cache_event(cache_map, config);
        case PERF_TYPE_RAW:
@@ -222,7 +170,6 @@ armpmu_stop(struct perf_event *event, int flags)
         */
        if (!(hwc->state & PERF_HES_STOPPED)) {
                armpmu->disable(hwc, hwc->idx);
-               barrier(); /* why? */
                armpmu_event_update(event, hwc, hwc->idx);
                hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
        }
@@ -350,99 +297,41 @@ validate_group(struct perf_event *event)
        return 0;
 }
 
-static irqreturn_t armpmu_platform_irq(int irq, void *dev)
+static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
 {
        struct arm_pmu *armpmu = (struct arm_pmu *) dev;
        struct platform_device *plat_device = armpmu->plat_device;
        struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
 
-       return plat->handle_irq(irq, dev, armpmu->handle_irq);
+       if (plat && plat->handle_irq)
+               return plat->handle_irq(irq, dev, armpmu->handle_irq);
+       else
+               return armpmu->handle_irq(irq, dev);
 }
 
 static void
 armpmu_release_hardware(struct arm_pmu *armpmu)
 {
-       int i, irq, irqs;
-       struct platform_device *pmu_device = armpmu->plat_device;
-       struct arm_pmu_platdata *plat =
-               dev_get_platdata(&pmu_device->dev);
-
-       irqs = min(pmu_device->num_resources, num_possible_cpus());
-
-       for (i = 0; i < irqs; ++i) {
-               if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
-                       continue;
-               irq = platform_get_irq(pmu_device, i);
-               if (irq >= 0) {
-                       if (plat && plat->disable_irq)
-                               plat->disable_irq(irq);
-                       free_irq(irq, armpmu);
-               }
-       }
-
-       release_pmu(armpmu->type);
+       armpmu->free_irq();
+       pm_runtime_put_sync(&armpmu->plat_device->dev);
 }
 
 static int
 armpmu_reserve_hardware(struct arm_pmu *armpmu)
 {
-       struct arm_pmu_platdata *plat;
-       irq_handler_t handle_irq;
-       int i, err, irq, irqs;
+       int err;
        struct platform_device *pmu_device = armpmu->plat_device;
 
        if (!pmu_device)
                return -ENODEV;
 
-       err = reserve_pmu(armpmu->type);
+       pm_runtime_get_sync(&pmu_device->dev);
+       err = armpmu->request_irq(armpmu_dispatch_irq);
        if (err) {
-               pr_warning("unable to reserve pmu\n");
+               armpmu_release_hardware(armpmu);
                return err;
        }
 
-       plat = dev_get_platdata(&pmu_device->dev);
-       if (plat && plat->handle_irq)
-               handle_irq = armpmu_platform_irq;
-       else
-               handle_irq = armpmu->handle_irq;
-
-       irqs = min(pmu_device->num_resources, num_possible_cpus());
-       if (irqs < 1) {
-               pr_err("no irqs for PMUs defined\n");
-               return -ENODEV;
-       }
-
-       for (i = 0; i < irqs; ++i) {
-               err = 0;
-               irq = platform_get_irq(pmu_device, i);
-               if (irq < 0)
-                       continue;
-
-               /*
-                * If we have a single PMU interrupt that we can't shift,
-                * assume that we're running on a uniprocessor machine and
-                * continue. Otherwise, continue without this interrupt.
-                */
-               if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
-                       pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
-                                   irq, i);
-                       continue;
-               }
-
-               err = request_irq(irq, handle_irq,
-                                 IRQF_DISABLED | IRQF_NOBALANCING,
-                                 "arm-pmu", armpmu);
-               if (err) {
-                       pr_err("unable to request IRQ%d for ARM PMU counters\n",
-                               irq);
-                       armpmu_release_hardware(armpmu);
-                       return err;
-               } else if (plat && plat->enable_irq)
-                       plat->enable_irq(irq);
-
-               cpumask_set_cpu(i, &armpmu->active_irqs);
-       }
-
        return 0;
 }
 
@@ -581,6 +470,32 @@ static void armpmu_disable(struct pmu *pmu)
        armpmu->stop();
 }
 
+#ifdef CONFIG_PM_RUNTIME
+static int armpmu_runtime_resume(struct device *dev)
+{
+       struct arm_pmu_platdata *plat = dev_get_platdata(dev);
+
+       if (plat && plat->runtime_resume)
+               return plat->runtime_resume(dev);
+
+       return 0;
+}
+
+static int armpmu_runtime_suspend(struct device *dev)
+{
+       struct arm_pmu_platdata *plat = dev_get_platdata(dev);
+
+       if (plat && plat->runtime_suspend)
+               return plat->runtime_suspend(dev);
+
+       return 0;
+}
+#endif
+
+const struct dev_pm_ops armpmu_dev_pm_ops = {
+       SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL)
+};
+
 static void __init armpmu_init(struct arm_pmu *armpmu)
 {
        atomic_set(&armpmu->active_events, 0);
@@ -598,174 +513,14 @@ static void __init armpmu_init(struct arm_pmu *armpmu)
        };
 }
 
-int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type)
+int armpmu_register(struct arm_pmu *armpmu, char *name, int type)
 {
        armpmu_init(armpmu);
+       pr_info("enabled with %s PMU driver, %d counters available\n",
+                       armpmu->name, armpmu->num_events);
        return perf_pmu_register(&armpmu->pmu, name, type);
 }
 
-/* Include the PMU-specific implementations. */
-#include "perf_event_xscale.c"
-#include "perf_event_v6.c"
-#include "perf_event_v7.c"
-
-/*
- * Ensure the PMU has sane values out of reset.
- * This requires SMP to be available, so exists as a separate initcall.
- */
-static int __init
-cpu_pmu_reset(void)
-{
-       if (cpu_pmu && cpu_pmu->reset)
-               return on_each_cpu(cpu_pmu->reset, NULL, 1);
-       return 0;
-}
-arch_initcall(cpu_pmu_reset);
-
-/*
- * PMU platform driver and devicetree bindings.
- */
-static struct of_device_id armpmu_of_device_ids[] = {
-       {.compatible = "arm,cortex-a9-pmu"},
-       {.compatible = "arm,cortex-a8-pmu"},
-       {.compatible = "arm,arm1136-pmu"},
-       {.compatible = "arm,arm1176-pmu"},
-       {},
-};
-
-static struct platform_device_id armpmu_plat_device_ids[] = {
-       {.name = "arm-pmu"},
-       {},
-};
-
-static int __devinit armpmu_device_probe(struct platform_device *pdev)
-{
-       if (!cpu_pmu)
-               return -ENODEV;
-
-       cpu_pmu->plat_device = pdev;
-       return 0;
-}
-
-static struct platform_driver armpmu_driver = {
-       .driver         = {
-               .name   = "arm-pmu",
-               .of_match_table = armpmu_of_device_ids,
-       },
-       .probe          = armpmu_device_probe,
-       .id_table       = armpmu_plat_device_ids,
-};
-
-static int __init register_pmu_driver(void)
-{
-       return platform_driver_register(&armpmu_driver);
-}
-device_initcall(register_pmu_driver);
-
-static struct pmu_hw_events *armpmu_get_cpu_events(void)
-{
-       return &__get_cpu_var(cpu_hw_events);
-}
-
-static void __init cpu_pmu_init(struct arm_pmu *armpmu)
-{
-       int cpu;
-       for_each_possible_cpu(cpu) {
-               struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
-               events->events = per_cpu(hw_events, cpu);
-               events->used_mask = per_cpu(used_mask, cpu);
-               raw_spin_lock_init(&events->pmu_lock);
-       }
-       armpmu->get_hw_events = armpmu_get_cpu_events;
-       armpmu->type = ARM_PMU_DEVICE_CPU;
-}
-
-/*
- * PMU hardware loses all context when a CPU goes offline.
- * When a CPU is hotplugged back in, since some hardware registers are
- * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
- * junk values out of them.
- */
-static int __cpuinit pmu_cpu_notify(struct notifier_block *b,
-                                       unsigned long action, void *hcpu)
-{
-       if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
-               return NOTIFY_DONE;
-
-       if (cpu_pmu && cpu_pmu->reset)
-               cpu_pmu->reset(NULL);
-
-       return NOTIFY_OK;
-}
-
-static struct notifier_block __cpuinitdata pmu_cpu_notifier = {
-       .notifier_call = pmu_cpu_notify,
-};
-
-/*
- * CPU PMU identification and registration.
- */
-static int __init
-init_hw_perf_events(void)
-{
-       unsigned long cpuid = read_cpuid_id();
-       unsigned long implementor = (cpuid & 0xFF000000) >> 24;
-       unsigned long part_number = (cpuid & 0xFFF0);
-
-       /* ARM Ltd CPUs. */
-       if (0x41 == implementor) {
-               switch (part_number) {
-               case 0xB360:    /* ARM1136 */
-               case 0xB560:    /* ARM1156 */
-               case 0xB760:    /* ARM1176 */
-                       cpu_pmu = armv6pmu_init();
-                       break;
-               case 0xB020:    /* ARM11mpcore */
-                       cpu_pmu = armv6mpcore_pmu_init();
-                       break;
-               case 0xC080:    /* Cortex-A8 */
-                       cpu_pmu = armv7_a8_pmu_init();
-                       break;
-               case 0xC090:    /* Cortex-A9 */
-                       cpu_pmu = armv7_a9_pmu_init();
-                       break;
-               case 0xC050:    /* Cortex-A5 */
-                       cpu_pmu = armv7_a5_pmu_init();
-                       break;
-               case 0xC0F0:    /* Cortex-A15 */
-                       cpu_pmu = armv7_a15_pmu_init();
-                       break;
-               case 0xC070:    /* Cortex-A7 */
-                       cpu_pmu = armv7_a7_pmu_init();
-                       break;
-               }
-       /* Intel CPUs [xscale]. */
-       } else if (0x69 == implementor) {
-               part_number = (cpuid >> 13) & 0x7;
-               switch (part_number) {
-               case 1:
-                       cpu_pmu = xscale1pmu_init();
-                       break;
-               case 2:
-                       cpu_pmu = xscale2pmu_init();
-                       break;
-               }
-       }
-
-       if (cpu_pmu) {
-               pr_info("enabled with %s PMU driver, %d counters available\n",
-                       cpu_pmu->name, cpu_pmu->num_events);
-               cpu_pmu_init(cpu_pmu);
-               register_cpu_notifier(&pmu_cpu_notifier);
-               armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW);
-       } else {
-               pr_info("no hardware support available\n");
-       }
-
-       return 0;
-}
-early_initcall(init_hw_perf_events);
-
 /*
  * Callchain handling code.
  */
diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c
new file mode 100644 (file)
index 0000000..8d7d8d4
--- /dev/null
@@ -0,0 +1,295 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) 2012 ARM Limited
+ *
+ * Author: Will Deacon <will.deacon@arm.com>
+ */
+#define pr_fmt(fmt) "CPU PMU: " fmt
+
+#include <linux/bitmap.h>
+#include <linux/export.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+
+#include <asm/cputype.h>
+#include <asm/irq_regs.h>
+#include <asm/pmu.h>
+
+/* Set at runtime when we know what CPU type we are. */
+static struct arm_pmu *cpu_pmu;
+
+static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
+static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
+static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
+
+/*
+ * Despite the names, these two functions are CPU-specific and are used
+ * by the OProfile/perf code.
+ */
+const char *perf_pmu_name(void)
+{
+       if (!cpu_pmu)
+               return NULL;
+
+       return cpu_pmu->pmu.name;
+}
+EXPORT_SYMBOL_GPL(perf_pmu_name);
+
+int perf_num_counters(void)
+{
+       int max_events = 0;
+
+       if (cpu_pmu != NULL)
+               max_events = cpu_pmu->num_events;
+
+       return max_events;
+}
+EXPORT_SYMBOL_GPL(perf_num_counters);
+
+/* Include the PMU-specific implementations. */
+#include "perf_event_xscale.c"
+#include "perf_event_v6.c"
+#include "perf_event_v7.c"
+
+static struct pmu_hw_events *cpu_pmu_get_cpu_events(void)
+{
+       return &__get_cpu_var(cpu_hw_events);
+}
+
+static void cpu_pmu_free_irq(void)
+{
+       int i, irq, irqs;
+       struct platform_device *pmu_device = cpu_pmu->plat_device;
+
+       irqs = min(pmu_device->num_resources, num_possible_cpus());
+
+       for (i = 0; i < irqs; ++i) {
+               if (!cpumask_test_and_clear_cpu(i, &cpu_pmu->active_irqs))
+                       continue;
+               irq = platform_get_irq(pmu_device, i);
+               if (irq >= 0)
+                       free_irq(irq, cpu_pmu);
+       }
+}
+
+static int cpu_pmu_request_irq(irq_handler_t handler)
+{
+       int i, err, irq, irqs;
+       struct platform_device *pmu_device = cpu_pmu->plat_device;
+
+       if (!pmu_device)
+               return -ENODEV;
+
+       irqs = min(pmu_device->num_resources, num_possible_cpus());
+       if (irqs < 1) {
+               pr_err("no irqs for PMUs defined\n");
+               return -ENODEV;
+       }
+
+       for (i = 0; i < irqs; ++i) {
+               err = 0;
+               irq = platform_get_irq(pmu_device, i);
+               if (irq < 0)
+                       continue;
+
+               /*
+                * If we have a single PMU interrupt that we can't shift,
+                * assume that we're running on a uniprocessor machine and
+                * continue. Otherwise, continue without this interrupt.
+                */
+               if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
+                       pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
+                                   irq, i);
+                       continue;
+               }
+
+               err = request_irq(irq, handler, IRQF_NOBALANCING, "arm-pmu",
+                                 cpu_pmu);
+               if (err) {
+                       pr_err("unable to request IRQ%d for ARM PMU counters\n",
+                               irq);
+                       return err;
+               }
+
+               cpumask_set_cpu(i, &cpu_pmu->active_irqs);
+       }
+
+       return 0;
+}
+
+static void __devinit cpu_pmu_init(struct arm_pmu *cpu_pmu)
+{
+       int cpu;
+       for_each_possible_cpu(cpu) {
+               struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
+               events->events = per_cpu(hw_events, cpu);
+               events->used_mask = per_cpu(used_mask, cpu);
+               raw_spin_lock_init(&events->pmu_lock);
+       }
+
+       cpu_pmu->get_hw_events  = cpu_pmu_get_cpu_events;
+       cpu_pmu->request_irq    = cpu_pmu_request_irq;
+       cpu_pmu->free_irq       = cpu_pmu_free_irq;
+
+       /* Ensure the PMU has sane values out of reset. */
+       if (cpu_pmu && cpu_pmu->reset)
+               on_each_cpu(cpu_pmu->reset, NULL, 1);
+}
+
+/*
+ * PMU hardware loses all context when a CPU goes offline.
+ * When a CPU is hotplugged back in, since some hardware registers are
+ * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
+ * junk values out of them.
+ */
+static int __cpuinit cpu_pmu_notify(struct notifier_block *b,
+                                   unsigned long action, void *hcpu)
+{
+       if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
+               return NOTIFY_DONE;
+
+       if (cpu_pmu && cpu_pmu->reset)
+               cpu_pmu->reset(NULL);
+
+       return NOTIFY_OK;
+}
+
+static struct notifier_block __cpuinitdata cpu_pmu_hotplug_notifier = {
+       .notifier_call = cpu_pmu_notify,
+};
+
+/*
+ * PMU platform driver and devicetree bindings.
+ */
+static struct of_device_id __devinitdata cpu_pmu_of_device_ids[] = {
+       {.compatible = "arm,cortex-a15-pmu",    .data = armv7_a15_pmu_init},
+       {.compatible = "arm,cortex-a9-pmu",     .data = armv7_a9_pmu_init},
+       {.compatible = "arm,cortex-a8-pmu",     .data = armv7_a8_pmu_init},
+       {.compatible = "arm,cortex-a7-pmu",     .data = armv7_a7_pmu_init},
+       {.compatible = "arm,cortex-a5-pmu",     .data = armv7_a5_pmu_init},
+       {.compatible = "arm,arm11mpcore-pmu",   .data = armv6mpcore_pmu_init},
+       {.compatible = "arm,arm1176-pmu",       .data = armv6pmu_init},
+       {.compatible = "arm,arm1136-pmu",       .data = armv6pmu_init},
+       {},
+};
+
+static struct platform_device_id __devinitdata cpu_pmu_plat_device_ids[] = {
+       {.name = "arm-pmu"},
+       {},
+};
+
+/*
+ * CPU PMU identification and probing.
+ */
+static struct arm_pmu *__devinit probe_current_pmu(void)
+{
+       struct arm_pmu *pmu = NULL;
+       int cpu = get_cpu();
+       unsigned long cpuid = read_cpuid_id();
+       unsigned long implementor = (cpuid & 0xFF000000) >> 24;
+       unsigned long part_number = (cpuid & 0xFFF0);
+
+       pr_info("probing PMU on CPU %d\n", cpu);
+
+       /* ARM Ltd CPUs. */
+       if (0x41 == implementor) {
+               switch (part_number) {
+               case 0xB360:    /* ARM1136 */
+               case 0xB560:    /* ARM1156 */
+               case 0xB760:    /* ARM1176 */
+                       pmu = armv6pmu_init();
+                       break;
+               case 0xB020:    /* ARM11mpcore */
+                       pmu = armv6mpcore_pmu_init();
+                       break;
+               case 0xC080:    /* Cortex-A8 */
+                       pmu = armv7_a8_pmu_init();
+                       break;
+               case 0xC090:    /* Cortex-A9 */
+                       pmu = armv7_a9_pmu_init();
+                       break;
+               case 0xC050:    /* Cortex-A5 */
+                       pmu = armv7_a5_pmu_init();
+                       break;
+               case 0xC0F0:    /* Cortex-A15 */
+                       pmu = armv7_a15_pmu_init();
+                       break;
+               case 0xC070:    /* Cortex-A7 */
+                       pmu = armv7_a7_pmu_init();
+                       break;
+               }
+       /* Intel CPUs [xscale]. */
+       } else if (0x69 == implementor) {
+               part_number = (cpuid >> 13) & 0x7;
+               switch (part_number) {
+               case 1:
+                       pmu = xscale1pmu_init();
+                       break;
+               case 2:
+                       pmu = xscale2pmu_init();
+                       break;
+               }
+       }
+
+       put_cpu();
+       return pmu;
+}
+
+static int __devinit cpu_pmu_device_probe(struct platform_device *pdev)
+{
+       const struct of_device_id *of_id;
+       struct arm_pmu *(*init_fn)(void);
+       struct device_node *node = pdev->dev.of_node;
+
+       if (cpu_pmu) {
+               pr_info("attempt to register multiple PMU devices!");
+               return -ENOSPC;
+       }
+
+       if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) {
+               init_fn = of_id->data;
+               cpu_pmu = init_fn();
+       } else {
+               cpu_pmu = probe_current_pmu();
+       }
+
+       if (!cpu_pmu)
+               return -ENODEV;
+
+       cpu_pmu->plat_device = pdev;
+       cpu_pmu_init(cpu_pmu);
+       register_cpu_notifier(&cpu_pmu_hotplug_notifier);
+       armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW);
+
+       return 0;
+}
+
+static struct platform_driver cpu_pmu_driver = {
+       .driver         = {
+               .name   = "arm-pmu",
+               .pm     = &armpmu_dev_pm_ops,
+               .of_match_table = cpu_pmu_of_device_ids,
+       },
+       .probe          = cpu_pmu_device_probe,
+       .id_table       = cpu_pmu_plat_device_ids,
+};
+
+static int __init register_pmu_driver(void)
+{
+       return platform_driver_register(&cpu_pmu_driver);
+}
+device_initcall(register_pmu_driver);
index c90fcb2..6ccc079 100644 (file)
@@ -645,7 +645,7 @@ armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc,
 
 static int armv6_map_event(struct perf_event *event)
 {
-       return map_cpu_event(event, &armv6_perf_map,
+       return armpmu_map_event(event, &armv6_perf_map,
                                &armv6_perf_cache_map, 0xFF);
 }
 
@@ -664,7 +664,7 @@ static struct arm_pmu armv6pmu = {
        .max_period             = (1LLU << 32) - 1,
 };
 
-static struct arm_pmu *__init armv6pmu_init(void)
+static struct arm_pmu *__devinit armv6pmu_init(void)
 {
        return &armv6pmu;
 }
@@ -679,7 +679,7 @@ static struct arm_pmu *__init armv6pmu_init(void)
 
 static int armv6mpcore_map_event(struct perf_event *event)
 {
-       return map_cpu_event(event, &armv6mpcore_perf_map,
+       return armpmu_map_event(event, &armv6mpcore_perf_map,
                                &armv6mpcore_perf_cache_map, 0xFF);
 }
 
@@ -698,17 +698,17 @@ static struct arm_pmu armv6mpcore_pmu = {
        .max_period             = (1LLU << 32) - 1,
 };
 
-static struct arm_pmu *__init armv6mpcore_pmu_init(void)
+static struct arm_pmu *__devinit armv6mpcore_pmu_init(void)
 {
        return &armv6mpcore_pmu;
 }
 #else
-static struct arm_pmu *__init armv6pmu_init(void)
+static struct arm_pmu *__devinit armv6pmu_init(void)
 {
        return NULL;
 }
 
-static struct arm_pmu *__init armv6mpcore_pmu_init(void)
+static struct arm_pmu *__devinit armv6mpcore_pmu_init(void)
 {
        return NULL;
 }
index f04070b..bd4b090 100644 (file)
@@ -1204,31 +1204,31 @@ static void armv7pmu_reset(void *info)
 
 static int armv7_a8_map_event(struct perf_event *event)
 {
-       return map_cpu_event(event, &armv7_a8_perf_map,
+       return armpmu_map_event(event, &armv7_a8_perf_map,
                                &armv7_a8_perf_cache_map, 0xFF);
 }
 
 static int armv7_a9_map_event(struct perf_event *event)
 {
-       return map_cpu_event(event, &armv7_a9_perf_map,
+       return armpmu_map_event(event, &armv7_a9_perf_map,
                                &armv7_a9_perf_cache_map, 0xFF);
 }
 
 static int armv7_a5_map_event(struct perf_event *event)
 {
-       return map_cpu_event(event, &armv7_a5_perf_map,
+       return armpmu_map_event(event, &armv7_a5_perf_map,
                                &armv7_a5_perf_cache_map, 0xFF);
 }
 
 static int armv7_a15_map_event(struct perf_event *event)
 {
-       return map_cpu_event(event, &armv7_a15_perf_map,
+       return armpmu_map_event(event, &armv7_a15_perf_map,
                                &armv7_a15_perf_cache_map, 0xFF);
 }
 
 static int armv7_a7_map_event(struct perf_event *event)
 {
-       return map_cpu_event(event, &armv7_a7_perf_map,
+       return armpmu_map_event(event, &armv7_a7_perf_map,
                                &armv7_a7_perf_cache_map, 0xFF);
 }
 
@@ -1245,7 +1245,7 @@ static struct arm_pmu armv7pmu = {
        .max_period             = (1LLU << 32) - 1,
 };
 
-static u32 __init armv7_read_num_pmnc_events(void)
+static u32 __devinit armv7_read_num_pmnc_events(void)
 {
        u32 nb_cnt;
 
@@ -1256,7 +1256,7 @@ static u32 __init armv7_read_num_pmnc_events(void)
        return nb_cnt + 1;
 }
 
-static struct arm_pmu *__init armv7_a8_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a8_pmu_init(void)
 {
        armv7pmu.name           = "ARMv7 Cortex-A8";
        armv7pmu.map_event      = armv7_a8_map_event;
@@ -1264,7 +1264,7 @@ static struct arm_pmu *__init armv7_a8_pmu_init(void)
        return &armv7pmu;
 }
 
-static struct arm_pmu *__init armv7_a9_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a9_pmu_init(void)
 {
        armv7pmu.name           = "ARMv7 Cortex-A9";
        armv7pmu.map_event      = armv7_a9_map_event;
@@ -1272,7 +1272,7 @@ static struct arm_pmu *__init armv7_a9_pmu_init(void)
        return &armv7pmu;
 }
 
-static struct arm_pmu *__init armv7_a5_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a5_pmu_init(void)
 {
        armv7pmu.name           = "ARMv7 Cortex-A5";
        armv7pmu.map_event      = armv7_a5_map_event;
@@ -1280,7 +1280,7 @@ static struct arm_pmu *__init armv7_a5_pmu_init(void)
        return &armv7pmu;
 }
 
-static struct arm_pmu *__init armv7_a15_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a15_pmu_init(void)
 {
        armv7pmu.name           = "ARMv7 Cortex-A15";
        armv7pmu.map_event      = armv7_a15_map_event;
@@ -1289,7 +1289,7 @@ static struct arm_pmu *__init armv7_a15_pmu_init(void)
        return &armv7pmu;
 }
 
-static struct arm_pmu *__init armv7_a7_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a7_pmu_init(void)
 {
        armv7pmu.name           = "ARMv7 Cortex-A7";
        armv7pmu.map_event      = armv7_a7_map_event;
@@ -1298,27 +1298,27 @@ static struct arm_pmu *__init armv7_a7_pmu_init(void)
        return &armv7pmu;
 }
 #else
-static struct arm_pmu *__init armv7_a8_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a8_pmu_init(void)
 {
        return NULL;
 }
 
-static struct arm_pmu *__init armv7_a9_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a9_pmu_init(void)
 {
        return NULL;
 }
 
-static struct arm_pmu *__init armv7_a5_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a5_pmu_init(void)
 {
        return NULL;
 }
 
-static struct arm_pmu *__init armv7_a15_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a15_pmu_init(void)
 {
        return NULL;
 }
 
-static struct arm_pmu *__init armv7_a7_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a7_pmu_init(void)
 {
        return NULL;
 }
index f759fe0..426e19f 100644 (file)
@@ -430,7 +430,7 @@ xscale1pmu_write_counter(int counter, u32 val)
 
 static int xscale_map_event(struct perf_event *event)
 {
-       return map_cpu_event(event, &xscale_perf_map,
+       return armpmu_map_event(event, &xscale_perf_map,
                                &xscale_perf_cache_map, 0xFF);
 }
 
@@ -449,7 +449,7 @@ static struct arm_pmu xscale1pmu = {
        .max_period     = (1LLU << 32) - 1,
 };
 
-static struct arm_pmu *__init xscale1pmu_init(void)
+static struct arm_pmu *__devinit xscale1pmu_init(void)
 {
        return &xscale1pmu;
 }
@@ -816,17 +816,17 @@ static struct arm_pmu xscale2pmu = {
        .max_period     = (1LLU << 32) - 1,
 };
 
-static struct arm_pmu *__init xscale2pmu_init(void)
+static struct arm_pmu *__devinit xscale2pmu_init(void)
 {
        return &xscale2pmu;
 }
 #else
-static struct arm_pmu *__init xscale1pmu_init(void)
+static struct arm_pmu *__devinit xscale1pmu_init(void)
 {
        return NULL;
 }
 
-static struct arm_pmu *__init xscale2pmu_init(void)
+static struct arm_pmu *__devinit xscale2pmu_init(void)
 {
        return NULL;
 }
diff --git a/arch/arm/kernel/pmu.c b/arch/arm/kernel/pmu.c
deleted file mode 100644 (file)
index 2334bf8..0000000
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- *  linux/arch/arm/kernel/pmu.c
- *
- *  Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
- *  Copyright (C) 2010 ARM Ltd, Will Deacon
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/err.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-
-#include <asm/pmu.h>
-
-/*
- * PMU locking to ensure mutual exclusion between different subsystems.
- */
-static unsigned long pmu_lock[BITS_TO_LONGS(ARM_NUM_PMU_DEVICES)];
-
-int
-reserve_pmu(enum arm_pmu_type type)
-{
-       return test_and_set_bit_lock(type, pmu_lock) ? -EBUSY : 0;
-}
-EXPORT_SYMBOL_GPL(reserve_pmu);
-
-void
-release_pmu(enum arm_pmu_type type)
-{
-       clear_bit_unlock(type, pmu_lock);
-}
-EXPORT_SYMBOL_GPL(release_pmu);
index 46090e6..6bd7300 100644 (file)
@@ -47,7 +47,7 @@ static void at91x40_idle(void)
         * Disable the processor clock.  The processor will be automatically
         * re-enabled by an interrupt or by a reset.
         */
-       __raw_writel(AT91_PS_CR_CPU, AT91_PS_CR);
+       __raw_writel(AT91_PS_CR_CPU, AT91_IO_P2V(AT91_PS_CR));
        cpu_do_idle();
 }
 
index 6ca680a..ee06d7b 100644 (file)
 #include <mach/at91_tc.h>
 
 #define at91_tc_read(field) \
-       __raw_readl(AT91_TC + field)
+       __raw_readl(AT91_IO_P2V(AT91_TC) + field)
 
 #define at91_tc_write(field, value) \
-       __raw_writel(value, AT91_TC + field);
+       __raw_writel(value, AT91_IO_P2V(AT91_TC) + field);
 
 /*
  *     3 counter/timer units present.
index 09242b6..711a789 100644 (file)
  * to 0xFEF78000 .. 0xFF000000.  (544Kb)
  */
 #define AT91_IO_PHYS_BASE      0xFFF78000
-#define AT91_IO_VIRT_BASE      (0xFF000000 - AT91_IO_SIZE)
+#define AT91_IO_VIRT_BASE      IOMEM(0xFF000000 - AT91_IO_SIZE)
 #else
 /*
  * Identity mapping for the non MMU case.
  */
 #define AT91_IO_PHYS_BASE      AT91_BASE_SYS
-#define AT91_IO_VIRT_BASE      AT91_IO_PHYS_BASE
+#define AT91_IO_VIRT_BASE      IOMEM(AT91_IO_PHYS_BASE)
 #endif
 
 #define AT91_IO_SIZE           (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1)
index 6f6118d..97ad68a 100644 (file)
@@ -94,7 +94,7 @@ static const u32 uarts_sam9x5[] = {
        0,
 };
 
-static inline const u32* decomp_soc_detect(u32 dbgu_base)
+static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
 {
        u32 cidr, socid;
 
@@ -142,10 +142,10 @@ static inline void arch_decomp_setup(void)
        int i = 0;
        const u32* usarts;
 
-       usarts = decomp_soc_detect(AT91_BASE_DBGU0);
+       usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0);
 
        if (!usarts)
-               usarts = decomp_soc_detect(AT91_BASE_DBGU1);
+               usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1);
        if (!usarts) {
                at91_uart = NULL;
                return;
index 944bffb..e6f52de 100644 (file)
@@ -73,7 +73,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
 {
        struct map_desc *desc = &sram_desc[bank];
 
-       desc->virtual = AT91_IO_VIRT_BASE - length;
+       desc->virtual = (unsigned long)AT91_IO_VIRT_BASE - length;
        if (bank > 0)
                desc->virtual -= sram_desc[bank - 1].length;
 
@@ -88,7 +88,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
 }
 
 static struct map_desc at91_io_desc __initdata = {
-       .virtual        = AT91_VA_BASE_SYS,
+       .virtual        = (unsigned long)AT91_VA_BASE_SYS,
        .pfn            = __phys_to_pfn(AT91_BASE_SYS),
        .length         = SZ_16K,
        .type           = MT_DEVICE,
index 45c97b1..c18a504 100644 (file)
@@ -29,7 +29,6 @@
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/mach/time.h>
-#include <asm/pmu.h>
 
 #include <asm/mach/arch.h>
 #include <mach/dma.h>
@@ -38,7 +37,7 @@
 #include <mach/csp/chipcHw_def.h>
 #include <mach/csp/chipcHw_inline.h>
 
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
 
 #include "core.h"
 
@@ -116,7 +115,7 @@ static struct resource pmu_resource = {
 
 static struct platform_device pmu_device = {
        .name           = "arm-pmu",
-       .id             = ARM_PMU_DEVICE_CPU,
+       .id             = -1,
        .resource       = &pmu_resource,
        .num_resources  = 1,
 };
index adbfb19..4b50228 100644 (file)
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
 
 #include "clock.h"
 
-#include <csp/secHw.h>
 #include <mach/csp/secHw_def.h>
 #include <mach/csp/chipcHw_inline.h>
 #include <mach/csp/tmrHw_reg.h>
index 96273ff..5050833 100644 (file)
 
 /* ---- Include Files ---------------------------------------------------- */
 
-#include <csp/errno.h>
-#include <csp/stdint.h>
-#include <csp/module.h>
+#include <linux/errno.h>
+#include <linux/types.h>
+#include <linux/export.h>
 
 #include <mach/csp/chipcHw_def.h>
 #include <mach/csp/chipcHw_inline.h>
 
-#include <csp/reg.h>
-#include <csp/delay.h>
+#include <mach/csp/reg.h>
+#include <linux/delay.h>
 
 /* ---- Private Constants and Types --------------------------------------- */
 
@@ -61,21 +61,21 @@ static int chipcHw_divide(int num, int denom)
 /****************************************************************************/
 chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock   /*  [ IN ] Configurable clock */
     ) {
-       volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
-       volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
-       volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
+       uint32_t __iomem *pPLLReg = NULL;
+       uint32_t __iomem *pClockCtrl = NULL;
+       uint32_t __iomem *pDependentClock = NULL;
        uint32_t vcoFreqPll1Hz = 0;     /* Effective VCO frequency for PLL1 in Hz */
        uint32_t vcoFreqPll2Hz = 0;     /* Effective VCO frequency for PLL2 in Hz */
        uint32_t dependentClockType = 0;
        uint32_t vcoHz = 0;
 
        /* Get VCO frequencies */
-       if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
+       if ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
                uint64_t adjustFreq = 0;
 
                vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                   ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                   ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
 
                /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
@@ -86,13 +86,13 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock        /*  [ IN ] Configur
        } else {
                vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                   ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                   ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
        }
        vcoFreqPll2Hz =
            chipcHw_XTAL_FREQ_Hz *
                 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-           ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+           ((readl(&pChipcHw->PLLPreDivider2) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
             chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
 
        switch (clock) {
@@ -187,51 +187,51 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock      /*  [ IN ] Configur
 
        if (pPLLReg) {
                /* Obtain PLL clock frequency */
-               if (*pPLLReg & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
+               if (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
                        /* Return crystal clock frequency when bypassed */
                        return chipcHw_XTAL_FREQ_Hz;
                } else if (clock == chipcHw_CLOCK_DDR) {
                        /* DDR frequency is configured in PLLDivider register */
-                       return chipcHw_divide (vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
+                       return chipcHw_divide (vcoHz, (((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) ? ((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) : 256));
                } else {
                        /* From chip revision number B0, LCD clock is internally divided by 2 */
                        if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
                                vcoHz >>= 1;
                        }
                        /* Obtain PLL clock frequency using VCO dividers */
-                       return chipcHw_divide(vcoHz, ((*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
+                       return chipcHw_divide(vcoHz, ((readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ?  (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
                }
        } else if (pClockCtrl) {
                /* Obtain divider clock frequency */
                uint32_t div;
                uint32_t freq = 0;
 
-               if (*pClockCtrl & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
+               if (readl(pClockCtrl) & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
                        /* Return crystal clock frequency when bypassed */
                        return chipcHw_XTAL_FREQ_Hz;
                } else if (pDependentClock) {
                        /* Identify the dependent clock frequency */
                        switch (dependentClockType) {
                        case PLL_CLOCK:
-                               if (*pDependentClock & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
+                               if (readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
                                        /* Use crystal clock frequency when dependent PLL clock is bypassed */
                                        freq = chipcHw_XTAL_FREQ_Hz;
                                } else {
                                        /* Obtain PLL clock frequency using VCO dividers */
-                                       div = *pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK;
+                                       div = readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_MDIV_MASK;
                                        freq = div ? chipcHw_divide(vcoHz, div) : 0;
                                }
                                break;
                        case NON_PLL_CLOCK:
-                               if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) {
+                               if (pDependentClock == &pChipcHw->ACLKClock) {
                                        freq = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
                                } else {
-                                       if (*pDependentClock & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
+                                       if (readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
                                                /* Use crystal clock frequency when dependent divider clock is bypassed */
                                                freq = chipcHw_XTAL_FREQ_Hz;
                                        } else {
                                                /* Obtain divider clock frequency using XTAL dividers */
-                                               div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK;
+                                               div = readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_DIV_MASK;
                                                freq = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, (div ? div : 256));
                                        }
                                }
@@ -242,7 +242,7 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock        /*  [ IN ] Configur
                        freq = chipcHw_XTAL_FREQ_Hz;
                }
 
-               div = *pClockCtrl & chipcHw_REG_DIV_CLOCK_DIV_MASK;
+               div = readl(pClockCtrl) & chipcHw_REG_DIV_CLOCK_DIV_MASK;
                return chipcHw_divide(freq, (div ? div : 256));
        }
        return 0;
@@ -261,9 +261,9 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock        /*  [ IN ] Configur
 chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,  /*  [ IN ] Configurable clock */
                                       uint32_t freq    /*  [ IN ] Clock frequency in Hz */
     ) {
-       volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
-       volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
-       volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
+       uint32_t __iomem *pPLLReg = NULL;
+       uint32_t __iomem *pClockCtrl = NULL;
+       uint32_t __iomem *pDependentClock = NULL;
        uint32_t vcoFreqPll1Hz = 0;     /* Effective VCO frequency for PLL1 in Hz */
        uint32_t desVcoFreqPll1Hz = 0;  /* Desired VCO frequency for PLL1 in Hz */
        uint32_t vcoFreqPll2Hz = 0;     /* Effective VCO frequency for PLL2 in Hz */
@@ -272,12 +272,12 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,     /*  [ IN ] Configu
        uint32_t desVcoHz = 0;
 
        /* Get VCO frequencies */
-       if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
+       if ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
                uint64_t adjustFreq = 0;
 
                vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                   ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                   ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
 
                /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
@@ -289,16 +289,16 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,     /*  [ IN ] Configu
                /* Desired VCO frequency */
                desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                   (((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                   (((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
                      chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) + 1);
        } else {
                vcoFreqPll1Hz = desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-                   ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                   ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
        }
        vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-           ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+           ((readl(&pChipcHw->PLLPreDivider2) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
             chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
 
        switch (clock) {
@@ -307,8 +307,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,       /*  [ IN ] Configu
                {
                        REG_LOCAL_IRQ_SAVE;
                        /* Dvide DDR_phy by two to obtain DDR_ctrl clock */
-                       pChipcHw->DDRClock = (pChipcHw->DDRClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
-                               << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
+                       writel((readl(&pChipcHw->DDRClock) & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT), &pChipcHw->DDRClock);
                        REG_LOCAL_IRQ_RESTORE;
                }
                pPLLReg = &pChipcHw->DDRClock;
@@ -329,8 +328,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,       /*  [ IN ] Configu
                /* Configure the VPM:BUS ratio settings */
                {
                        REG_LOCAL_IRQ_SAVE;
-                       pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
-                               << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
+                       writel((readl(&pChipcHw->VPMClock) & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT), &pChipcHw->VPMClock);
                        REG_LOCAL_IRQ_RESTORE;
                }
                pPLLReg = &pChipcHw->VPMClock;
@@ -428,9 +426,9 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,       /*  [ IN ] Configu
                /* For DDR settings use only the PLL divider clock */
                if (pPLLReg == &pChipcHw->DDRClock) {
                        /* Set M1DIV for PLL1, which controls the DDR clock */
-                       reg32_write(&pChipcHw->PLLDivider, (pChipcHw->PLLDivider & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24));
+                       reg32_write(&pChipcHw->PLLDivider, (readl(&pChipcHw->PLLDivider) & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24));
                        /* Calculate expected frequency */
-                       freq = chipcHw_divide(vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
+                       freq = chipcHw_divide(vcoHz, (((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) ? ((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) : 256));
                } else {
                        /* From chip revision number B0, LCD clock is internally divided by 2 */
                        if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
@@ -441,7 +439,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,       /*  [ IN ] Configu
                        reg32_modify_and(pPLLReg, ~(chipcHw_REG_PLL_CLOCK_MDIV_MASK));
                        reg32_modify_or(pPLLReg, chipcHw_REG_PLL_DIVIDER_MDIV(desVcoHz, freq));
                        /* Calculate expected frequency */
-                       freq = chipcHw_divide(vcoHz, ((*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
+                       freq = chipcHw_divide(vcoHz, ((readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
                }
                /* Wait for for atleast 200ns as per the protocol to change frequency */
                udelay(1);
@@ -460,16 +458,16 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,     /*  [ IN ] Configu
                if (pDependentClock) {
                        switch (dependentClockType) {
                        case PLL_CLOCK:
-                               divider = chipcHw_divide(chipcHw_divide (desVcoHz, (*pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq);
+                               divider = chipcHw_divide(chipcHw_divide (desVcoHz, (readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq);
                                break;
                        case NON_PLL_CLOCK:
                                {
                                        uint32_t sourceClock = 0;
 
-                                       if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) {
+                                       if (pDependentClock == &pChipcHw->ACLKClock) {
                                                sourceClock = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
                                        } else {
-                                               uint32_t div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK;
+                                               uint32_t div = readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_DIV_MASK;
                                                sourceClock = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, ((div) ? div : 256));
                                        }
                                        divider = chipcHw_divide(sourceClock, freq);
@@ -483,7 +481,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,       /*  [ IN ] Configu
                if (divider) {
                        REG_LOCAL_IRQ_SAVE;
                        /* Set the divider to obtain the required frequency */
-                       *pClockCtrl = (*pClockCtrl & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK);
+                       writel((readl(pClockCtrl) & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK), pClockCtrl);
                        REG_LOCAL_IRQ_RESTORE;
                        return freq;
                }
@@ -515,25 +513,26 @@ static int vpmPhaseAlignA0(void)
        int count = 0;
 
        for (iter = 0; (iter < MAX_PHASE_ALIGN_ATTEMPTS) && (adjustCount < MAX_PHASE_ADJUST_COUNT); iter++) {
-               phaseControl = (pChipcHw->VPMClock & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT;
+               phaseControl = (readl(&pChipcHw->VPMClock) & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT;
                phaseValue = 0;
                prevPhaseComp = 0;
 
                /* Step 1: Look for falling PH_COMP transition */
 
                /* Read the contents of VPM Clock resgister */
-               phaseValue = pChipcHw->VPMClock;
+               phaseValue = readl(&pChipcHw->VPMClock);
                do {
                        /* Store previous value of phase comparator */
                        prevPhaseComp = phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP;
                        /* Change the value of PH_CTRL. */
-                       reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                       reg32_write(&pChipcHw->VPMClock,
+                       (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
                        /* Wait atleast 20 ns */
                        udelay(1);
                        /* Toggle the LOAD_CH after phase control is written. */
-                       pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+                       writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
                        /* Read the contents of  VPM Clock resgister. */
-                       phaseValue = pChipcHw->VPMClock;
+                       phaseValue = readl(&pChipcHw->VPMClock);
 
                        if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
                                phaseControl = (0x3F & (phaseControl - 1));
@@ -557,12 +556,13 @@ static int vpmPhaseAlignA0(void)
 
                for (count = 0; (count < 5) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
                        phaseControl = (0x3F & (phaseControl + 1));
-                       reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                       reg32_write(&pChipcHw->VPMClock,
+                       (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
                        /* Wait atleast 20 ns */
                        udelay(1);
                        /* Toggle the LOAD_CH after phase control is written. */
-                       pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-                       phaseValue = pChipcHw->VPMClock;
+                       writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
+                       phaseValue = readl(&pChipcHw->VPMClock);
                        /* Count number of adjustment made */
                        adjustCount++;
                }
@@ -581,12 +581,13 @@ static int vpmPhaseAlignA0(void)
 
                for (count = 0; (count < 3) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
                        phaseControl = (0x3F & (phaseControl - 1));
-                       reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                       reg32_write(&pChipcHw->VPMClock,
+                       (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
                        /* Wait atleast 20 ns */
                        udelay(1);
                        /* Toggle the LOAD_CH after phase control is written. */
-                       pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-                       phaseValue = pChipcHw->VPMClock;
+                       writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
+                       phaseValue = readl(&pChipcHw->VPMClock);
                        /* Count number of adjustment made */
                        adjustCount++;
                }
@@ -605,12 +606,13 @@ static int vpmPhaseAlignA0(void)
 
                for (count = 0; (count < 5); count++) {
                        phaseControl = (0x3F & (phaseControl - 1));
-                       reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                       reg32_write(&pChipcHw->VPMClock,
+                       (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
                        /* Wait atleast 20 ns */
                        udelay(1);
                        /* Toggle the LOAD_CH after phase control is written. */
-                       pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-                       phaseValue = pChipcHw->VPMClock;
+                       writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
+                       phaseValue = readl(&pChipcHw->VPMClock);
                        /* Count number of adjustment made */
                        adjustCount++;
                }
@@ -631,14 +633,14 @@ static int vpmPhaseAlignA0(void)
                        /* Store previous value of phase comparator */
                        prevPhaseComp = phaseValue;
                        /* Change the value of PH_CTRL. */
-                       reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                       reg32_write(&pChipcHw->VPMClock,
+                       (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
                        /* Wait atleast 20 ns */
                        udelay(1);
                        /* Toggle the LOAD_CH after phase control is written. */
-                       pChipcHw->VPMClock ^=
-                           chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+                       writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
                        /* Read the contents of  VPM Clock resgister. */
-                       phaseValue = pChipcHw->VPMClock;
+                       phaseValue = readl(&pChipcHw->VPMClock);
 
                        if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
                                phaseControl = (0x3F & (phaseControl - 1));
@@ -661,13 +663,13 @@ static int vpmPhaseAlignA0(void)
        }
 
        /* For VPM Phase should be perfectly aligned. */
-       phaseControl = (((pChipcHw->VPMClock >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F);
+       phaseControl = (((readl(&pChipcHw->VPMClock) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F);
        {
                REG_LOCAL_IRQ_SAVE;
 
-               pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT);
+               writel((readl(&pChipcHw->VPMClock) & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT), &pChipcHw->VPMClock);
                /* Load new phase value */
-               pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+               writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
 
                REG_LOCAL_IRQ_RESTORE;
        }
@@ -697,7 +699,7 @@ int chipcHw_vpmPhaseAlign(void)
                int adjustCount = 0;
 
                /* Disable VPM access */
-               pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
+               writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1);
                /* Disable HW VPM phase alignment  */
                chipcHw_vpmHwPhaseAlignDisable();
                /* Enable SW VPM phase alignment  */
@@ -715,23 +717,24 @@ int chipcHw_vpmPhaseAlign(void)
                                phaseControl--;
                        } else {
                                /* Enable VPM access */
-                               pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
+                               writel(readl(&pChipcHw->Spare1) | chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1);
                                /* Return adjust count */
                                return adjustCount;
                        }
                        /* Change the value of PH_CTRL. */
-                       reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                       reg32_write(&pChipcHw->VPMClock,
+                       (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
                        /* Wait atleast 20 ns */
                        udelay(1);
                        /* Toggle the LOAD_CH after phase control is written. */
-                       pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+                       writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
                        /* Count adjustment */
                        adjustCount++;
                }
        }
 
        /* Disable VPM access */
-       pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
+       writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1);
        return -1;
 }
 
index 367df75..8377d80 100644 (file)
 
 /* ---- Include Files ---------------------------------------------------- */
 
-#include <csp/errno.h>
-#include <csp/stdint.h>
-#include <csp/module.h>
+#include <linux/errno.h>
+#include <linux/types.h>
+#include <linux/export.h>
 
 #include <mach/csp/chipcHw_def.h>
 #include <mach/csp/chipcHw_inline.h>
 
-#include <csp/reg.h>
-#include <csp/delay.h>
+#include <mach/csp/reg.h>
+#include <linux/delay.h>
 /* ---- Private Constants and Types --------------------------------------- */
 
 /*
@@ -73,9 +73,9 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz)
 
        {
                REG_LOCAL_IRQ_SAVE;
-               pChipcHw->PLLConfig2 =
-                   chipcHw_REG_PLL_CONFIG_D_RESET |
-                   chipcHw_REG_PLL_CONFIG_A_RESET;
+               writel(chipcHw_REG_PLL_CONFIG_D_RESET |
+                      chipcHw_REG_PLL_CONFIG_A_RESET,
+                       &pChipcHw->PLLConfig2);
 
                pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
                    chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
@@ -87,28 +87,30 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz)
                     chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
 
                /* Enable CHIPC registers to control the PLL */
-               pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
+               writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus);
 
                /* Set pre divider to get desired VCO frequency */
-               pChipcHw->PLLPreDivider2 = pllPreDivider2;
+               writel(pllPreDivider2, &pChipcHw->PLLPreDivider2);
                /* Set NDIV Frac */
-               pChipcHw->PLLDivider2 = chipcHw_REG_PLL_DIVIDER_NDIV_f;
+               writel(chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider2);
 
                /* This has to be removed once the default values are fixed for PLL2. */
-               pChipcHw->PLLControl12 = 0x38000700;
-               pChipcHw->PLLControl22 = 0x00000015;
+               writel(0x38000700, &pChipcHw->PLLControl12);
+               writel(0x00000015, &pChipcHw->PLLControl22);
 
                /* Reset PLL2 */
                if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
-                       pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
+                       writel(chipcHw_REG_PLL_CONFIG_D_RESET |
                            chipcHw_REG_PLL_CONFIG_A_RESET |
                            chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
-                           chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+                           chipcHw_REG_PLL_CONFIG_POWER_DOWN,
+                           &pChipcHw->PLLConfig2);
                } else {
-                       pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
+                       writel(chipcHw_REG_PLL_CONFIG_D_RESET |
                            chipcHw_REG_PLL_CONFIG_A_RESET |
                            chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
-                           chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+                           chipcHw_REG_PLL_CONFIG_POWER_DOWN,
+                           &pChipcHw->PLLConfig2);
                }
                REG_LOCAL_IRQ_RESTORE;
        }
@@ -119,22 +121,25 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz)
        {
                REG_LOCAL_IRQ_SAVE;
                /* Remove analog reset and Power on the PLL */
-               pChipcHw->PLLConfig2 &=
+               writel(readl(&pChipcHw->PLLConfig2) &
                    ~(chipcHw_REG_PLL_CONFIG_A_RESET |
-                     chipcHw_REG_PLL_CONFIG_POWER_DOWN);
+                     chipcHw_REG_PLL_CONFIG_POWER_DOWN),
+                     &pChipcHw->PLLConfig2);
 
                REG_LOCAL_IRQ_RESTORE;
 
        }
 
        /* Wait until PLL is locked */
-       while (!(pChipcHw->PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
+       while (!(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED))
                ;
 
        {
                REG_LOCAL_IRQ_SAVE;
                /* Remove digital reset */
-               pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
+               writel(readl(&pChipcHw->PLLConfig2) &
+                       ~chipcHw_REG_PLL_CONFIG_D_RESET,
+                       &pChipcHw->PLLConfig2);
 
                REG_LOCAL_IRQ_RESTORE;
        }
@@ -157,9 +162,9 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
        {
                REG_LOCAL_IRQ_SAVE;
 
-               pChipcHw->PLLConfig =
-                   chipcHw_REG_PLL_CONFIG_D_RESET |
-                   chipcHw_REG_PLL_CONFIG_A_RESET;
+               writel(chipcHw_REG_PLL_CONFIG_D_RESET |
+                   chipcHw_REG_PLL_CONFIG_A_RESET,
+                   &pChipcHw->PLLConfig);
                /* Setting VCO frequency */
                if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
                        pllPreDivider =
@@ -182,30 +187,22 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
                }
 
                /* Enable CHIPC registers to control the PLL */
-               pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
+               writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus);
 
                /* Set pre divider to get desired VCO frequency */
-               pChipcHw->PLLPreDivider = pllPreDivider;
+               writel(pllPreDivider, &pChipcHw->PLLPreDivider);
                /* Set NDIV Frac */
                if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
-                       pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
-                           chipcHw_REG_PLL_DIVIDER_NDIV_f_SS;
+                       writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f_SS, &pChipcHw->PLLDivider);
                } else {
-                       pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
-                           chipcHw_REG_PLL_DIVIDER_NDIV_f;
+                       writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider);
                }
 
                /* Reset PLL1 */
                if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
-                       pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
-                           chipcHw_REG_PLL_CONFIG_A_RESET |
-                           chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
-                           chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+                       writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig);
                } else {
-                       pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
-                           chipcHw_REG_PLL_CONFIG_A_RESET |
-                           chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
-                           chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+                       writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_800_1600 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig);
                }
 
                REG_LOCAL_IRQ_RESTORE;
@@ -216,22 +213,19 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
                {
                        REG_LOCAL_IRQ_SAVE;
                        /* Remove analog reset and Power on the PLL */
-                       pChipcHw->PLLConfig &=
-                           ~(chipcHw_REG_PLL_CONFIG_A_RESET |
-                             chipcHw_REG_PLL_CONFIG_POWER_DOWN);
+                       writel(readl(&pChipcHw->PLLConfig) & ~(chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_POWER_DOWN), &pChipcHw->PLLConfig);
                        REG_LOCAL_IRQ_RESTORE;
                }
 
                /* Wait until PLL is locked */
-               while (!(pChipcHw->PLLStatus & chipcHw_REG_PLL_STATUS_LOCKED)
-                      || !(pChipcHw->
-                           PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
+               while (!(readl(&pChipcHw->PLLStatus) & chipcHw_REG_PLL_STATUS_LOCKED)
+                      || !(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED))
                        ;
 
                /* Remove digital reset */
                {
                        REG_LOCAL_IRQ_SAVE;
-                       pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
+                       writel(readl(&pChipcHw->PLLConfig) & ~chipcHw_REG_PLL_CONFIG_D_RESET, &pChipcHw->PLLConfig);
                        REG_LOCAL_IRQ_RESTORE;
                }
        }
@@ -267,11 +261,7 @@ void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam  /*  [ IN ] Misc chip initializ
        chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET);
 
        /* Before configuring the ARM clock, atleast we need to make sure BUS clock maintains the proper ratio with ARM clock */
-       pChipcHw->ACLKClock =
-           (pChipcHw->
-            ACLKClock & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam->
-                                                                armBusRatio &
-                                                                chipcHw_REG_ACLKClock_CLK_DIV_MASK);
+       writel((readl(&pChipcHw->ACLKClock) & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam-> armBusRatio & chipcHw_REG_ACLKClock_CLK_DIV_MASK), &pChipcHw->ACLKClock);
 
        /* Set various core component frequencies. The order in which this is done is important for some. */
        /* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the ARM, and VPM needs to know BUS */
index 2671d88..f95ce91 100644 (file)
 *****************************************************************************/
 
 /* ---- Include Files ---------------------------------------------------- */
-#include <csp/stdint.h>
+#include <linux/types.h>
 #include <mach/csp/chipcHw_def.h>
 #include <mach/csp/chipcHw_inline.h>
-#include <csp/intcHw.h>
-#include <csp/cache.h>
+#include <mach/csp/intcHw_reg.h>
+#include <asm/cacheflush.h>
 
 /* ---- Private Constants and Types --------------------------------------- */
 /* ---- Private Variables ------------------------------------------------- */
@@ -50,17 +50,18 @@ void chipcHw_reset(uint32_t mask)
                        chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
                }
                /* Bypass the PLL clocks before reboot */
-               pChipcHw->UARTClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
-               pChipcHw->SPIClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
+               writel(readl(&pChipcHw->UARTClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT,
+                       &pChipcHw->UARTClock);
+               writel(readl(&pChipcHw->SPIClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT,
+                       &pChipcHw->SPIClock);
 
                /* Copy the chipcHw_warmReset_run_from_aram function into ARAM */
                do {
-                       ((uint32_t *) MM_IO_BASE_ARAM)[i] =
-                           ((uint32_t *) &chipcHw_reset_run_from_aram)[i];
+                       writel(((uint32_t *) &chipcHw_reset_run_from_aram)[i], ((uint32_t __iomem *) MM_IO_BASE_ARAM) + i);
                        i++;
-               } while (((uint32_t *) MM_IO_BASE_ARAM)[i - 1] != 0xe1a0f00f);  /* 0xe1a0f00f == asm ("mov r15, r15"); */
+               } while (readl(((uint32_t __iomem*) MM_IO_BASE_ARAM) + i - 1) != 0xe1a0f00f);   /* 0xe1a0f00f == asm ("mov r15, r15"); */
 
-               CSP_CACHE_FLUSH_ALL;
+               flush_cache_all();
 
                /* run the function from ARAM */
                runFunc();
index 6b9be2e..547f746 100644 (file)
 /****************************************************************************/
 
 /* ---- Include Files ---------------------------------------------------- */
-#include <csp/stdint.h>
-#include <csp/string.h>
-#include <stddef.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/stddef.h>
 
-#include <csp/dmacHw.h>
+#include <mach/csp/dmacHw.h>
 #include <mach/csp/dmacHw_reg.h>
 #include <mach/csp/dmacHw_priv.h>
 #include <mach/csp/chipcHw_inline.h>
@@ -55,33 +55,32 @@ static uint32_t GetFifoSize(dmacHw_HANDLE_t handle  /*   [ IN ] DMA Channel handl
     ) {
        uint32_t val = 0;
        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-       dmacHw_MISC_t *pMiscReg =
-           (dmacHw_MISC_t *) dmacHw_REG_MISC_BASE(pCblk->module);
+       dmacHw_MISC_t __iomem *pMiscReg = (void __iomem *)dmacHw_REG_MISC_BASE(pCblk->module);
 
        switch (pCblk->channel) {
        case 0:
-               val = (pMiscReg->CompParm2.lo & 0x70000000) >> 28;
+               val = (readl(&pMiscReg->CompParm2.lo) & 0x70000000) >> 28;
                break;
        case 1:
-               val = (pMiscReg->CompParm3.hi & 0x70000000) >> 28;
+               val = (readl(&pMiscReg->CompParm3.hi) & 0x70000000) >> 28;
                break;
        case 2:
-               val = (pMiscReg->CompParm3.lo & 0x70000000) >> 28;
+               val = (readl(&pMiscReg->CompParm3.lo) & 0x70000000) >> 28;
                break;
        case 3:
-               val = (pMiscReg->CompParm4.hi & 0x70000000) >> 28;
+               val = (readl(&pMiscReg->CompParm4.hi) & 0x70000000) >> 28;
                break;
        case 4:
-               val = (pMiscReg->CompParm4.lo & 0x70000000) >> 28;
+               val = (readl(&pMiscReg->CompParm4.lo) & 0x70000000) >> 28;
                break;
        case 5:
-               val = (pMiscReg->CompParm5.hi & 0x70000000) >> 28;
+               val = (readl(&pMiscReg->CompParm5.hi) & 0x70000000) >> 28;
                break;
        case 6:
-               val = (pMiscReg->CompParm5.lo & 0x70000000) >> 28;
+               val = (readl(&pMiscReg->CompParm5.lo) & 0x70000000) >> 28;
                break;
        case 7:
-               val = (pMiscReg->CompParm6.hi & 0x70000000) >> 28;
+               val = (readl(&pMiscReg->CompParm6.hi) & 0x70000000) >> 28;
                break;
        }
 
index a1f3283..fe43869 100644 (file)
 
 /* ---- Include Files ---------------------------------------------------- */
 
-#include <csp/stdint.h>
-#include <stddef.h>
+#include <linux/types.h>
+#include <linux/stddef.h>
 
-#include <csp/dmacHw.h>
+#include <mach/csp/dmacHw.h>
 #include <mach/csp/dmacHw_reg.h>
 #include <mach/csp/dmacHw_priv.h>
 
index 16225e4..dc4137f 100644 (file)
 
 /* ---- Include Files ---------------------------------------------------- */
 
-#include <csp/errno.h>
-#include <csp/stdint.h>
+#include <linux/errno.h>
+#include <linux/types.h>
 
-#include <csp/tmrHw.h>
+#include <mach/csp/tmrHw.h>
 #include <mach/csp/tmrHw_reg.h>
 
 #define tmrHw_ASSERT(a)                     if (!(a)) *(char *)0 = 0
diff --git a/arch/arm/mach-bcmring/include/cfg_global.h b/arch/arm/mach-bcmring/include/cfg_global.h
deleted file mode 100644 (file)
index f01da87..0000000
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _CFG_GLOBAL_H_
-#define _CFG_GLOBAL_H_
-
-#include <cfg_global_defines.h>
-
-#define CFG_GLOBAL_CHIP                         BCM11107
-#define CFG_GLOBAL_CHIP_FAMILY                  CFG_GLOBAL_CHIP_FAMILY_BCMRING
-#define CFG_GLOBAL_CHIP_REV                     0xB0
-#define CFG_GLOBAL_RAM_SIZE                     0x10000000
-#define CFG_GLOBAL_RAM_BASE                     0x00000000
-#define CFG_GLOBAL_RAM_RESERVED_SIZE            0x000000
-
-#endif /* _CFG_GLOBAL_H_ */
diff --git a/arch/arm/mach-bcmring/include/csp/cache.h b/arch/arm/mach-bcmring/include/csp/cache.h
deleted file mode 100644 (file)
index caa20e5..0000000
+++ /dev/null
@@ -1,35 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CSP_CACHE_H
-#define CSP_CACHE_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#include <csp/stdint.h>
-
-/* ---- Public Constants and Types --------------------------------------- */
-
-#if defined(__KERNEL__) && !defined(STANDALONE)
-#include <asm/cacheflush.h>
-
-#define CSP_CACHE_FLUSH_ALL      flush_cache_all()
-
-#else
-
-#define CSP_CACHE_FLUSH_ALL
-
-#endif
-
-#endif /* CSP_CACHE_H */
diff --git a/arch/arm/mach-bcmring/include/csp/delay.h b/arch/arm/mach-bcmring/include/csp/delay.h
deleted file mode 100644 (file)
index 8b3d803..0000000
+++ /dev/null
@@ -1,36 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-#ifndef CSP_DELAY_H
-#define CSP_DELAY_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-/* Some CSP routines require use of the following delay routines. Use the OS */
-/* version if available, otherwise use a CSP specific definition. */
-/* void udelay(unsigned long usecs); */
-/* void mdelay(unsigned long msecs); */
-
-#if defined(__KERNEL__) && !defined(STANDALONE)
-   #include <linux/delay.h>
-#else
-   #include <mach/csp/delay.h>
-#endif
-
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-#endif /*  CSP_DELAY_H */
diff --git a/arch/arm/mach-bcmring/include/csp/errno.h b/arch/arm/mach-bcmring/include/csp/errno.h
deleted file mode 100644 (file)
index 51357dd..0000000
+++ /dev/null
@@ -1,32 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CSP_ERRNO_H
-#define CSP_ERRNO_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#if   defined(__KERNEL__)
-#include <linux/errno.h>
-#elif defined(CSP_SIMULATION)
-#include <asm-generic/errno.h>
-#else
-#include <errno.h>
-#endif
-
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-#endif /* CSP_ERRNO_H */
diff --git a/arch/arm/mach-bcmring/include/csp/intcHw.h b/arch/arm/mach-bcmring/include/csp/intcHw.h
deleted file mode 100644 (file)
index 1c639c8..0000000
+++ /dev/null
@@ -1,40 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-/****************************************************************************/
-/**
-*  @file    intcHw.h
-*
-*  @brief   generic interrupt controller API
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef _INTCHW_H
-#define _INTCHW_H
-
-/* ---- Include Files ---------------------------------------------------- */
-#include <mach/csp/intcHw_reg.h>
-
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-static inline void intcHw_irq_disable(void *basep, uint32_t mask);
-static inline void intcHw_irq_enable(void *basep, uint32_t mask);
-
-#endif /* _INTCHW_H */
-
diff --git a/arch/arm/mach-bcmring/include/csp/module.h b/arch/arm/mach-bcmring/include/csp/module.h
deleted file mode 100644 (file)
index c30d2a5..0000000
+++ /dev/null
@@ -1,32 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-#ifndef CSP_MODULE_H
-#define CSP_MODULE_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#ifdef __KERNEL__
-    #include <linux/module.h>
-#else
-    #define EXPORT_SYMBOL(symbol)
-#endif
-
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-
-#endif /* CSP_MODULE_H */
diff --git a/arch/arm/mach-bcmring/include/csp/secHw.h b/arch/arm/mach-bcmring/include/csp/secHw.h
deleted file mode 100644 (file)
index b9d7e07..0000000
+++ /dev/null
@@ -1,65 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    secHw.h
-*
-*  @brief   Definitions for accessing low level security features
-*
-*/
-/****************************************************************************/
-#ifndef SECHW_H
-#define SECHW_H
-
-typedef void (*secHw_FUNC_t) (void);
-
-typedef enum {
-       secHw_MODE_SECURE = 0x0,        /* Switches processor into secure mode */
-       secHw_MODE_NONSECURE = 0x1      /* Switches processor into non-secure mode */
-} secHw_MODE;
-
-/****************************************************************************/
-/**
-*  @brief   Requesting to execute the function in secure mode
-*
-*  This function requests the given function to run in secure mode
-*
-*/
-/****************************************************************************/
-void secHw_RunSecure(secHw_FUNC_t      /* Function to run in secure mode */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Sets the  mode
-*
-*  his function sets the processor mode (secure/non-secure)
-*
-*/
-/****************************************************************************/
-void secHw_SetMode(secHw_MODE  /* Processor mode */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Get the current mode
-*
-*  This function retieves the processor mode (secure/non-secure)
-*
-*/
-/****************************************************************************/
-void secHw_GetMode(secHw_MODE *);
-
-#endif /* SECHW_H */
diff --git a/arch/arm/mach-bcmring/include/csp/stdint.h b/arch/arm/mach-bcmring/include/csp/stdint.h
deleted file mode 100644 (file)
index 3a8718b..0000000
+++ /dev/null
@@ -1,30 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CSP_STDINT_H
-#define CSP_STDINT_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#ifdef __KERNEL__
-#include <linux/types.h>
-#else
-#include <stdint.h>
-#endif
-
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-#endif /* CSP_STDINT_H */
diff --git a/arch/arm/mach-bcmring/include/csp/string.h b/arch/arm/mach-bcmring/include/csp/string.h
deleted file mode 100644 (file)
index ad9e400..0000000
+++ /dev/null
@@ -1,34 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-
-#ifndef CSP_STRING_H
-#define CSP_STRING_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#ifdef __KERNEL__
-   #include <linux/string.h>
-#else
-   #include <string.h>
-#endif
-
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-
-#endif /* CSP_STRING_H */
-
 
 #define IMAGE_HEADER_SIZE_CHECKSUM    4
 #endif
+#ifndef _CFG_GLOBAL_H_
+#define _CFG_GLOBAL_H_
+
+#define CFG_GLOBAL_CHIP                         BCM11107
+#define CFG_GLOBAL_CHIP_FAMILY                  CFG_GLOBAL_CHIP_FAMILY_BCMRING
+#define CFG_GLOBAL_CHIP_REV                     0xB0
+#define CFG_GLOBAL_RAM_SIZE                     0x10000000
+#define CFG_GLOBAL_RAM_BASE                     0x00000000
+#define CFG_GLOBAL_RAM_RESERVED_SIZE            0x000000
+
+#endif /* _CFG_GLOBAL_H_ */
index 933ce68..0a89e0c 100644 (file)
@@ -17,7 +17,7 @@
 
 /* ---- Include Files ---------------------------------------------------- */
 #include <mach/csp/cap.h>
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
 
 /* ---- Public Constants and Types --------------------------------------- */
 #define CAP_CONFIG0_VPM_DIS          0x00000001
index 1619733..39f09cb 100644 (file)
@@ -17,9 +17,9 @@
 
 /* ---- Include Files ----------------------------------------------------- */
 
-#include <csp/stdint.h>
-#include <csp/errno.h>
-#include <csp/reg.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <mach/csp/reg.h>
 #include <mach/csp/chipcHw_reg.h>
 
 /* ---- Public Constants and Types ---------------------------------------- */
index 03238c2..a66f3f7 100644 (file)
@@ -17,8 +17,8 @@
 
 /* ---- Include Files ----------------------------------------------------- */
 
-#include <csp/errno.h>
-#include <csp/reg.h>
+#include <linux/errno.h>
+#include <mach/csp/reg.h>
 #include <mach/csp/chipcHw_reg.h>
 #include <mach/csp/chipcHw_def.h>
 
@@ -47,7 +47,7 @@ static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
 /****************************************************************************/
 static inline uint32_t chipcHw_getChipId(void)
 {
-       return pChipcHw->ChipId;
+       return readl(&pChipcHw->ChipId);
 }
 
 /****************************************************************************/
@@ -59,15 +59,16 @@ static inline uint32_t chipcHw_getChipId(void)
 /****************************************************************************/
 static inline void chipcHw_enableSpreadSpectrum(void)
 {
-       if ((pChipcHw->
-            PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) !=
+       if ((readl(&pChipcHw->
+            PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) !=
            chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
-               ddrcReg_PHY_ADDR_CTL_REGP->ssCfg =
-                   (0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) |
+               writel((0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) |
                    (ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK <<
-                    ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT);
-               ddrcReg_PHY_ADDR_CTL_REGP->ssCtl |=
-                   ddrcReg_PHY_ADDR_SS_CTRL_ENABLE;
+                    ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT),
+                    &ddrcReg_PHY_ADDR_CTL_REGP->ssCfg);
+               writel(readl(&ddrcReg_PHY_ADDR_CTL_REGP->ssCtl) |
+                   ddrcReg_PHY_ADDR_SS_CTRL_ENABLE,
+                   &ddrcReg_PHY_ADDR_CTL_REGP->ssCtl);
        }
 }
 
@@ -93,8 +94,8 @@ static inline void chipcHw_disableSpreadSpectrum(void)
 /****************************************************************************/
 static inline uint32_t chipcHw_getChipProductId(void)
 {
-       return (pChipcHw->
-                ChipId & chipcHw_REG_CHIPID_BASE_MASK) >>
+       return (readl(&pChipcHw->
+                ChipId) & chipcHw_REG_CHIPID_BASE_MASK) >>
                chipcHw_REG_CHIPID_BASE_SHIFT;
 }
 
@@ -109,7 +110,7 @@ static inline uint32_t chipcHw_getChipProductId(void)
 /****************************************************************************/
 static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void)
 {
-       return pChipcHw->ChipId & chipcHw_REG_CHIPID_REV_MASK;
+       return readl(&pChipcHw->ChipId) & chipcHw_REG_CHIPID_REV_MASK;
 }
 
 /****************************************************************************/
@@ -156,7 +157,7 @@ static inline void chipcHw_busInterfaceClockDisable(uint32_t mask)
 /****************************************************************************/
 static inline uint32_t chipcHw_getBusInterfaceClockStatus(void)
 {
-       return pChipcHw->BusIntfClock;
+       return readl(&pChipcHw->BusIntfClock);
 }
 
 /****************************************************************************/
@@ -215,8 +216,9 @@ static inline void chipcHw_softResetDisable(uint64_t mask)
 
        /* Deassert module soft reset */
        REG_LOCAL_IRQ_SAVE;
-       pChipcHw->SoftReset1 ^= ctrl1;
-       pChipcHw->SoftReset2 ^= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
+       writel(readl(&pChipcHw->SoftReset1) ^ ctrl1, &pChipcHw->SoftReset1);
+       writel(readl(&pChipcHw->SoftReset2) ^ (ctrl2 &
+               (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)), &pChipcHw->SoftReset2);
        REG_LOCAL_IRQ_RESTORE;
 }
 
@@ -227,9 +229,10 @@ static inline void chipcHw_softResetEnable(uint64_t mask)
        uint32_t unhold = 0;
 
        REG_LOCAL_IRQ_SAVE;
-       pChipcHw->SoftReset1 |= ctrl1;
+       writel(readl(&pChipcHw->SoftReset1) | ctrl1, &pChipcHw->SoftReset1);
        /* Mask out unhold request bits */
-       pChipcHw->SoftReset2 |= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
+       writel(readl(&pChipcHw->SoftReset2) | (ctrl2 &
+               (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)), &pChipcHw->SoftReset2);
 
        /* Process unhold requests */
        if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD) {
@@ -246,7 +249,7 @@ static inline void chipcHw_softResetEnable(uint64_t mask)
 
        if (unhold) {
                /* Make sure unhold request is effective */
-               pChipcHw->SoftReset1 &= ~unhold;
+               writel(readl(&pChipcHw->SoftReset1) & ~unhold, &pChipcHw->SoftReset1);
        }
        REG_LOCAL_IRQ_RESTORE;
 }
@@ -307,7 +310,7 @@ static inline void chipcHw_setOTPOption(uint64_t mask)
 /****************************************************************************/
 static inline uint32_t chipcHw_getStickyBits(void)
 {
-       return pChipcHw->Sticky;
+       return readl(&pChipcHw->Sticky);
 }
 
 /****************************************************************************/
@@ -328,7 +331,7 @@ static inline void chipcHw_setStickyBits(uint32_t mask)
                bits |= chipcHw_REG_STICKY_POR_BROM;
        } else {
                uint32_t sticky;
-               sticky = pChipcHw->Sticky;
+               sticky = readl(pChipcHw->Sticky);
 
                if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
                    && (sticky & chipcHw_REG_STICKY_BOOT_DONE) == 0) {
@@ -355,7 +358,7 @@ static inline void chipcHw_setStickyBits(uint32_t mask)
                        bits |= chipcHw_REG_STICKY_GENERAL_5;
                }
        }
-       pChipcHw->Sticky = bits;
+       writel(bits, pChipcHw->Sticky);
        REG_LOCAL_IRQ_RESTORE;
 }
 
@@ -377,7 +380,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask)
            (chipcHw_REG_STICKY_BOOT_DONE | chipcHw_REG_STICKY_GENERAL_1 |
             chipcHw_REG_STICKY_GENERAL_2 | chipcHw_REG_STICKY_GENERAL_3 |
             chipcHw_REG_STICKY_GENERAL_4 | chipcHw_REG_STICKY_GENERAL_5)) {
-               uint32_t sticky = pChipcHw->Sticky;
+               uint32_t sticky = readl(&pChipcHw->Sticky);
 
                if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
                    && (sticky & chipcHw_REG_STICKY_BOOT_DONE)) {
@@ -410,7 +413,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask)
                        mask &= ~chipcHw_REG_STICKY_GENERAL_5;
                }
        }
-       pChipcHw->Sticky = bits | mask;
+       writel(bits | mask, &pChipcHw->Sticky);
        REG_LOCAL_IRQ_RESTORE;
 }
 
@@ -426,7 +429,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask)
 /****************************************************************************/
 static inline uint32_t chipcHw_getSoftStraps(void)
 {
-       return pChipcHw->SoftStraps;
+       return readl(&pChipcHw->SoftStraps);
 }
 
 /****************************************************************************/
@@ -456,7 +459,7 @@ static inline void chipcHw_setSoftStraps(uint32_t strapOptions)
 /****************************************************************************/
 static inline uint32_t chipcHw_getPinStraps(void)
 {
-       return pChipcHw->PinStraps;
+       return readl(&pChipcHw->PinStraps);
 }
 
 /****************************************************************************/
@@ -671,9 +674,9 @@ static inline void chipcHw_selectGE3(void)
 /****************************************************************************/
 static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin)
 {
-       return (*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &
+       return (readl(chipcHw_REG_GPIO_MUX(pin))) &
                (chipcHw_REG_GPIO_MUX_MASK <<
-                chipcHw_REG_GPIO_MUX_POSITION(pin))) >>
+                chipcHw_REG_GPIO_MUX_POSITION(pin)) >>
            chipcHw_REG_GPIO_MUX_POSITION(pin);
 }
 
@@ -841,8 +844,8 @@ static inline void chipcHw_setUsbDevice(void)
 static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
                                    chipcHw_OPTYPE_e type, int mode)
 {
-       volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
-       volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
+       uint32_t __iomem *pPLLReg = NULL;
+       uint32_t __iomem *pClockCtrl = NULL;
 
        switch (clock) {
        case chipcHw_CLOCK_DDR:
@@ -1071,7 +1074,7 @@ static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock)
 /****************************************************************************/
 static inline int chipcHw_isSoftwareStrapsEnable(void)
 {
-       return pChipcHw->SoftStraps & 0x00000001;
+       return readl(&pChipcHw->SoftStraps) & 0x00000001;
 }
 
 /****************************************************************************/
@@ -1138,7 +1141,7 @@ static inline void chipcHw_pll2TestDisable(void)
 /****************************************************************************/
 static inline int chipcHw_isPllTestEnable(void)
 {
-       return pChipcHw->PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
+       return readl(&pChipcHw->PLLConfig) & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
 }
 
 /****************************************************************************/
@@ -1147,7 +1150,7 @@ static inline int chipcHw_isPllTestEnable(void)
 /****************************************************************************/
 static inline int chipcHw_isPll2TestEnable(void)
 {
-       return pChipcHw->PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
+       return readl(&pChipcHw->PLLConfig2) & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
 }
 
 /****************************************************************************/
@@ -1183,8 +1186,8 @@ static inline void chipcHw_pll2TestSelect(uint32_t val)
 /****************************************************************************/
 static inline uint8_t chipcHw_getPllTestSelected(void)
 {
-       return (uint8_t) ((pChipcHw->
-                          PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
+       return (uint8_t) ((readl(&pChipcHw->
+                          PLLConfig) & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
                          >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
 }
 
@@ -1194,8 +1197,8 @@ static inline uint8_t chipcHw_getPllTestSelected(void)
 /****************************************************************************/
 static inline uint8_t chipcHw_getPll2TestSelected(void)
 {
-       return (uint8_t) ((pChipcHw->
-                          PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
+       return (uint8_t) ((readl(&pChipcHw->
+                          PLLConfig2) & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
                          >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
 }
 
@@ -1208,7 +1211,8 @@ static inline uint8_t chipcHw_getPll2TestSelected(void)
 static inline void chipcHw_pll1Disable(void)
 {
        REG_LOCAL_IRQ_SAVE;
-       pChipcHw->PLLConfig |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+       writel(readl(&pChipcHw->PLLConfig) | chipcHw_REG_PLL_CONFIG_POWER_DOWN,
+               &pChipcHw->PLLConfig);
        REG_LOCAL_IRQ_RESTORE;
 }
 
@@ -1221,7 +1225,8 @@ static inline void chipcHw_pll1Disable(void)
 static inline void chipcHw_pll2Disable(void)
 {
        REG_LOCAL_IRQ_SAVE;
-       pChipcHw->PLLConfig2 |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+       writel(readl(&pChipcHw->PLLConfig2) | chipcHw_REG_PLL_CONFIG_POWER_DOWN,
+               &pChipcHw->PLLConfig2);
        REG_LOCAL_IRQ_RESTORE;
 }
 
@@ -1233,7 +1238,8 @@ static inline void chipcHw_pll2Disable(void)
 static inline void chipcHw_ddrPhaseAlignInterruptEnable(void)
 {
        REG_LOCAL_IRQ_SAVE;
-       pChipcHw->Spare1 |= chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
+       writel(readl(&pChipcHw->Spare1) | chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE,
+               &pChipcHw->Spare1);
        REG_LOCAL_IRQ_RESTORE;
 }
 
@@ -1245,7 +1251,8 @@ static inline void chipcHw_ddrPhaseAlignInterruptEnable(void)
 static inline void chipcHw_ddrPhaseAlignInterruptDisable(void)
 {
        REG_LOCAL_IRQ_SAVE;
-       pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
+       writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE,
+               &pChipcHw->Spare1);
        REG_LOCAL_IRQ_RESTORE;
 }
 
@@ -1333,7 +1340,8 @@ static inline void chipcHw_ddrHwPhaseAlignDisable(void)
 static inline void chipcHw_vpmSwPhaseAlignEnable(void)
 {
        REG_LOCAL_IRQ_SAVE;
-       pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
+       writel(readl(&pChipcHw->VPMPhaseCtrl1) | chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE,
+                       &pChipcHw->VPMPhaseCtrl1);
        REG_LOCAL_IRQ_RESTORE;
 }
 
@@ -1372,7 +1380,8 @@ static inline void chipcHw_vpmHwPhaseAlignEnable(void)
 static inline void chipcHw_vpmHwPhaseAlignDisable(void)
 {
        REG_LOCAL_IRQ_SAVE;
-       pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
+       writel(readl(&pChipcHw->VPMPhaseCtrl1) & ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE,
+               &pChipcHw->VPMPhaseCtrl1);
        REG_LOCAL_IRQ_RESTORE;
 }
 
@@ -1474,8 +1483,8 @@ chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin)
 /****************************************************************************/
 static inline uint32_t chipcHw_isDdrHwPhaseAligned(void)
 {
-       return (pChipcHw->
-               PhaseAlignStatus & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0;
+       return (readl(&pChipcHw->
+               PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0;
 }
 
 /****************************************************************************/
@@ -1488,8 +1497,8 @@ static inline uint32_t chipcHw_isDdrHwPhaseAligned(void)
 /****************************************************************************/
 static inline uint32_t chipcHw_isVpmHwPhaseAligned(void)
 {
-       return (pChipcHw->
-               PhaseAlignStatus & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0;
+       return (readl(&pChipcHw->
+               PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0;
 }
 
 /****************************************************************************/
@@ -1500,8 +1509,8 @@ static inline uint32_t chipcHw_isVpmHwPhaseAligned(void)
 /****************************************************************************/
 static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void)
 {
-       return (pChipcHw->
-               PhaseAlignStatus & chipcHw_REG_DDR_PHASE_STATUS_MASK) >>
+       return (readl(&pChipcHw->
+               PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_STATUS_MASK) >>
            chipcHw_REG_DDR_PHASE_STATUS_SHIFT;
 }
 
@@ -1513,8 +1522,8 @@ static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void)
 /****************************************************************************/
 static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void)
 {
-       return (pChipcHw->
-               PhaseAlignStatus & chipcHw_REG_VPM_PHASE_STATUS_MASK) >>
+       return (readl(&pChipcHw->
+               PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_STATUS_MASK) >>
            chipcHw_REG_VPM_PHASE_STATUS_SHIFT;
 }
 
@@ -1526,8 +1535,8 @@ static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void)
 /****************************************************************************/
 static inline uint32_t chipcHw_getDdrPhaseControl(void)
 {
-       return (pChipcHw->
-               PhaseAlignStatus & chipcHw_REG_DDR_PHASE_CTRL_MASK) >>
+       return (readl(&pChipcHw->
+               PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_CTRL_MASK) >>
            chipcHw_REG_DDR_PHASE_CTRL_SHIFT;
 }
 
@@ -1539,8 +1548,8 @@ static inline uint32_t chipcHw_getDdrPhaseControl(void)
 /****************************************************************************/
 static inline uint32_t chipcHw_getVpmPhaseControl(void)
 {
-       return (pChipcHw->
-               PhaseAlignStatus & chipcHw_REG_VPM_PHASE_CTRL_MASK) >>
+       return (readl(&pChipcHw->
+               PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_CTRL_MASK) >>
            chipcHw_REG_VPM_PHASE_CTRL_SHIFT;
 }
 
index b162448..26f5d0e 100644 (file)
@@ -24,7 +24,7 @@
 #define CHIPCHW_REG_H
 
 #include <mach/csp/mm_io.h>
-#include <csp/reg.h>
+#include <mach/csp/reg.h>
 #include <mach/csp/ddrcReg.h>
 
 #define chipcHw_BASE_ADDRESS    MM_IO_BASE_CHIPC
@@ -131,8 +131,8 @@ typedef struct {
        uint32_t MiscInput_0_15;        /* Input type for MISC 0 - 16 */
 } chipcHw_REG_t;
 
-#define pChipcHw  ((volatile chipcHw_REG_t *) chipcHw_BASE_ADDRESS)
-#define pChipcPhysical  ((volatile chipcHw_REG_t *) MM_ADDR_IO_CHIPC)
+#define pChipcHw  ((chipcHw_REG_t __iomem *) chipcHw_BASE_ADDRESS)
+#define pChipcPhysical  (MM_ADDR_IO_CHIPC)
 
 #define chipcHw_REG_CHIPID_BASE_MASK                    0xFFFFF000
 #define chipcHw_REG_CHIPID_BASE_SHIFT                   12
index f1b68e2..39da2c1 100644 (file)
@@ -30,8 +30,8 @@ extern "C" {
 
 /* ---- Include Files ---------------------------------------------------- */
 
-#include <csp/reg.h>
-#include <csp/stdint.h>
+#include <mach/csp/reg.h>
+#include <linux/types.h>
 
 #include <mach/csp/mm_io.h>
 
@@ -416,7 +416,7 @@ extern "C" {
        } ddrcReg_PHY_ADDR_CTL_REG_t;
 
 #define ddrcReg_PHY_ADDR_CTL_REG_OFFSET                 0x0400
-#define ddrcReg_PHY_ADDR_CTL_REGP                       ((volatile ddrcReg_PHY_ADDR_CTL_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET))
+#define ddrcReg_PHY_ADDR_CTL_REGP                       ((volatile ddrcReg_PHY_ADDR_CTL_REG_t __iomem*) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET))
 
 /* @todo These SS definitions are duplicates of ones below */
 
similarity index 99%
rename from arch/arm/mach-bcmring/include/csp/dmacHw.h
rename to arch/arm/mach-bcmring/include/mach/csp/dmacHw.h
index e6a1dc4..9dc90f4 100644 (file)
@@ -23,9 +23,9 @@
 #ifndef _DMACHW_H
 #define _DMACHW_H
 
-#include <stddef.h>
+#include <linux/stddef.h>
 
-#include <csp/stdint.h>
+#include <linux/types.h>
 #include <mach/csp/dmacHw_reg.h>
 
 /* Define DMA Channel ID using DMA controller number (m) and channel number (c).
index d67e2f8..9d9455e 100644 (file)
@@ -24,7 +24,7 @@
 #ifndef _DMACHW_PRIV_H
 #define _DMACHW_PRIV_H
 
-#include <csp/stdint.h>
+#include <linux/types.h>
 
 /* Data type for DMA Link List Item */
 typedef struct {
index f1ecf96..7cd0aaf 100644 (file)
@@ -24,7 +24,7 @@
 #ifndef _DMACHW_REG_H
 #define _DMACHW_REG_H
 
-#include <csp/stdint.h>
+#include <linux/types.h>
 #include <mach/csp/mm_io.h>
 
 /* Data type for 64 bit little endian register */
@@ -121,75 +121,75 @@ typedef struct {
 } dmacHw_MISC_t;
 
 /* Base registers */
-#define dmacHw_0_MODULE_BASE_ADDR        (char *) MM_IO_BASE_DMA0      /* DMAC 0 module's base address */
-#define dmacHw_1_MODULE_BASE_ADDR        (char *) MM_IO_BASE_DMA1      /* DMAC 1 module's base address */
+#define dmacHw_0_MODULE_BASE_ADDR        (char __iomem*) MM_IO_BASE_DMA0       /* DMAC 0 module's base address */
+#define dmacHw_1_MODULE_BASE_ADDR        (char __iomem*) MM_IO_BASE_DMA1       /* DMAC 1 module's base address */
 
 extern uint32_t dmaChannelCount_0;
 extern uint32_t dmaChannelCount_1;
 
 /* Define channel specific registers */
-#define dmacHw_CHAN_BASE(module, chan)          ((dmacHw_CH_REG_t *) ((char *)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t))))
+#define dmacHw_CHAN_BASE(module, chan)          ((dmacHw_CH_REG_t __iomem*) ((char __iomem*)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t))))
 
 /* Raw interrupt status registers */
-#define dmacHw_REG_INT_RAW_BASE(module)         ((char *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0)))
-#define dmacHw_REG_INT_RAW_TRAN(module)         (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo)
-#define dmacHw_REG_INT_RAW_BLOCK(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo)
-#define dmacHw_REG_INT_RAW_STRAN(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo)
-#define dmacHw_REG_INT_RAW_DTRAN(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo)
-#define dmacHw_REG_INT_RAW_ERROR(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo)
+#define dmacHw_REG_INT_RAW_BASE(module)         ((char __iomem *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0)))
+#define dmacHw_REG_INT_RAW_TRAN(module)         (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo)
+#define dmacHw_REG_INT_RAW_BLOCK(module)        (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo)
+#define dmacHw_REG_INT_RAW_STRAN(module)        (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo)
+#define dmacHw_REG_INT_RAW_DTRAN(module)        (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo)
+#define dmacHw_REG_INT_RAW_ERROR(module)        (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo)
 
 /* Interrupt status registers */
-#define dmacHw_REG_INT_STAT_BASE(module)        ((char *)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t)))
-#define dmacHw_REG_INT_STAT_TRAN(module)        (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo)
-#define dmacHw_REG_INT_STAT_BLOCK(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo)
-#define dmacHw_REG_INT_STAT_STRAN(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo)
-#define dmacHw_REG_INT_STAT_DTRAN(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo)
-#define dmacHw_REG_INT_STAT_ERROR(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo)
+#define dmacHw_REG_INT_STAT_BASE(module)        ((char __iomem*)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t)))
+#define dmacHw_REG_INT_STAT_TRAN(module)        (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo)
+#define dmacHw_REG_INT_STAT_BLOCK(module)       (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo)
+#define dmacHw_REG_INT_STAT_STRAN(module)       (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo)
+#define dmacHw_REG_INT_STAT_DTRAN(module)       (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo)
+#define dmacHw_REG_INT_STAT_ERROR(module)       (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo)
 
 /* Interrupt status registers */
-#define dmacHw_REG_INT_MASK_BASE(module)        ((char *)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t)))
-#define dmacHw_REG_INT_MASK_TRAN(module)        (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo)
-#define dmacHw_REG_INT_MASK_BLOCK(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo)
-#define dmacHw_REG_INT_MASK_STRAN(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo)
-#define dmacHw_REG_INT_MASK_DTRAN(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo)
-#define dmacHw_REG_INT_MASK_ERROR(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo)
+#define dmacHw_REG_INT_MASK_BASE(module)        ((char __iomem*)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t)))
+#define dmacHw_REG_INT_MASK_TRAN(module)        (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo)
+#define dmacHw_REG_INT_MASK_BLOCK(module)       (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo)
+#define dmacHw_REG_INT_MASK_STRAN(module)       (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo)
+#define dmacHw_REG_INT_MASK_DTRAN(module)       (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo)
+#define dmacHw_REG_INT_MASK_ERROR(module)       (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo)
 
 /* Interrupt clear registers */
-#define dmacHw_REG_INT_CLEAR_BASE(module)       ((char *)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t)))
-#define dmacHw_REG_INT_CLEAR_TRAN(module)       (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo)
-#define dmacHw_REG_INT_CLEAR_BLOCK(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo)
-#define dmacHw_REG_INT_CLEAR_STRAN(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo)
-#define dmacHw_REG_INT_CLEAR_DTRAN(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo)
-#define dmacHw_REG_INT_CLEAR_ERROR(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo)
-#define dmacHw_REG_INT_STATUS(module)           (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo)
+#define dmacHw_REG_INT_CLEAR_BASE(module)       ((char __iomem*)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t)))
+#define dmacHw_REG_INT_CLEAR_TRAN(module)       (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo)
+#define dmacHw_REG_INT_CLEAR_BLOCK(module)      (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo)
+#define dmacHw_REG_INT_CLEAR_STRAN(module)      (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo)
+#define dmacHw_REG_INT_CLEAR_DTRAN(module)      (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo)
+#define dmacHw_REG_INT_CLEAR_ERROR(module)      (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo)
+#define dmacHw_REG_INT_STATUS(module)           (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo)
 
 /* Software handshaking registers */
-#define dmacHw_REG_SW_HS_BASE(module)           ((char *)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t)))
-#define dmacHw_REG_SW_HS_SRC_REQ(module)        (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_REQ(module)        (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo)
-#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_SGL_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo)
-#define dmacHw_REG_SW_HS_SRC_LST_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_LST_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo)
+#define dmacHw_REG_SW_HS_BASE(module)           ((char __iomem*)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t)))
+#define dmacHw_REG_SW_HS_SRC_REQ(module)        (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo)
+#define dmacHw_REG_SW_HS_DST_REQ(module)        (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo)
+#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module)    (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo)
+#define dmacHw_REG_SW_HS_DST_SGL_REQ(module)    (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo)
+#define dmacHw_REG_SW_HS_SRC_LST_REQ(module)    (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo)
+#define dmacHw_REG_SW_HS_DST_LST_REQ(module)    (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo)
 
 /* Miscellaneous registers */
-#define dmacHw_REG_MISC_BASE(module)            ((char *)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t)))
-#define dmacHw_REG_MISC_CFG(module)             (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo)
-#define dmacHw_REG_MISC_CH_ENABLE(module)       (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo)
-#define dmacHw_REG_MISC_ID(module)              (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo)
-#define dmacHw_REG_MISC_TEST(module)            (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo)
-#define dmacHw_REG_MISC_COMP_PARAM1_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo)
-#define dmacHw_REG_MISC_COMP_PARAM1_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi)
-#define dmacHw_REG_MISC_COMP_PARAM2_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo)
-#define dmacHw_REG_MISC_COMP_PARAM2_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi)
-#define dmacHw_REG_MISC_COMP_PARAM3_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo)
-#define dmacHw_REG_MISC_COMP_PARAM3_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi)
-#define dmacHw_REG_MISC_COMP_PARAM4_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo)
-#define dmacHw_REG_MISC_COMP_PARAM4_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi)
-#define dmacHw_REG_MISC_COMP_PARAM5_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo)
-#define dmacHw_REG_MISC_COMP_PARAM5_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi)
-#define dmacHw_REG_MISC_COMP_PARAM6_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo)
-#define dmacHw_REG_MISC_COMP_PARAM6_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi)
+#define dmacHw_REG_MISC_BASE(module)            ((char __iomem*)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t)))
+#define dmacHw_REG_MISC_CFG(module)             (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo)
+#define dmacHw_REG_MISC_CH_ENABLE(module)       (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo)
+#define dmacHw_REG_MISC_ID(module)              (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo)
+#define dmacHw_REG_MISC_TEST(module)            (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo)
+#define dmacHw_REG_MISC_COMP_PARAM1_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo)
+#define dmacHw_REG_MISC_COMP_PARAM1_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi)
+#define dmacHw_REG_MISC_COMP_PARAM2_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo)
+#define dmacHw_REG_MISC_COMP_PARAM2_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi)
+#define dmacHw_REG_MISC_COMP_PARAM3_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo)
+#define dmacHw_REG_MISC_COMP_PARAM3_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi)
+#define dmacHw_REG_MISC_COMP_PARAM4_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo)
+#define dmacHw_REG_MISC_COMP_PARAM4_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi)
+#define dmacHw_REG_MISC_COMP_PARAM5_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo)
+#define dmacHw_REG_MISC_COMP_PARAM5_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi)
+#define dmacHw_REG_MISC_COMP_PARAM6_LO(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo)
+#define dmacHw_REG_MISC_COMP_PARAM6_HI(module)  (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi)
 
 /* Channel control registers */
 #define dmacHw_REG_SAR(module, chan)            (dmacHw_CHAN_BASE((module), (chan))->ChannelSar.lo)
index cfa91be..27f59dd 100644 (file)
@@ -18,7 +18,7 @@
 
 /* ---- Include Files ---------------------------------------------------- */
 
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
 #include <mach/csp/cap_inline.h>
 
 #if defined(__KERNEL__)
index 0aeb6a6..f59db25 100644 (file)
@@ -27,8 +27,8 @@
 #define _INTCHW_REG_H
 
 /* ---- Include Files ---------------------------------------------------- */
-#include <csp/stdint.h>
-#include <csp/reg.h>
+#include <linux/types.h>
+#include <mach/csp/reg.h>
 #include <mach/csp/mm_io.h>
 
 /* ---- Public Constants and Types --------------------------------------- */
@@ -37,9 +37,9 @@
 #define INTCHW_NUM_INTC           3
 
 /* Defines for interrupt controllers. This simplifies and cleans up the function calls. */
-#define INTCHW_INTC0    ((void *)MM_IO_BASE_INTC0)
-#define INTCHW_INTC1    ((void *)MM_IO_BASE_INTC1)
-#define INTCHW_SINTC    ((void *)MM_IO_BASE_SINTC)
+#define INTCHW_INTC0    (MM_IO_BASE_INTC0)
+#define INTCHW_INTC1    (MM_IO_BASE_INTC1)
+#define INTCHW_SINTC    (MM_IO_BASE_SINTC)
 
 /* INTC0 - interrupt controller 0 */
 #define INTCHW_INTC0_PIF_BITNUM           31   /* Peripheral interface interrupt */
 /* ---- Public Variable Externs ------------------------------------------ */
 /* ---- Public Function Prototypes --------------------------------------- */
 /* Clear one or more IRQ interrupts. */
-static inline void intcHw_irq_disable(void *basep, uint32_t mask)
+static inline void intcHw_irq_disable(void __iomem *basep, uint32_t mask)
 {
-       __REG32(basep + INTCHW_INTENCLEAR) = mask;
+       writel(mask, basep + INTCHW_INTENCLEAR);
 }
 
 /* Enables one or more IRQ interrupts. */
-static inline void intcHw_irq_enable(void *basep, uint32_t mask)
+static inline void intcHw_irq_enable(void __iomem *basep, uint32_t mask)
 {
-       __REG32(basep + INTCHW_INTENABLE) = mask;
+       writel(mask, basep + INTCHW_INTENABLE);
 }
 
 #endif /* _INTCHW_REG_H */
index ad58cf8..d571962 100644 (file)
@@ -29,7 +29,7 @@
 /* ---- Include Files ---------------------------------------------------- */
 
 #if !defined(CSP_SIMULATION)
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
 #endif
 
 /* ---- Public Constants and Types --------------------------------------- */
index de92ec6..47450c2 100644 (file)
@@ -30,7 +30,7 @@
 #include <mach/csp/mm_addr.h>
 
 #if !defined(CSP_SIMULATION)
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
 #endif
 
 /* ---- Public Constants and Types --------------------------------------- */
@@ -49,7 +49,7 @@
 #ifdef __ASSEMBLY__
 #define MM_IO_PHYS_TO_VIRT(phys)       (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF))
 #else
-#define MM_IO_PHYS_TO_VIRT(phys)       (((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \
+#define MM_IO_PHYS_TO_VIRT(phys)       (void __iomem *)(((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \
                        (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)))
 #endif
 #endif
@@ -60,8 +60,8 @@
 #ifdef __ASSEMBLY__
 #define MM_IO_VIRT_TO_PHYS(virt)       ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF))
 #else
-#define MM_IO_VIRT_TO_PHYS(virt)       (((virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \
-                       ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF)))
+#define MM_IO_VIRT_TO_PHYS(virt)       (((unsigned long)(virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \
+                       ((((unsigned long)(virt) & 0x0F000000) << 4) | ((unsigned long)(virt) & 0xFFFFFF)))
 #endif
 #endif
 
similarity index 81%
rename from arch/arm/mach-bcmring/include/csp/reg.h
rename to arch/arm/mach-bcmring/include/mach/csp/reg.h
index 56654d2..d9cbdca 100644 (file)
 
 /* ---- Include Files ---------------------------------------------------- */
 
-#include <csp/stdint.h>
+#include <linux/types.h>
+#include <linux/io.h>
 
 /* ---- Public Constants and Types --------------------------------------- */
 
-#define __REG32(x)      (*((volatile uint32_t *)(x)))
-#define __REG16(x)      (*((volatile uint16_t *)(x)))
-#define __REG8(x)       (*((volatile uint8_t *) (x)))
+#define __REG32(x)      (*((volatile uint32_t __iomem *)(x)))
+#define __REG16(x)      (*((volatile uint16_t __iomem *)(x)))
+#define __REG8(x)       (*((volatile uint8_t __iomem *) (x)))
 
 /* Macros used to define a sequence of reserved registers. The start / end */
 /* are byte offsets in the particular register definition, with the "end" */
 
 #endif
 
-static inline void reg32_modify_and(volatile uint32_t *reg, uint32_t value)
+static inline void reg32_modify_and(volatile uint32_t __iomem *reg, uint32_t value)
 {
        REG_LOCAL_IRQ_SAVE;
-       *reg &= value;
+       __raw_writel(__raw_readl(reg) & value, reg);
        REG_LOCAL_IRQ_RESTORE;
 }
 
-static inline void reg32_modify_or(volatile uint32_t *reg, uint32_t value)
+static inline void reg32_modify_or(volatile uint32_t __iomem *reg, uint32_t value)
 {
        REG_LOCAL_IRQ_SAVE;
-       *reg |= value;
+       __raw_writel(__raw_readl(reg) | value, reg);
        REG_LOCAL_IRQ_RESTORE;
 }
 
-static inline void reg32_modify_mask(volatile uint32_t *reg, uint32_t mask,
+static inline void reg32_modify_mask(volatile uint32_t __iomem *reg, uint32_t mask,
                                     uint32_t value)
 {
        REG_LOCAL_IRQ_SAVE;
-       *reg = (*reg & mask) | value;
+       __raw_writel((__raw_readl(reg) & mask) | value, reg);
        REG_LOCAL_IRQ_RESTORE;
 }
 
-static inline void reg32_write(volatile uint32_t *reg, uint32_t value)
+static inline void reg32_write(volatile uint32_t __iomem *reg, uint32_t value)
 {
-       *reg = value;
+       __raw_writel(value, reg);
 }
 
 #endif /* CSP_REG_H */
index 9cd6a03..55d3cd4 100644 (file)
@@ -34,7 +34,7 @@
 /****************************************************************************/
 static inline void secHw_setSecure(uint32_t mask       /*  mask of type secHw_BLK_MASK_XXXXXX */
     ) {
-       secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
+       secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC;
 
        if (mask & 0x0000FFFF) {
                regp->reg[secHw_IDX_LS].setSecure = mask & 0x0000FFFF;
@@ -53,13 +53,13 @@ static inline void secHw_setSecure(uint32_t mask    /*  mask of type secHw_BLK_MASK
 /****************************************************************************/
 static inline void secHw_setUnsecure(uint32_t mask     /*  mask of type secHw_BLK_MASK_XXXXXX */
     ) {
-       secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
+       secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC;
 
        if (mask & 0x0000FFFF) {
-               regp->reg[secHw_IDX_LS].setUnsecure = mask & 0x0000FFFF;
+               writel(mask & 0x0000FFFF, &regp->reg[secHw_IDX_LS].setUnsecure);
        }
        if (mask & 0xFFFF0000) {
-               regp->reg[secHw_IDX_MS].setUnsecure = mask >> 16;
+               writel(mask >> 16, &regp->reg[secHw_IDX_MS].setUnsecure);
        }
 }
 
@@ -71,7 +71,7 @@ static inline void secHw_setUnsecure(uint32_t mask    /*  mask of type secHw_BLK_MA
 /****************************************************************************/
 static inline uint32_t secHw_getStatus(void)
 {
-       secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
+       secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC;
 
        return (regp->reg[1].status << 16) + regp->reg[0].status;
 }
similarity index 99%
rename from arch/arm/mach-bcmring/include/csp/tmrHw.h
rename to arch/arm/mach-bcmring/include/mach/csp/tmrHw.h
index 2cbb530..1cc882a 100644 (file)
@@ -23,7 +23,7 @@
 #ifndef _TMRHW_H
 #define _TMRHW_H
 
-#include <csp/stdint.h>
+#include <linux/types.h>
 
 typedef uint32_t tmrHw_ID_t;   /* Timer ID */
 typedef uint32_t tmrHw_COUNT_t;        /* Timer count */
index 7254378..13e0138 100644 (file)
@@ -27,7 +27,7 @@
 
 #include <linux/kernel.h>
 #include <linux/semaphore.h>
-#include <csp/dmacHw.h>
+#include <mach/csp/dmacHw.h>
 #include <mach/timer.h>
 
 /* ---- Constants and Types ---------------------------------------------- */
index 6ae20a6..a0c92b4 100644 (file)
@@ -22,7 +22,7 @@
 #define __ASM_ARCH_HARDWARE_H
 
 #include <asm/sizes.h>
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
 #include <mach/csp/mm_io.h>
 
 /* Hardware addresses of major areas.
index 387376f..f8d51a8 100644 (file)
@@ -30,7 +30,7 @@
 #define __ASM_ARCH_REG_NAND_H
 
 /* ---- Include Files ---------------------------------------------------- */
-#include <csp/reg.h>
+#include <mach/csp/reg.h>
 #include <mach/reg_umi.h>
 
 /* ---- Constants and Types ---------------------------------------------- */
index 0992842..56dd9de 100644 (file)
@@ -30,7 +30,7 @@
 #define __ASM_ARCH_REG_UMI_H
 
 /* ---- Include Files ---------------------------------------------------- */
-#include <csp/reg.h>
+#include <mach/csp/reg.h>
 #include <mach/csp/mm_io.h>
 
 /* ---- Constants and Types ---------------------------------------------- */
 #define REG_UMI_BCH_ERR_LOC_WORD              0x00000018
 /* location within a page (512 byte) */
 #define REG_UMI_BCH_ERR_LOC_PAGE              0x00001FE0
-#define REG_UMI_BCH_ERR_LOC_ADDR(index)     (__REG32(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16))
+#define REG_UMI_BCH_ERR_LOC_ADDR(index)     (readl(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16))
 #endif
index 1adec78..33824a8 100644 (file)
 #include <mach/hardware.h>
 #include <mach/csp/mm_io.h>
 
-#define IO_DESC(va, sz) { .virtual = va, \
+#define IO_DESC(va, sz) { .virtual = (unsigned long)va, \
        .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
        .length = sz, \
        .type = MT_DEVICE }
 
-#define MEM_DESC(va, sz) { .virtual = va, \
+#define MEM_DESC(va, sz) { .virtual = (unsigned long)va, \
        .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
        .length = sz, \
        .type = MT_MEMORY }
index af9c3d7..5941290 100644 (file)
@@ -14,7 +14,7 @@
 
 #include <linux/types.h>
 #include <linux/module.h>
-#include <csp/tmrHw.h>
+#include <mach/csp/tmrHw.h>
 
 #include <mach/timer.h>
 /* The core.c file initializes timers 1 and 3 as a linux clocksource. */
index 6321567..cc4c6a5 100644 (file)
@@ -49,16 +49,6 @@ static struct map_desc dove_io_desc[] __initdata = {
                .pfn            = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
                .length         = DOVE_NB_REGS_SIZE,
                .type           = MT_DEVICE,
-       }, {
-               .virtual        = DOVE_PCIE0_IO_VIRT_BASE,
-               .pfn            = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE),
-               .length         = DOVE_PCIE0_IO_SIZE,
-               .type           = MT_DEVICE,
-       }, {
-               .virtual        = DOVE_PCIE1_IO_VIRT_BASE,
-               .pfn            = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE),
-               .length         = DOVE_PCIE1_IO_SIZE,
-               .type           = MT_DEVICE,
        },
 };
 
index d52b0ef..c91e300 100644 (file)
 #define DOVE_NB_REGS_SIZE              SZ_8M
 
 #define DOVE_PCIE0_IO_PHYS_BASE                0xf2000000
-#define DOVE_PCIE0_IO_VIRT_BASE                0xfee00000
 #define DOVE_PCIE0_IO_BUS_BASE         0x00000000
-#define DOVE_PCIE0_IO_SIZE             SZ_1M
+#define DOVE_PCIE0_IO_SIZE             SZ_64K
 
 #define DOVE_PCIE1_IO_PHYS_BASE                0xf2100000
-#define DOVE_PCIE1_IO_VIRT_BASE                0xfef00000
-#define DOVE_PCIE1_IO_BUS_BASE         0x00100000
-#define DOVE_PCIE1_IO_SIZE             SZ_1M
+#define DOVE_PCIE1_IO_BUS_BASE         0x00010000
+#define DOVE_PCIE1_IO_SIZE             SZ_64K
 
 /*
  * Dove Core Registers Map
diff --git a/arch/arm/mach-dove/include/mach/io.h b/arch/arm/mach-dove/include/mach/io.h
deleted file mode 100644 (file)
index 29c8b85..0000000
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-dove/include/mach/io.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#include "dove.h"
-
-#define IO_SPACE_LIMIT         0xffffffff
-
-#define __io(a)        ((void __iomem *)(((a) - DOVE_PCIE0_IO_BUS_BASE) + \
-                                                DOVE_PCIE0_IO_VIRT_BASE))
-
-#endif
index 47921b0..355332d 100644 (file)
@@ -26,9 +26,8 @@ struct pcie_port {
        u8                      root_bus_nr;
        void __iomem            *base;
        spinlock_t              conf_lock;
-       char                    io_space_name[16];
        char                    mem_space_name[16];
-       struct resource         res[2];
+       struct resource         res;
 };
 
 static struct pcie_port pcie_port[2];
@@ -53,24 +52,10 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
 
        orion_pcie_setup(pp->base);
 
-       /*
-        * IORESOURCE_IO
-        */
-       snprintf(pp->io_space_name, sizeof(pp->io_space_name),
-                "PCIe %d I/O", pp->index);
-       pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
-       pp->res[0].name = pp->io_space_name;
-       if (pp->index == 0) {
-               pp->res[0].start = DOVE_PCIE0_IO_PHYS_BASE;
-               pp->res[0].end = pp->res[0].start + DOVE_PCIE0_IO_SIZE - 1;
-       } else {
-               pp->res[0].start = DOVE_PCIE1_IO_PHYS_BASE;
-               pp->res[0].end = pp->res[0].start + DOVE_PCIE1_IO_SIZE - 1;
-       }
-       pp->res[0].flags = IORESOURCE_IO;
-       if (request_resource(&ioport_resource, &pp->res[0]))
-               panic("Request PCIe IO resource failed\n");
-       pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
+       if (pp->index == 0)
+               pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE0_IO_PHYS_BASE);
+       else
+               pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE1_IO_PHYS_BASE);
 
        /*
         * IORESOURCE_MEM
@@ -78,18 +63,18 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
        snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
                 "PCIe %d MEM", pp->index);
        pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
-       pp->res[1].name = pp->mem_space_name;
+       pp->res.name = pp->mem_space_name;
        if (pp->index == 0) {
-               pp->res[1].start = DOVE_PCIE0_MEM_PHYS_BASE;
-               pp->res[1].end = pp->res[1].start + DOVE_PCIE0_MEM_SIZE - 1;
+               pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE;
+               pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1;
        } else {
-               pp->res[1].start = DOVE_PCIE1_MEM_PHYS_BASE;
-               pp->res[1].end = pp->res[1].start + DOVE_PCIE1_MEM_SIZE - 1;
+               pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE;
+               pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1;
        }
-       pp->res[1].flags = IORESOURCE_MEM;
-       if (request_resource(&iomem_resource, &pp->res[1]))
+       pp->res.flags = IORESOURCE_MEM;
+       if (request_resource(&iomem_resource, &pp->res))
                panic("Request PCIe Memory resource failed\n");
-       pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
+       pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
 
        return 1;
 }
@@ -210,7 +195,7 @@ static void __init add_pcie_port(int index, unsigned long base)
                pp->root_bus_nr = -1;
                pp->base = (void __iomem *)base;
                spin_lock_init(&pp->conf_lock);
-               memset(pp->res, 0, sizeof(pp->res));
+               memset(&pp->res, 0, sizeof(pp->res));
        } else {
                printk(KERN_INFO "link down, ignoring\n");
        }
index 6f80686..f0fe6b5 100644 (file)
@@ -74,22 +74,22 @@ static struct map_desc ebsa110_io_desc[] __initdata = {
         * sparse external-decode ISAIO space
         */
        {       /* IRQ_STAT/IRQ_MCLR */
-               .virtual        = IRQ_STAT,
+               .virtual        = (unsigned long)IRQ_STAT,
                .pfn            = __phys_to_pfn(TRICK4_PHYS),
                .length         = TRICK4_SIZE,
                .type           = MT_DEVICE
        }, {    /* IRQ_MASK/IRQ_MSET */
-               .virtual        = IRQ_MASK,
+               .virtual        = (unsigned long)IRQ_MASK,
                .pfn            = __phys_to_pfn(TRICK3_PHYS),
                .length         = TRICK3_SIZE,
                .type           = MT_DEVICE
        }, {    /* SOFT_BASE */
-               .virtual        = SOFT_BASE,
+               .virtual        = (unsigned long)SOFT_BASE,
                .pfn            = __phys_to_pfn(TRICK1_PHYS),
                .length         = TRICK1_SIZE,
                .type           = MT_DEVICE
        }, {    /* PIT_BASE */
-               .virtual        = PIT_BASE,
+               .virtual        = (unsigned long)PIT_BASE,
                .pfn            = __phys_to_pfn(TRICK0_PHYS),
                .length         = TRICK0_SIZE,
                .type           = MT_DEVICE
index c93c9e4..afe137e 100644 (file)
 #define TRICK7_PHYS            0xf3c00000
 
 /* Virtual addresses */
-#define PIT_BASE               0xfc000000      /* trick 0 */
-#define SOFT_BASE              0xfd000000      /* trick 1 */
-#define IRQ_MASK               0xfe000000      /* trick 3 - read */
-#define IRQ_MSET               0xfe000000      /* trick 3 - write */
-#define IRQ_STAT               0xff000000      /* trick 4 - read */
-#define IRQ_MCLR               0xff000000      /* trick 4 - write */
+#define PIT_BASE               IOMEM(0xfc000000)       /* trick 0 */
+#define SOFT_BASE              IOMEM(0xfd000000)       /* trick 1 */
+#define IRQ_MASK               IOMEM(0xfe000000)       /* trick 3 - read */
+#define IRQ_MSET               IOMEM(0xfe000000)       /* trick 3 - write */
+#define IRQ_STAT               IOMEM(0xff000000)       /* trick 4 - read */
+#define IRQ_MCLR               IOMEM(0xff000000)       /* trick 4 - write */
 
 #endif
index 774533c..3b00e29 100644 (file)
@@ -166,11 +166,6 @@ static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
 }
 
-static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);
-}
-
 static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
 {
        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
@@ -672,10 +667,6 @@ static struct clk exynos5_init_clocks_off[] = {
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 7),
        }, {
-               .name           = "gps",
-               .enable         = exynos5_clk_ip_gps_ctrl,
-               .ctrlbit        = ((1 << 3) | (1 << 2) | (1 << 0)),
-       }, {
                .name           = "nfcon",
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 22),
index c941053..6d33f50 100644 (file)
 #define EXYNOS5_PA_SYSMMU_JPEG         0x11F20000
 #define EXYNOS5_PA_SYSMMU_IOP          0x12360000
 #define EXYNOS5_PA_SYSMMU_RTIC         0x12370000
-#define EXYNOS5_PA_SYSMMU_GPS          0x12630000
 #define EXYNOS5_PA_SYSMMU_ISP          0x13260000
 #define EXYNOS5_PA_SYSMMU_DRC          0x12370000
 #define EXYNOS5_PA_SYSMMU_SCALERC      0x13280000
index 3e6aaa6..a42b369 100644 (file)
@@ -15,7 +15,7 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/spinlock.h>
+
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/irq.h>
@@ -26,6 +26,7 @@
 
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
+#include <asm/mach/pci.h>
 
 #include "common.h"
 
@@ -175,11 +176,6 @@ static struct map_desc ebsa285_host_io_desc[] __initdata = {
                .pfn            = __phys_to_pfn(DC21285_PCI_IACK),
                .length         = PCIIACK_SIZE,
                .type           = MT_DEVICE,
-       }, {
-               .virtual        = PCIO_BASE,
-               .pfn            = __phys_to_pfn(DC21285_PCI_IO),
-               .length         = PCIO_SIZE,
-               .type           = MT_DEVICE,
        },
 #endif
 };
@@ -196,8 +192,10 @@ void __init footbridge_map_io(void)
         * Now, work out what we've got to map in addition on this
         * platform.
         */
-       if (footbridge_cfn_mode())
+       if (footbridge_cfn_mode()) {
                iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc));
+               pci_map_io_early(__phys_to_pfn(DC21285_PCI_IO));
+       }
 }
 
 void footbridge_restart(char mode, const char *cmd)
index 9d62e33..a7cd2cf 100644 (file)
@@ -276,8 +276,8 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys)
 
        sys->mem_offset  = DC21285_PCI_MEM;
 
-       pci_add_resource_offset(&sys->resources,
-                               &ioport_resource, sys->io_offset);
+       pci_ioremap_io(0, DC21285_PCI_IO);
+
        pci_add_resource_offset(&sys->resources, &res[0], sys->mem_offset);
        pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
 
@@ -298,7 +298,7 @@ void __init dc21285_preinit(void)
        mem_size = (unsigned int)high_memory - PAGE_OFFSET;
        for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1)
                if (mem_mask >= mem_size)
-                       break;          
+                       break;
 
        /*
         * These registers need to be set up whether we're the
@@ -350,14 +350,6 @@ void __init dc21285_preinit(void)
                            "PCI data parity", NULL);
 
        if (cfn_mode) {
-               static struct resource csrio;
-
-               csrio.flags  = IORESOURCE_IO;
-               csrio.name   = "Footbridge";
-
-               allocate_resource(&ioport_resource, &csrio, 128,
-                                 0xff00, 0xffff, 128, NULL, NULL);
-
                /*
                 * Map our SDRAM at a known address in PCI space, just in case
                 * the firmware had other ideas.  Using a nonzero base is
@@ -365,7 +357,7 @@ void __init dc21285_preinit(void)
                 * in the range 0x000a0000 to 0x000c0000. (eg, S3 cards).
                 */
                *CSR_PCICSRBASE       = 0xf4000000;
-               *CSR_PCICSRIOBASE     = csrio.start;
+               *CSR_PCICSRIOBASE     = 0;
                *CSR_PCISDRAMBASE     = __virt_to_bus(PAGE_OFFSET);
                *CSR_PCIROMBASE       = 0;
                *CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
index e5acde2..c169f0c 100644 (file)
@@ -17,7 +17,8 @@
        /* For NetWinder debugging */
                .macro  addruart, rp, rv, tmp
                mov     \rp, #0x000003f8
-               orr     \rv, \rp, #0xff000000   @ virtual
+               orr     \rv, \rp, #0xfe000000   @ virtual
+               orr     \rv, \rv, #0x00e00000   @ virtual
                orr     \rp, \rp, #0x7c000000   @ physical
                .endm
 
index aba531e..aba4638 100644 (file)
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#ifdef CONFIG_MMU
-#define MMU_IO(a, b)   (a)
-#else
-#define MMU_IO(a, b)   (b)
-#endif
-
-#define PCIO_SIZE       0x00100000
-#define PCIO_BASE       MMU_IO(0xff000000, 0x7c000000)
-
 /*
- * Translation of various region addresses to virtual addresses
+ * Translation of various i/o addresses to host addresses for !CONFIG_MMU
  */
+#define PCIO_BASE       0x7c000000
 #define __io(a)                        ((void __iomem *)(PCIO_BASE + (a)))
 
 #endif
index d004d37..d120419 100644 (file)
@@ -13,7 +13,7 @@ imx5-pm-$(CONFIG_PM) += pm-imx5.o
 obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) cpu_op-mx51.o
 
 obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
-                           clk-pfd.o clk-busy.o
+                           clk-pfd.o clk-busy.o clk.o
 
 # Support for CMOS sensor interface
 obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
index ea13e61..cf65148 100644 (file)
@@ -23,7 +23,6 @@
 #include <linux/clk-provider.h>
 #include <linux/io.h>
 #include <linux/module.h>
-#include <linux/clkdev.h>
 #include <linux/err.h>
 
 #include <mach/hardware.h>
index 4bdcaa9..f89c440 100644 (file)
@@ -39,10 +39,10 @@ static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", };
 static const char *emi_slow_sel[] = { "main_bus", "ahb", };
 static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };
 static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };
-static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0", };
+static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", };
 static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", };
 static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", };
-static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1", };
+static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", };
 static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", };
 static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", };
 static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };
index 2d856f9..02be731 100644 (file)
@@ -6,7 +6,7 @@
 #include <linux/err.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/clock.h>
+
 #include "clk.h"
 
 /**
@@ -29,8 +29,53 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
                unsigned long parent_rate)
 {
        struct clk_pllv1 *pll = to_clk_pllv1(hw);
+       long long ll;
+       int mfn_abs;
+       unsigned int mfi, mfn, mfd, pd;
+       u32 reg;
+       unsigned long rate;
+
+       reg = readl(pll->base);
+
+       /*
+        * Get the resulting clock rate from a PLL register value and the input
+        * frequency. PLLs with this register layout can be found on i.MX1,
+        * i.MX21, i.MX27 and i,MX31
+        *
+        *                  mfi + mfn / (mfd + 1)
+        *  f = 2 * f_ref * --------------------
+        *                        pd + 1
+        */
+
+       mfi = (reg >> 10) & 0xf;
+       mfn = reg & 0x3ff;
+       mfd = (reg >> 16) & 0x3ff;
+       pd =  (reg >> 26) & 0xf;
+
+       mfi = mfi <= 5 ? 5 : mfi;
+
+       mfn_abs = mfn;
+
+       /*
+        * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
+        * 2's complements number
+        */
+       if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
+               mfn_abs = 0x400 - mfn;
+
+       rate = parent_rate * 2;
+       rate /= pd + 1;
+
+       ll = (unsigned long long)rate * mfn_abs;
+
+       do_div(ll, mfd + 1);
+
+       if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
+               ll = -ll;
+
+       ll = (rate * mfi) + ll;
 
-       return mxc_decode_pll(readl(pll->base), parent_rate);
+       return ll;
 }
 
 struct clk_ops clk_pllv1_ops = {
diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c
new file mode 100644 (file)
index 0000000..f5e8be8
--- /dev/null
@@ -0,0 +1,3 @@
+#include <linux/spinlock.h>
+
+DEFINE_SPINLOCK(imx_ccm_lock);
index 1bf64fe..5f2d8ac 100644 (file)
@@ -3,7 +3,8 @@
 
 #include <linux/spinlock.h>
 #include <linux/clk-provider.h>
-#include <mach/clock.h>
+
+extern spinlock_t imx_ccm_lock;
 
 struct clk *imx_clk_pllv1(const char *name, const char *parent,
                void __iomem *base);
index 5d08533..0330078 100644 (file)
@@ -36,7 +36,6 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 
-#include <mach/clock.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx3.h>
@@ -259,13 +258,13 @@ static void __init kzm_board_init(void)
  */
 static struct map_desc kzm_io_desc[] __initdata = {
        {
-               .virtual        = MX31_CS4_BASE_ADDR_VIRT,
+               .virtual        = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
                .pfn            = __phys_to_pfn(MX31_CS4_BASE_ADDR),
                .length         = MX31_CS4_SIZE,
                .type           = MT_DEVICE
        },
        {
-               .virtual        = MX31_CS5_BASE_ADDR_VIRT,
+               .virtual        = (unsigned long)MX31_CS5_BASE_ADDR_VIRT,
                .pfn            = __phys_to_pfn(MX31_CS5_BASE_ADDR),
                .length         = MX31_CS5_SIZE,
                .type           = MT_DEVICE
index d37f480..e774b07 100644 (file)
@@ -540,7 +540,7 @@ static void __init mxc_init_audio(void)
  */
 static struct map_desc mx31ads_io_desc[] __initdata = {
        {
-               .virtual        = MX31_CS4_BASE_ADDR_VIRT,
+               .virtual        = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
                .pfn            = __phys_to_pfn(MX31_CS4_BASE_ADDR),
                .length         = CS4_CS8900_MMIO_START,
                .type           = MT_DEVICE
index c8785b3..ef57cff 100644 (file)
@@ -207,7 +207,7 @@ static struct platform_device physmap_flash_device = {
  */
 static struct map_desc mx31lite_io_desc[] __initdata = {
        {
-               .virtual = MX31_CS4_BASE_ADDR_VIRT,
+               .virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
                .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
                .length = MX31_CS4_SIZE,
                .type = MT_DEVICE
index 3fa6c51..a432d43 100644 (file)
@@ -95,8 +95,8 @@ arch_initcall(integrator_init);
  *  UART0  7    6
  *  UART1  5    4
  */
-#define SC_CTRLC       IO_ADDRESS(INTEGRATOR_SC_CTRLC)
-#define SC_CTRLS       IO_ADDRESS(INTEGRATOR_SC_CTRLS)
+#define SC_CTRLC       __io_address(INTEGRATOR_SC_CTRLC)
+#define SC_CTRLS       __io_address(INTEGRATOR_SC_CTRLS)
 
 static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *base, unsigned int mctrl)
 {
index fbb4577..590c192 100644 (file)
 
 static struct cpufreq_driver integrator_driver;
 
-#define CM_ID          IO_ADDRESS(INTEGRATOR_HDR_ID)
-#define CM_OSC IO_ADDRESS(INTEGRATOR_HDR_OSC)
-#define CM_STAT IO_ADDRESS(INTEGRATOR_HDR_STAT)
-#define CM_LOCK IO_ADDRESS(INTEGRATOR_HDR_LOCK)
+#define CM_ID          __io_address(INTEGRATOR_HDR_ID)
+#define CM_OSC __io_address(INTEGRATOR_HDR_OSC)
+#define CM_STAT __io_address(INTEGRATOR_HDR_STAT)
+#define CM_LOCK __io_address(INTEGRATOR_HDR_LOCK)
 
 static const struct icst_params lclk_params = {
        .ref            = 24000000,
diff --git a/arch/arm/mach-integrator/include/mach/io.h b/arch/arm/mach-integrator/include/mach/io.h
deleted file mode 100644 (file)
index 8de70de..0000000
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- *  arch/arm/mach-integrator/include/mach/io.h
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-/*
- * WARNING: this has to mirror definitions in platform.h
- */
-#define PCI_MEMORY_VADDR        0xe8000000
-#define PCI_CONFIG_VADDR        0xec000000
-#define PCI_V3_VADDR            0xed000000
-#define PCI_IO_VADDR            0xee000000
-
-#define __io(a)                        ((void __iomem *)(PCI_IO_VADDR + (a)))
-
-#endif
index ec467ba..4c03475 100644 (file)
  */
 #define PHYS_PCI_V3_BASE                0x62000000
 
+#define PCI_MEMORY_VADDR               0xe8000000
+#define PCI_CONFIG_VADDR               0xec000000
+#define PCI_V3_VADDR                   0xed000000
+
 /* ------------------------------------------------------------------------
  *  Integrator Interrupt Controllers
  * ------------------------------------------------------------------------
index 3b22675..2215d96 100644 (file)
@@ -50,6 +50,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
+#include <asm/mach/pci.h>
 #include <asm/mach/time.h>
 
 #include <plat/fpga-irq.h>
@@ -73,7 +74,7 @@
  * e8000000    40000000        PCI memory              PHYS_PCI_MEM_BASE       (max 512M)
  * ec000000    61000000        PCI config space        PHYS_PCI_CONFIG_BASE    (max 16M)
  * ed000000    62000000        PCI V3 regs             PHYS_PCI_V3_BASE        (max 64k)
- * ee000000    60000000        PCI IO                  PHYS_PCI_IO_BASE        (max 16M)
+ * fee00000    60000000        PCI IO                  PHYS_PCI_IO_BASE        (max 16M)
  * ef000000                    Cache flush
  * f1000000    10000000        Core module registers
  * f1100000    11000000        System controller registers
@@ -133,25 +134,20 @@ static struct map_desc ap_io_desc[] __initdata = {
                .length         = SZ_4K,
                .type           = MT_DEVICE
        }, {
-               .virtual        = PCI_MEMORY_VADDR,
+               .virtual        = (unsigned long)PCI_MEMORY_VADDR,
                .pfn            = __phys_to_pfn(PHYS_PCI_MEM_BASE),
                .length         = SZ_16M,
                .type           = MT_DEVICE
        }, {
-               .virtual        = PCI_CONFIG_VADDR,
+               .virtual        = (unsigned long)PCI_CONFIG_VADDR,
                .pfn            = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
                .length         = SZ_16M,
                .type           = MT_DEVICE
        }, {
-               .virtual        = PCI_V3_VADDR,
+               .virtual        = (unsigned long)PCI_V3_VADDR,
                .pfn            = __phys_to_pfn(PHYS_PCI_V3_BASE),
                .length         = SZ_64K,
                .type           = MT_DEVICE
-       }, {
-               .virtual        = PCI_IO_VADDR,
-               .pfn            = __phys_to_pfn(PHYS_PCI_IO_BASE),
-               .length         = SZ_64K,
-               .type           = MT_DEVICE
        }
 };
 
@@ -159,6 +155,7 @@ static void __init ap_map_io(void)
 {
        iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
        vga_base = PCI_MEMORY_VADDR;
+       pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
 }
 
 #define INTEGRATOR_SC_VALID_INT        0x003fffff
@@ -317,9 +314,9 @@ static void __init ap_init(void)
 /*
  * Where is the timer (VA)?
  */
-#define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
-#define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE)
-#define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE)
+#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
+#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
+#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
 
 static unsigned long timer_reload;
 
index 82d5c83..3df5fc3 100644 (file)
@@ -59,7 +59,7 @@
 
 #define INTCP_ETH_SIZE                 0x10
 
-#define INTCP_VA_CTRL_BASE             IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
+#define INTCP_VA_CTRL_BASE             __io_address(INTEGRATOR_CP_CTL_BASE)
 #define INTCP_FLASHPROG                        0x04
 #define CINTEGRATOR_FLASHPROG_FLVPPEN  (1 << 0)
 #define CINTEGRATOR_FLASHPROG_FLWREN   (1 << 1)
@@ -265,8 +265,8 @@ static struct platform_device *intcp_devs[] __initdata = {
  */
 static unsigned int mmc_status(struct device *dev)
 {
-       unsigned int status = readl(IO_ADDRESS(0xca000000 + 4));
-       writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8));
+       unsigned int status = readl(__io_address(0xca000000 + 4));
+       writel(8, __io_address(INTEGRATOR_CP_CTL_BASE + 8));
 
        return status & 8;
 }
index b866880..bbeca59 100644 (file)
 /*
  * The V3 PCI interface chip in Integrator provides several windows from
  * local bus memory into the PCI memory areas.   Unfortunately, there
- * are not really enough windows for our usage, therefore we reuse 
+ * are not really enough windows for our usage, therefore we reuse
  * one of the windows for access to PCI configuration space.  The
  * memory map is as follows:
- * 
+ *
  * Local Bus Memory         Usage
- * 
+ *
  * 40000000 - 4FFFFFFF      PCI memory.  256M non-prefetchable
  * 50000000 - 5FFFFFFF      PCI memory.  256M prefetchable
  * 60000000 - 60FFFFFF      PCI IO.  16M
  * 61000000 - 61FFFFFF      PCI Configuration. 16M
- * 
+ *
  * There are three V3 windows, each described by a pair of V3 registers.
  * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2.
  * Base0 and Base1 can be used for any type of PCI memory access.   Base2
  * can be used either for PCI I/O or for I20 accesses.  By default, uHAL
  * uses this only for PCI IO space.
- * 
+ *
  * Normally these spaces are mapped using the following base registers:
- * 
+ *
  * Usage Local Bus Memory         Base/Map registers used
- * 
+ *
  * Mem   40000000 - 4FFFFFFF      LB_BASE0/LB_MAP0
  * Mem   50000000 - 5FFFFFFF      LB_BASE1/LB_MAP1
  * IO    60000000 - 60FFFFFF      LB_BASE2/LB_MAP2
  * Cfg   61000000 - 61FFFFFF
- * 
+ *
  * This means that I20 and PCI configuration space accesses will fail.
- * When PCI configuration accesses are needed (via the uHAL PCI 
+ * When PCI configuration accesses are needed (via the uHAL PCI
  * configuration space primitives) we must remap the spaces as follows:
- * 
+ *
  * Usage Local Bus Memory         Base/Map registers used
- * 
+ *
  * Mem   40000000 - 4FFFFFFF      LB_BASE0/LB_MAP0
  * Mem   50000000 - 5FFFFFFF      LB_BASE0/LB_MAP0
  * IO    60000000 - 60FFFFFF      LB_BASE2/LB_MAP2
  * Cfg   61000000 - 61FFFFFF      LB_BASE1/LB_MAP1
- * 
+ *
  * To make this work, the code depends on overlapping windows working.
- * The V3 chip translates an address by checking its range within 
+ * The V3 chip translates an address by checking its range within
  * each of the BASE/MAP pairs in turn (in ascending register number
  * order).  It will use the first matching pair.   So, for example,
  * if the same address is mapped by both LB_BASE0/LB_MAP0 and
- * LB_BASE1/LB_MAP1, the V3 will use the translation from 
+ * LB_BASE1/LB_MAP1, the V3 will use the translation from
  * LB_BASE0/LB_MAP0.
- * 
+ *
  * To allow PCI Configuration space access, the code enlarges the
  * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M.  This occludes
  * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can
  * be remapped for use by configuration cycles.
- * 
- * At the end of the PCI Configuration space accesses, 
+ *
+ * At the end of the PCI Configuration space accesses,
  * LB_BASE1/LB_MAP1 is reset to map PCI Memory.  Finally the window
  * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to
  * reveal the now restored LB_BASE1/LB_MAP1 window.
- * 
+ *
  * NOTE: We do not set up I2O mapping.  I suspect that this is only
  * for an intelligent (target) device.  Using I2O disables most of
  * the mappings into PCI memory.
  *
  * returns:    configuration address to play on the PCI bus
  *
- * To generate the appropriate PCI configuration cycles in the PCI 
- * configuration address space, you present the V3 with the following pattern 
+ * To generate the appropriate PCI configuration cycles in the PCI
+ * configuration address space, you present the V3 with the following pattern
  * (which is very nearly a type 1 (except that the lower two bits are 00 and
  * not 01).   In order for this mapping to work you need to set up one of
  * the local to PCI aperatures to 16Mbytes in length translating to
  *
  * Type 0:
  *
- *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 
+ *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
  *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
  *
  * Type 1:
  *
- *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 
+ *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
  *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
  *     15:11   Device number (5 bits)
  *     10:8    function number
  *      7:2    register number
- *  
+ *
  */
 static DEFINE_RAW_SPINLOCK(v3_lock);
 
@@ -181,7 +181,7 @@ static DEFINE_RAW_SPINLOCK(v3_lock);
 #undef V3_LB_BASE_PREFETCH
 #define V3_LB_BASE_PREFETCH 0
 
-static unsigned long v3_open_config_window(struct pci_bus *bus,
+static void __iomem *v3_open_config_window(struct pci_bus *bus,
                                           unsigned int devfn, int offset)
 {
        unsigned int address, mapaddress, busnr;
@@ -280,7 +280,7 @@ static void v3_close_config_window(void)
 static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
                          int size, u32 *val)
 {
-       unsigned long addr;
+       void __iomem *addr;
        unsigned long flags;
        u32 v;
 
@@ -311,7 +311,7 @@ static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
 static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
                           int size, u32 val)
 {
-       unsigned long addr;
+       void __iomem *addr;
        unsigned long flags;
 
        raw_spin_lock_irqsave(&v3_lock, flags);
@@ -374,12 +374,9 @@ static int __init pci_v3_setup_resources(struct pci_sys_data *sys)
        }
 
        /*
-        * the IO resource for this bus
         * the mem resource for this bus
         * the prefetch mem resource for this bus
         */
-       pci_add_resource_offset(&sys->resources,
-                               &ioport_resource, sys->io_offset);
        pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset);
        pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset);
 
@@ -391,9 +388,9 @@ static int __init pci_v3_setup_resources(struct pci_sys_data *sys)
  * means I can't get additional information on the reason for the pm2fb
  * problems.  I suppose I'll just have to mind-meld with the machine. ;)
  */
-#define SC_PCI     IO_ADDRESS(INTEGRATOR_SC_PCIENABLE)
-#define SC_LBFADDR IO_ADDRESS(INTEGRATOR_SC_BASE + 0x20)
-#define SC_LBFCODE IO_ADDRESS(INTEGRATOR_SC_BASE + 0x24)
+#define SC_PCI     __io_address(INTEGRATOR_SC_PCIENABLE)
+#define SC_LBFADDR __io_address(INTEGRATOR_SC_BASE + 0x20)
+#define SC_LBFCODE __io_address(INTEGRATOR_SC_BASE + 0x24)
 
 static int
 v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
@@ -498,7 +495,6 @@ void __init pci_v3_preinit(void)
        unsigned int temp;
        int ret;
 
-       pcibios_min_io = 0x6000;
        pcibios_min_mem = 0x00100000;
 
        /*
diff --git a/arch/arm/mach-iop13xx/include/mach/io.h b/arch/arm/mach-iop13xx/include/mach/io.h
deleted file mode 100644 (file)
index f131885..0000000
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * iop13xx custom ioremap implementation
- * Copyright (c) 2005-2006, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
- * Place - Suite 330, Boston, MA 02111-1307 USA.
- *
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define __io(a) __iop13xx_io(a)
-
-extern void __iomem * __iop13xx_io(unsigned long io_addr);
-
-#endif
index e190dcd..7480f58 100644 (file)
@@ -69,21 +69,11 @@ extern unsigned long get_iop_tick_rate(void);
  * 0x8000.0000 + 928M  0x2.8000.0000   (ioremap)       PCIE outbound memory window
  *
  * IO MAP
- * 0x1000 + 64K        0x0.fffb.1000   0xfec6.1000     PCIX outbound i/o window
- * 0x1000 + 64K        0x0.fffd.1000   0xfed7.1000     PCIE outbound i/o window
+ * 0x00000 + 64K       0x0.fffb.0000   0xfee0.0000     PCIX outbound i/o window
+ * 0x10000 + 64K       0x0.fffd.0000   0xfee1.0000     PCIE outbound i/o window
  */
-#define IOP13XX_PCIX_IO_WINDOW_SIZE   0x10000UL
 #define IOP13XX_PCIX_LOWER_IO_PA      0xfffb0000UL
-#define IOP13XX_PCIX_LOWER_IO_VA      0xfec60000UL
 #define IOP13XX_PCIX_LOWER_IO_BA      0x0UL /* OIOTVR */
-#define IOP13XX_PCIX_IO_BUS_OFFSET    0x1000UL
-#define IOP13XX_PCIX_UPPER_IO_PA      (IOP13XX_PCIX_LOWER_IO_PA +\
-                                      IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
-#define IOP13XX_PCIX_UPPER_IO_VA      (IOP13XX_PCIX_LOWER_IO_VA +\
-                                      IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
-#define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
-                                          (IOP13XX_PCIX_LOWER_IO_PA\
-                                          - IOP13XX_PCIX_LOWER_IO_VA))
 
 #define IOP13XX_PCIX_MEM_PHYS_OFFSET  0x100000000ULL
 #define IOP13XX_PCIX_MEM_WINDOW_SIZE  0x3a000000UL
@@ -103,20 +93,8 @@ extern unsigned long get_iop_tick_rate(void);
                                        IOP13XX_PCIX_LOWER_MEM_BA)
 
 /* PCI-E ranges */
-#define IOP13XX_PCIE_IO_WINDOW_SIZE     0x10000UL
 #define IOP13XX_PCIE_LOWER_IO_PA        0xfffd0000UL
-#define IOP13XX_PCIE_LOWER_IO_VA        0xfed70000UL
-#define IOP13XX_PCIE_LOWER_IO_BA        0x0UL  /* OIOTVR */
-#define IOP13XX_PCIE_IO_BUS_OFFSET      0x1000UL
-#define IOP13XX_PCIE_UPPER_IO_PA        (IOP13XX_PCIE_LOWER_IO_PA +\
-                                        IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
-#define IOP13XX_PCIE_UPPER_IO_VA        (IOP13XX_PCIE_LOWER_IO_VA +\
-                                        IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
-#define IOP13XX_PCIE_UPPER_IO_BA        (IOP13XX_PCIE_LOWER_IO_BA +\
-                                        IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
-#define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
-                                          (IOP13XX_PCIE_LOWER_IO_PA\
-                                          - IOP13XX_PCIE_LOWER_IO_VA))
+#define IOP13XX_PCIE_LOWER_IO_BA        0x10000UL  /* OIOTVR */
 
 #define IOP13XX_PCIE_MEM_PHYS_OFFSET    0x200000000ULL
 #define IOP13XX_PCIE_MEM_WINDOW_SIZE    0x3a000000UL
@@ -148,18 +126,16 @@ extern unsigned long get_iop_tick_rate(void);
  * IOP13XX chipset registers
  */
 #define IOP13XX_PMMR_PHYS_MEM_BASE        0xffd80000UL  /* PMMR phys. address */
-#define IOP13XX_PMMR_VIRT_MEM_BASE        0xfee80000UL  /* PMMR phys. address */
+#define IOP13XX_PMMR_VIRT_MEM_BASE        (void __iomem *)(0xfee80000UL)  /* PMMR phys. address */
 #define IOP13XX_PMMR_MEM_WINDOW_SIZE      0x80000
 #define IOP13XX_PMMR_UPPER_MEM_VA         (IOP13XX_PMMR_VIRT_MEM_BASE +\
                                           IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
 #define IOP13XX_PMMR_UPPER_MEM_PA         (IOP13XX_PMMR_PHYS_MEM_BASE +\
                                           IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
-#define IOP13XX_PMMR_VIRT_TO_PHYS(addr)   (u32) ((u32) addr +\
-                                          (IOP13XX_PMMR_PHYS_MEM_BASE\
-                                          - IOP13XX_PMMR_VIRT_MEM_BASE))
-#define IOP13XX_PMMR_PHYS_TO_VIRT(addr)   (u32) ((u32) addr -\
-                                          (IOP13XX_PMMR_PHYS_MEM_BASE\
-                                          - IOP13XX_PMMR_VIRT_MEM_BASE))
+#define IOP13XX_PMMR_VIRT_TO_PHYS(addr)   (((addr) - IOP13XX_PMMR_VIRT_MEM_BASE)\
+                                          + IOP13XX_PMMR_PHYS_MEM_BASE)
+#define IOP13XX_PMMR_PHYS_TO_VIRT(addr)   (((addr) - IOP13XX_PMMR_PHYS_MEM_BASE)\
+                                          + IOP13XX_PMMR_VIRT_MEM_BASE)
 #define IOP13XX_REG_ADDR32(reg)           (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
 #define IOP13XX_REG_ADDR16(reg)           (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
 #define IOP13XX_REG_ADDR8(reg)            (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
@@ -169,10 +145,10 @@ extern unsigned long get_iop_tick_rate(void);
 #define IOP13XX_PMMR_SIZE                 0x00080000
 
 /*=================== Defines for Platform Devices =====================*/
-#define IOP13XX_UART0_PHYS  (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300)
-#define IOP13XX_UART1_PHYS  (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340)
-#define IOP13XX_UART0_VIRT  (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300)
-#define IOP13XX_UART1_VIRT  (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340)
+#define IOP13XX_UART0_PHYS  (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002300)
+#define IOP13XX_UART1_PHYS  (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002340)
+#define IOP13XX_UART0_VIRT  (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002300)
+#define IOP13XX_UART1_VIRT  (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002340)
 
 #define IOP13XX_I2C0_PHYS   (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
 #define IOP13XX_I2C1_PHYS   (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
index 1afa99e..7c032d0 100644 (file)
 #define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE)
 #define IOP13XX_PMMR_P_END   (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE)
 
-static inline dma_addr_t __virt_to_lbus(unsigned long x)
+static inline dma_addr_t __virt_to_lbus(void __iomem *x)
 {
        return x + IOP13XX_PMMR_PHYS_MEM_BASE - IOP13XX_PMMR_VIRT_MEM_BASE;
 }
 
-static inline unsigned long __lbus_to_virt(dma_addr_t x)
+static inline void __iomem *__lbus_to_virt(dma_addr_t x)
 {
        return x + IOP13XX_PMMR_VIRT_MEM_BASE - IOP13XX_PMMR_PHYS_MEM_BASE;
 }
@@ -38,23 +38,23 @@ static inline unsigned long __lbus_to_virt(dma_addr_t x)
 
 #define __arch_dma_to_virt(dev, addr)                                  \
        ({                                                              \
-               unsigned long __virt;                                   \
+               void * __virt;                                          \
                dma_addr_t __dma = addr;                                \
                if (is_lbus_device(dev) && __is_lbus_dma(__dma))        \
                        __virt = __lbus_to_virt(__dma);                 \
                else                                                    \
-                       __virt = __phys_to_virt(__dma);                 \
-               (void *)__virt;                                         \
+                       __virt = (void *)__phys_to_virt(__dma);         \
+               __virt;                                                 \
        })
 
 #define __arch_virt_to_dma(dev, addr)                                  \
        ({                                                              \
-               unsigned long __virt = (unsigned long)addr;             \
+               void * __virt = addr;                                   \
                dma_addr_t __dma;                                       \
                if (is_lbus_device(dev) && __is_lbus_virt(__virt))      \
                        __dma = __virt_to_lbus(__virt);                 \
                else                                                    \
-                       __dma = __virt_to_phys(__virt);                 \
+                       __dma = __virt_to_phys((unsigned long)__virt);  \
                __dma;                                                  \
        })
 
index 3c36419..183dc8b 100644 (file)
 
 #include "pci.h"
 
-void * __iomem __iop13xx_io(unsigned long io_addr)
-{
-       void __iomem * io_virt;
-
-       switch (io_addr) {
-       case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA:
-               io_virt = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(io_addr);
-               break;
-       case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA:
-               io_virt = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(io_addr);
-               break;
-       default:
-               BUG();
-       }
-
-       return io_virt;
-}
-EXPORT_SYMBOL(__iop13xx_io);
-
 static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
        size_t size, unsigned int mtype, void *caller)
 {
@@ -52,14 +33,14 @@ static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
                if (unlikely(!iop13xx_atux_mem_base))
                        retval = NULL;
                else
-                       retval = (void *)(iop13xx_atux_mem_base +
+                       retval = (iop13xx_atux_mem_base +
                                 (cookie - IOP13XX_PCIX_LOWER_MEM_RA));
                break;
        case IOP13XX_PCIE_LOWER_MEM_RA ... IOP13XX_PCIE_UPPER_MEM_RA:
                if (unlikely(!iop13xx_atue_mem_base))
                        retval = NULL;
                else
-                       retval = (void *)(iop13xx_atue_mem_base +
+                       retval = (iop13xx_atue_mem_base +
                                 (cookie - IOP13XX_PCIE_LOWER_MEM_RA));
                break;
        case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA:
@@ -67,14 +48,8 @@ static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
                                       (cookie - IOP13XX_PBI_LOWER_MEM_RA),
                                       size, mtype, __builtin_return_address(0));
                break;
-       case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA:
-               retval = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(cookie);
-               break;
-       case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA:
-               retval = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(cookie);
-               break;
        case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA:
-               retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
+               retval = IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
                break;
        default:
                retval = __arm_ioremap_caller(cookie, size, mtype,
@@ -99,9 +74,7 @@ static void __iop13xx_iounmap(volatile void __iomem *addr)
                    goto skip;
 
        switch ((u32) addr) {
-       case IOP13XX_PCIE_LOWER_IO_VA ... IOP13XX_PCIE_UPPER_IO_VA:
-       case IOP13XX_PCIX_LOWER_IO_VA ... IOP13XX_PCIX_UPPER_IO_VA:
-       case IOP13XX_PMMR_VIRT_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_VA:
+       case (u32)IOP13XX_PMMR_VIRT_MEM_BASE ... (u32)IOP13XX_PMMR_UPPER_MEM_VA:
                goto skip;
        }
        __iounmap(addr);
index 861cb12..9082b84 100644 (file)
@@ -36,8 +36,8 @@ u32 iop13xx_atux_pmmr_offset; /* This offset can change based on strapping */
 u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */
 static struct pci_bus *pci_bus_atux = 0;
 static struct pci_bus *pci_bus_atue = 0;
-u32 iop13xx_atue_mem_base;
-u32 iop13xx_atux_mem_base;
+void __iomem *iop13xx_atue_mem_base;
+void __iomem *iop13xx_atux_mem_base;
 size_t iop13xx_atue_mem_size;
 size_t iop13xx_atux_mem_size;
 
@@ -88,8 +88,7 @@ void iop13xx_map_pci_memory(void)
                                }
 
                                if (end) {
-                                       iop13xx_atux_mem_base =
-                                       (u32) __arm_ioremap_pfn(
+                                       iop13xx_atux_mem_base = __arm_ioremap_pfn(
                                        __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA)
                                        , 0, iop13xx_atux_mem_size, MT_DEVICE);
                                        if (!iop13xx_atux_mem_base) {
@@ -99,7 +98,7 @@ void iop13xx_map_pci_memory(void)
                                        }
                                } else
                                        iop13xx_atux_mem_size = 0;
-                               PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
+                               PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n",
                                __func__, atu, iop13xx_atux_mem_size,
                                iop13xx_atux_mem_base);
                                break;
@@ -114,8 +113,7 @@ void iop13xx_map_pci_memory(void)
                                }
 
                                if (end) {
-                                       iop13xx_atue_mem_base =
-                                       (u32) __arm_ioremap_pfn(
+                                       iop13xx_atue_mem_base = __arm_ioremap_pfn(
                                        __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA)
                                        , 0, iop13xx_atue_mem_size, MT_DEVICE);
                                        if (!iop13xx_atue_mem_base) {
@@ -125,13 +123,13 @@ void iop13xx_map_pci_memory(void)
                                        }
                                } else
                                        iop13xx_atue_mem_size = 0;
-                               PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
+                               PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n",
                                __func__, atu, iop13xx_atue_mem_size,
                                iop13xx_atue_mem_base);
                                break;
                        }
 
-                       printk("%s: Initialized (%uM @ resource/virtual: %08lx/%08x)\n",
+                       printk("%s: Initialized (%uM @ resource/virtual: %08lx/%p)\n",
                        atu ? "ATUE" : "ATUX",
                        (atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) /
                        SZ_1M,
@@ -970,7 +968,6 @@ void __init iop13xx_pci_init(void)
        __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR);
 
        /* Setup the Min Address for PCI memory... */
-       pcibios_min_io = 0;
        pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA;
 
        /* if Linux is given control of an ATU
@@ -1003,7 +1000,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
        if (nr > 1)
                return 0;
 
-       res = kcalloc(2, sizeof(struct resource), GFP_KERNEL);
+       res = kzalloc(sizeof(struct resource), GFP_KERNEL);
        if (!res)
                panic("PCI: unable to alloc resources");
 
@@ -1042,17 +1039,13 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
                                  << IOP13XX_ATUX_PCIXSR_FUNC_NUM;
                __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR);
 
-               res[0].start = IOP13XX_PCIX_LOWER_IO_PA + IOP13XX_PCIX_IO_BUS_OFFSET;
-               res[0].end   = IOP13XX_PCIX_UPPER_IO_PA;
-               res[0].name  = "IQ81340 ATUX PCI I/O Space";
-               res[0].flags = IORESOURCE_IO;
+               pci_ioremap_io(0, IOP13XX_PCIX_LOWER_IO_PA);
 
-               res[1].start = IOP13XX_PCIX_LOWER_MEM_RA;
-               res[1].end   = IOP13XX_PCIX_UPPER_MEM_RA;
-               res[1].name  = "IQ81340 ATUX PCI Memory Space";
-               res[1].flags = IORESOURCE_MEM;
+               res->start = IOP13XX_PCIX_LOWER_MEM_RA;
+               res->end   = IOP13XX_PCIX_UPPER_MEM_RA;
+               res->name  = "IQ81340 ATUX PCI Memory Space";
+               res->flags = IORESOURCE_MEM;
                sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET;
-               sys->io_offset = IOP13XX_PCIX_LOWER_IO_PA;
                break;
        case IOP13XX_INIT_ATU_ATUE:
                /* Note: the function number field in the PCSR is ro */
@@ -1063,17 +1056,13 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
 
                __raw_writel(pcsr, IOP13XX_ATUE_PCSR);
 
-               res[0].start = IOP13XX_PCIE_LOWER_IO_PA + IOP13XX_PCIE_IO_BUS_OFFSET;
-               res[0].end   = IOP13XX_PCIE_UPPER_IO_PA;
-               res[0].name  = "IQ81340 ATUE PCI I/O Space";
-               res[0].flags = IORESOURCE_IO;
+               pci_ioremap_io(SZ_64K, IOP13XX_PCIE_LOWER_IO_PA);
 
-               res[1].start = IOP13XX_PCIE_LOWER_MEM_RA;
-               res[1].end   = IOP13XX_PCIE_UPPER_MEM_RA;
-               res[1].name  = "IQ81340 ATUE PCI Memory Space";
-               res[1].flags = IORESOURCE_MEM;
+               res->start = IOP13XX_PCIE_LOWER_MEM_RA;
+               res->end   = IOP13XX_PCIE_UPPER_MEM_RA;
+               res->name  = "IQ81340 ATUE PCI Memory Space";
+               res->flags = IORESOURCE_MEM;
                sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET;
-               sys->io_offset = IOP13XX_PCIE_LOWER_IO_PA;
                sys->map_irq = iop13xx_pcie_map_irq;
                break;
        default:
@@ -1081,11 +1070,9 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
                return 0;
        }
 
-       request_resource(&ioport_resource, &res[0]);
-       request_resource(&iomem_resource, &res[1]);
+       request_resource(&iomem_resource, res);
 
-       pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
-       pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
+       pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
 
        return 1;
 }
index c70cf5b..d45a80b 100644 (file)
@@ -1,6 +1,6 @@
 #include <linux/types.h>
 
-extern u32 iop13xx_atue_mem_base;
-extern u32 iop13xx_atux_mem_base;
+extern void __iomem *iop13xx_atue_mem_base;
+extern void __iomem *iop13xx_atux_mem_base;
 extern size_t iop13xx_atue_mem_size;
 extern size_t iop13xx_atux_mem_size;
index daabb1f..3181f61 100644 (file)
  */
 static struct map_desc iop13xx_std_desc[] __initdata = {
        {    /* mem mapped registers */
-               .virtual = IOP13XX_PMMR_VIRT_MEM_BASE,
+               .virtual = (unsigned long)IOP13XX_PMMR_VIRT_MEM_BASE,
                .pfn     = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
                .length  = IOP13XX_PMMR_SIZE,
                .type    = MT_DEVICE,
-       }, { /* PCIE IO space */
-               .virtual = IOP13XX_PCIE_LOWER_IO_VA,
-               .pfn     = __phys_to_pfn(IOP13XX_PCIE_LOWER_IO_PA),
-               .length  = IOP13XX_PCIX_IO_WINDOW_SIZE,
-               .type    = MT_DEVICE,
-       }, { /* PCIX IO space */
-               .virtual = IOP13XX_PCIX_LOWER_IO_VA,
-               .pfn     = __phys_to_pfn(IOP13XX_PCIX_LOWER_IO_PA),
-               .length  = IOP13XX_PCIX_IO_WINDOW_SIZE,
-               .type    = MT_DEVICE,
        },
 };
 
@@ -81,8 +71,8 @@ static struct resource iop13xx_uart1_resources[] = {
 
 static struct plat_serial8250_port iop13xx_uart0_data[] = {
        {
-       .membase     = (char*)(IOP13XX_UART0_VIRT),
-       .mapbase     = (IOP13XX_UART0_PHYS),
+       .membase     = IOP13XX_UART0_VIRT,
+       .mapbase     = IOP13XX_UART0_PHYS,
        .irq         = IRQ_IOP13XX_UART0,
        .uartclk     = IOP13XX_UART_XTAL,
        .regshift    = 2,
@@ -94,8 +84,8 @@ static struct plat_serial8250_port iop13xx_uart0_data[] = {
 
 static struct plat_serial8250_port iop13xx_uart1_data[] = {
        {
-       .membase     = (char*)(IOP13XX_UART1_VIRT),
-       .mapbase     = (IOP13XX_UART1_PHYS),
+       .membase     = IOP13XX_UART1_VIRT,
+       .mapbase     = IOP13XX_UART1_PHYS,
        .irq         = IRQ_IOP13XX_UART1,
        .uartclk     = IOP13XX_UART_XTAL,
        .regshift    = 2,
index c15a100..02e20c3 100644 (file)
@@ -183,7 +183,7 @@ static struct i2c_board_info __initdata glantank_i2c_devices[] = {
 
 static void glantank_power_off(void)
 {
-       __raw_writeb(0x01, 0xfe8d0004);
+       __raw_writeb(0x01, IOMEM(0xfe8d0004));
 
        while (1)
                ;
diff --git a/arch/arm/mach-iop32x/include/mach/io.h b/arch/arm/mach-iop32x/include/mach/io.h
deleted file mode 100644 (file)
index e2ada26..0000000
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-iop32x/include/mach/io.h
- *
- * Copyright (C) 2001 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __IO_H
-#define __IO_H
-
-#include <asm/hardware/iop3xx.h>
-
-#define IO_SPACE_LIMIT         0xffffffff
-#define __io(p)                ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
-
-#endif
diff --git a/arch/arm/mach-iop33x/include/mach/io.h b/arch/arm/mach-iop33x/include/mach/io.h
deleted file mode 100644 (file)
index f7c1b65..0000000
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-iop33x/include/mach/io.h
- *
- * Copyright (C) 2001  MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __IO_H
-#define __IO_H
-
-#include <asm/hardware/iop3xx.h>
-
-#define IO_SPACE_LIMIT         0xffffffff
-#define __io(p)                ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
-
-#endif
index a9f8094..fdf91a1 100644 (file)
@@ -53,24 +53,24 @@ static struct clock_event_device clockevent_ixp4xx;
  *************************************************************************/
 static struct map_desc ixp4xx_io_desc[] __initdata = {
        {       /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
-               .virtual        = IXP4XX_PERIPHERAL_BASE_VIRT,
+               .virtual        = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT,
                .pfn            = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
                .length         = IXP4XX_PERIPHERAL_REGION_SIZE,
                .type           = MT_DEVICE
        }, {    /* Expansion Bus Config Registers */
-               .virtual        = IXP4XX_EXP_CFG_BASE_VIRT,
+               .virtual        = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT,
                .pfn            = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
                .length         = IXP4XX_EXP_CFG_REGION_SIZE,
                .type           = MT_DEVICE
        }, {    /* PCI Registers */
-               .virtual        = IXP4XX_PCI_CFG_BASE_VIRT,
+               .virtual        = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT,
                .pfn            = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
                .length         = IXP4XX_PCI_CFG_REGION_SIZE,
                .type           = MT_DEVICE
        },
 #ifdef CONFIG_DEBUG_LL
        {       /* Debug UART mapping */
-               .virtual        = IXP4XX_DEBUG_UART_BASE_VIRT,
+               .virtual        = (unsigned long)IXP4XX_DEBUG_UART_BASE_VIRT,
                .pfn            = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
                .length         = IXP4XX_DEBUG_UART_REGION_SIZE,
                .type           = MT_DEVICE
index b2ef65d..ebc0ba3 100644 (file)
@@ -14,6 +14,7 @@
 #ifndef __ASM_ARCH_CPU_H__
 #define __ASM_ARCH_CPU_H__
 
+#include <linux/io.h>
 #include <asm/cputype.h>
 
 /* Processor id value in CP15 Register 0 */
@@ -37,7 +38,7 @@
 
 static inline u32 ixp4xx_read_feature_bits(void)
 {
-       u32 val = ~*IXP4XX_EXP_CFG2;
+       u32 val = ~__raw_readl(IXP4XX_EXP_CFG2);
 
        if (cpu_is_ixp42x_rev_a0())
                return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP |
@@ -51,7 +52,7 @@ static inline u32 ixp4xx_read_feature_bits(void)
 
 static inline void ixp4xx_write_feature_bits(u32 value)
 {
-       *IXP4XX_EXP_CFG2 = ~value;
+       __raw_writel(~value, IXP4XX_EXP_CFG2);
 }
 
 #endif  /* _ASM_ARCH_CPU_H */
index 97c530f..eb68b61 100644 (file)
  * Expansion BUS Configuration registers
  */
 #define IXP4XX_EXP_CFG_BASE_PHYS       (0xC4000000)
-#define IXP4XX_EXP_CFG_BASE_VIRT       (0xFFBFE000)
+#define IXP4XX_EXP_CFG_BASE_VIRT       IOMEM(0xFFBFE000)
 #define IXP4XX_EXP_CFG_REGION_SIZE     (0x00001000)
 
 /*
  * PCI Config registers
  */
 #define IXP4XX_PCI_CFG_BASE_PHYS       (0xC0000000)
-#define        IXP4XX_PCI_CFG_BASE_VIRT        (0xFFBFF000)
+#define        IXP4XX_PCI_CFG_BASE_VIRT        IOMEM(0xFFBFF000)
 #define IXP4XX_PCI_CFG_REGION_SIZE     (0x00001000)
 
 /*
  * Peripheral space
  */
 #define IXP4XX_PERIPHERAL_BASE_PHYS    (0xC8000000)
-#define IXP4XX_PERIPHERAL_BASE_VIRT    (0xFFBEB000)
+#define IXP4XX_PERIPHERAL_BASE_VIRT    IOMEM(0xFFBEB000)
 #define IXP4XX_PERIPHERAL_REGION_SIZE  (0x00013000)
 
 /*
@@ -73,7 +73,7 @@
  * aligned so that it * can be used with the low-level debug code.
  */
 #define        IXP4XX_DEBUG_UART_BASE_PHYS     (0xC8000000)
-#define        IXP4XX_DEBUG_UART_BASE_VIRT     (0xffb00000)
+#define        IXP4XX_DEBUG_UART_BASE_VIRT     IOMEM(0xffb00000)
 #define        IXP4XX_DEBUG_UART_REGION_SIZE   (0x00001000)
 
 #define IXP4XX_EXP_CS0_OFFSET  0x00
@@ -92,7 +92,7 @@
 /*
  * Expansion Bus Controller registers.
  */
-#define IXP4XX_EXP_REG(x) ((volatile u32 *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))
+#define IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))
 
 #define IXP4XX_EXP_CS0      IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET)
 #define IXP4XX_EXP_CS1      IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)
index 1201191..3f7b05f 100644 (file)
  ****************************************************************************/
 static struct map_desc kirkwood_io_desc[] __initdata = {
        {
-               .virtual        = KIRKWOOD_PCIE_IO_VIRT_BASE,
-               .pfn            = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
-               .length         = KIRKWOOD_PCIE_IO_SIZE,
-               .type           = MT_DEVICE,
-       }, {
-               .virtual        = KIRKWOOD_PCIE1_IO_VIRT_BASE,
-               .pfn            = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
-               .length         = KIRKWOOD_PCIE1_IO_SIZE,
-               .type           = MT_DEVICE,
-       }, {
                .virtual        = KIRKWOOD_REGS_VIRT_BASE,
                .pfn            = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
                .length         = KIRKWOOD_REGS_SIZE,
diff --git a/arch/arm/mach-kirkwood/include/mach/io.h b/arch/arm/mach-kirkwood/include/mach/io.h
deleted file mode 100644 (file)
index 5d0ab61..0000000
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/include/mach/io.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#include "kirkwood.h"
-
-#define IO_SPACE_LIMIT         0xffffffff
-
-static inline void __iomem *__io(unsigned long addr)
-{
-       return (void __iomem *)((addr - KIRKWOOD_PCIE_IO_BUS_BASE)
-                                       + KIRKWOOD_PCIE_IO_VIRT_BASE);
-}
-
-#define __io(a)                        __io(a)
-
-#endif
index c5b6851..af4f000 100644 (file)
 #define KIRKWOOD_NAND_MEM_SIZE         SZ_1K
 
 #define KIRKWOOD_PCIE1_IO_PHYS_BASE    0xf3000000
-#define KIRKWOOD_PCIE1_IO_VIRT_BASE    0xfef00000
-#define KIRKWOOD_PCIE1_IO_BUS_BASE     0x00100000
-#define KIRKWOOD_PCIE1_IO_SIZE         SZ_1M
+#define KIRKWOOD_PCIE1_IO_BUS_BASE     0x00010000
+#define KIRKWOOD_PCIE1_IO_SIZE         SZ_64K
 
 #define KIRKWOOD_PCIE_IO_PHYS_BASE     0xf2000000
-#define KIRKWOOD_PCIE_IO_VIRT_BASE     0xfee00000
 #define KIRKWOOD_PCIE_IO_BUS_BASE      0x00000000
-#define KIRKWOOD_PCIE_IO_SIZE          SZ_1M
+#define KIRKWOOD_PCIE_IO_SIZE          SZ_64K
 
 #define KIRKWOOD_REGS_PHYS_BASE                0xf1000000
 #define KIRKWOOD_REGS_VIRT_BASE                0xfed00000
index 6e8b2ef..532d8ac 100644 (file)
@@ -56,7 +56,7 @@ struct pcie_port {
        void __iomem            *base;
        spinlock_t              conf_lock;
        int                     irq;
-       struct resource         res[2];
+       struct resource         res;
 };
 
 static int pcie_port_map[2];
@@ -137,20 +137,12 @@ static void __init pcie0_ioresources_init(struct pcie_port *pp)
        pp->irq = IRQ_KIRKWOOD_PCIE;
 
        /*
-        * IORESOURCE_IO
-        */
-       pp->res[0].name = "PCIe 0 I/O Space";
-       pp->res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
-       pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
-       pp->res[0].flags = IORESOURCE_IO;
-
-       /*
         * IORESOURCE_MEM
         */
-       pp->res[1].name = "PCIe 0 MEM";
-       pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
-       pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
-       pp->res[1].flags = IORESOURCE_MEM;
+       pp->res.name = "PCIe 0 MEM";
+       pp->res.start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
+       pp->res.end = pp->res.start + KIRKWOOD_PCIE_MEM_SIZE - 1;
+       pp->res.flags = IORESOURCE_MEM;
 }
 
 static void __init pcie1_ioresources_init(struct pcie_port *pp)
@@ -159,20 +151,12 @@ static void __init pcie1_ioresources_init(struct pcie_port *pp)
        pp->irq = IRQ_KIRKWOOD_PCIE1;
 
        /*
-        * IORESOURCE_IO
-        */
-       pp->res[0].name = "PCIe 1 I/O Space";
-       pp->res[0].start = KIRKWOOD_PCIE1_IO_BUS_BASE;
-       pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
-       pp->res[0].flags = IORESOURCE_IO;
-
-       /*
         * IORESOURCE_MEM
         */
-       pp->res[1].name = "PCIe 1 MEM";
-       pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
-       pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
-       pp->res[1].flags = IORESOURCE_MEM;
+       pp->res.name = "PCIe 1 MEM";
+       pp->res.start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
+       pp->res.end = pp->res.start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
+       pp->res.flags = IORESOURCE_MEM;
 }
 
 static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
@@ -197,23 +181,21 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
        case 0:
                kirkwood_enable_pcie_clk("0");
                pcie0_ioresources_init(pp);
+               pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE_IO_PHYS_BASE);
                break;
        case 1:
                kirkwood_enable_pcie_clk("1");
                pcie1_ioresources_init(pp);
+               pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE1_IO_PHYS_BASE);
                break;
        default:
                panic("PCIe setup: invalid controller %d", index);
        }
 
-       if (request_resource(&ioport_resource, &pp->res[0]))
-               panic("Request PCIe%d IO resource failed\n", index);
-       if (request_resource(&iomem_resource, &pp->res[1]))
+       if (request_resource(&iomem_resource, &pp->res))
                panic("Request PCIe%d Memory resource failed\n", index);
 
-       sys->io_offset = 0;
-       pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
-       pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
+       pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
 
        /*
         * Generic PCIe unit setup.
index 7f3f240..ddb2422 100644 (file)
@@ -36,7 +36,7 @@
 
 static struct __initdata map_desc ks8695_io_desc[] = {
        {
-               .virtual        = KS8695_IO_VA,
+               .virtual        = (unsigned long)KS8695_IO_VA,
                .pfn            = __phys_to_pfn(KS8695_IO_PA),
                .length         = KS8695_IO_SIZE,
                .type           = MT_DEVICE,
index 5e0c388..5090338 100644 (file)
@@ -33,7 +33,7 @@
  * head debug code as the initial MMU setup only deals in L1 sections.
  */
 #define KS8695_IO_PA           0x03F00000
-#define KS8695_IO_VA           0xF0000000
+#define KS8695_IO_VA           IOMEM(0xF0000000)
 #define KS8695_IO_SIZE         SZ_1M
 
 #define KS8695_PCIMEM_PA       0x60000000
diff --git a/arch/arm/mach-ks8695/include/mach/regs-timer.h b/arch/arm/mach-ks8695/include/mach/regs-timer.h
deleted file mode 100644 (file)
index e620cda..0000000
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * arch/arm/mach-ks8695/include/mach/regs-timer.h
- *
- * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
- * Copyright (C) 2006 Simtec Electronics
- *
- * KS8695 - Timer registers and bit definitions.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef KS8695_TIMER_H
-#define KS8695_TIMER_H
-
-#define KS8695_TMR_OFFSET      (0xF0000 + 0xE400)
-#define KS8695_TMR_VA          (KS8695_IO_VA + KS8695_TMR_OFFSET)
-#define KS8695_TMR_PA          (KS8695_IO_PA + KS8695_TMR_OFFSET)
-
-
-/*
- * Timer registers
- */
-#define KS8695_TMCON           (0x00)          /* Timer Control Register */
-#define KS8695_T1TC            (0x04)          /* Timer 1 Timeout Count Register */
-#define KS8695_T0TC            (0x08)          /* Timer 0 Timeout Count Register */
-#define KS8695_T1PD            (0x0C)          /* Timer 1 Pulse Count Register */
-#define KS8695_T0PD            (0x10)          /* Timer 0 Pulse Count Register */
-
-
-/* Timer Control Register */
-#define TMCON_T1EN             (1 << 1)        /* Timer 1 Enable */
-#define TMCON_T0EN             (1 << 0)        /* Timer 0 Enable */
-
-/* Timer0 Timeout Counter Register */
-#define T0TC_WATCHDOG          (0xff)          /* Enable watchdog mode */
-
-
-#endif
index 9495cb4..8879d61 100644 (file)
 
 static void putc(char c)
 {
-       while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE))
+       while (!(__raw_readl((void __iomem*)KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE))
                barrier();
 
-       __raw_writel(c, KS8695_UART_PA + KS8695_URTH);
+       __raw_writel(c, (void __iomem*)KS8695_UART_PA + KS8695_URTH);
 }
 
 static inline void flush(void)
 {
-       while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTE))
+       while (!(__raw_readl((void __iomem*)KS8695_UART_PA + KS8695_URLS) & URLS_URTE))
                barrier();
 }
 
index ec783a3..46c84bc 100644 (file)
 #include <linux/kernel.h>
 #include <linux/sched.h>
 #include <linux/io.h>
+#include <linux/clockchips.h>
 
 #include <asm/mach/time.h>
 #include <asm/system_misc.h>
 
-#include <mach/regs-timer.h>
 #include <mach/regs-irq.h>
 
 #include "generic.h"
 
+#define KS8695_TMR_OFFSET      (0xF0000 + 0xE400)
+#define KS8695_TMR_VA          (KS8695_IO_VA + KS8695_TMR_OFFSET)
+#define KS8695_TMR_PA          (KS8695_IO_PA + KS8695_TMR_OFFSET)
+
 /*
- * Returns number of ms since last clock interrupt.  Note that interrupts
- * will have been disabled by do_gettimeoffset()
+ * Timer registers
  */
-static unsigned long ks8695_gettimeoffset (void)
+#define KS8695_TMCON           (0x00)          /* Timer Control Register */
+#define KS8695_T1TC            (0x04)          /* Timer 1 Timeout Count Register */
+#define KS8695_T0TC            (0x08)          /* Timer 0 Timeout Count Register */
+#define KS8695_T1PD            (0x0C)          /* Timer 1 Pulse Count Register */
+#define KS8695_T0PD            (0x10)          /* Timer 0 Pulse Count Register */
+
+/* Timer Control Register */
+#define TMCON_T1EN             (1 << 1)        /* Timer 1 Enable */
+#define TMCON_T0EN             (1 << 0)        /* Timer 0 Enable */
+
+/* Timer0 Timeout Counter Register */
+#define T0TC_WATCHDOG          (0xff)          /* Enable watchdog mode */
+
+static void ks8695_set_mode(enum clock_event_mode mode,
+                           struct clock_event_device *evt)
 {
-       unsigned long elapsed, tick2, intpending;
+       u32 tmcon;
 
-       /*
-        * Get the current number of ticks.  Note that there is a race
-        * condition between us reading the timer and checking for an
-        * interrupt.  We solve this by ensuring that the counter has not
-        * reloaded between our two reads.
-        */
-       elapsed = __raw_readl(KS8695_TMR_VA + KS8695_T1TC) + __raw_readl(KS8695_TMR_VA + KS8695_T1PD);
-       do {
-               tick2 = elapsed;
-               intpending = __raw_readl(KS8695_IRQ_VA + KS8695_INTST) & (1 << KS8695_IRQ_TIMER1);
-               elapsed = __raw_readl(KS8695_TMR_VA + KS8695_T1TC) + __raw_readl(KS8695_TMR_VA + KS8695_T1PD);
-       } while (elapsed > tick2);
-
-       /* Convert to number of ticks expired (not remaining) */
-       elapsed = (CLOCK_TICK_RATE / HZ) - elapsed;
-
-       /* Is interrupt pending?  If so, then timer has been reloaded already. */
-       if (intpending)
-               elapsed += (CLOCK_TICK_RATE / HZ);
-
-       /* Convert ticks to usecs */
-       return (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH;
+       if (mode == CLOCK_EVT_FEAT_PERIODIC) {
+               u32 rate = DIV_ROUND_CLOSEST(KS8695_CLOCK_RATE, HZ);
+               u32 half = DIV_ROUND_CLOSEST(rate, 2);
+
+               /* Disable timer 1 */
+               tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
+               tmcon &= ~TMCON_T1EN;
+               writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
+
+               /* Both registers need to count down */
+               writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC);
+               writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD);
+
+               /* Re-enable timer1 */
+               tmcon |= TMCON_T1EN;
+               writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
+       }
 }
 
+static int ks8695_set_next_event(unsigned long cycles,
+                                struct clock_event_device *evt)
+
+{
+       u32 half = DIV_ROUND_CLOSEST(cycles, 2);
+       u32 tmcon;
+
+       /* Disable timer 1 */
+       tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
+       tmcon &= ~TMCON_T1EN;
+       writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
+
+       /* Both registers need to count down */
+       writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC);
+       writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD);
+
+       /* Re-enable timer1 */
+       tmcon |= TMCON_T1EN;
+       writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
+
+       return 0;
+}
+
+static struct clock_event_device clockevent_ks8695 = {
+       .name           = "ks8695_t1tc",
+       .rating         = 300, /* Reasonably fast and accurate clock event */
+       .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
+       .set_next_event = ks8695_set_next_event,
+       .set_mode       = ks8695_set_mode,
+};
+
 /*
  * IRQ handler for the timer.
  */
 static irqreturn_t ks8695_timer_interrupt(int irq, void *dev_id)
 {
-       timer_tick();
+       struct clock_event_device *evt = &clockevent_ks8695;
+
+       evt->event_handler(evt);
        return IRQ_HANDLED;
 }
 
@@ -83,18 +128,22 @@ static struct irqaction ks8695_timer_irq = {
 
 static void ks8695_timer_setup(void)
 {
-       unsigned long tmout = CLOCK_TICK_RATE / HZ;
        unsigned long tmcon;
 
-       /* disable timer1 */
-       tmcon = __raw_readl(KS8695_TMR_VA + KS8695_TMCON);
-       __raw_writel(tmcon & ~TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON);
-
-       __raw_writel(tmout / 2, KS8695_TMR_VA + KS8695_T1TC);
-       __raw_writel(tmout / 2, KS8695_TMR_VA + KS8695_T1PD);
+       /* Disable timer 0 and 1 */
+       tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
+       tmcon &= ~TMCON_T0EN;
+       tmcon &= ~TMCON_T1EN;
+       writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
 
-       /* re-enable timer1 */
-       __raw_writel(tmcon | TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON);
+       /*
+        * Use timer 1 to fire IRQs on the timeline, minimum 2 cycles
+        * (one on each counter) maximum 2*2^32, but the API will only
+        * accept up to a 32bit full word (0xFFFFFFFFU).
+        */
+       clockevents_config_and_register(&clockevent_ks8695,
+                                       KS8695_CLOCK_RATE, 2,
+                                       0xFFFFFFFFU);
 }
 
 static void __init ks8695_timer_init (void)
@@ -107,8 +156,6 @@ static void __init ks8695_timer_init (void)
 
 struct sys_timer ks8695_timer = {
        .init           = ks8695_timer_init,
-       .offset         = ks8695_gettimeoffset,
-       .resume         = ks8695_timer_setup,
 };
 
 void ks8695_restart(char mode, const char *cmd)
@@ -119,12 +166,12 @@ void ks8695_restart(char mode, const char *cmd)
                soft_restart(0);
 
        /* disable timer0 */
-       reg = __raw_readl(KS8695_TMR_VA + KS8695_TMCON);
-       __raw_writel(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
+       reg = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
+       writel_relaxed(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
 
        /* enable watchdog mode */
-       __raw_writel((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC);
+       writel_relaxed((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC);
 
        /* re-enable timer0 */
-       __raw_writel(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
+       writel_relaxed(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
 }
index a48dc2d..0d4db8c 100644 (file)
@@ -177,25 +177,25 @@ u32 clk_get_pclk_div(void)
 
 static struct map_desc lpc32xx_io_desc[] __initdata = {
        {
-               .virtual        = IO_ADDRESS(LPC32XX_AHB0_START),
+               .virtual        = (unsigned long)IO_ADDRESS(LPC32XX_AHB0_START),
                .pfn            = __phys_to_pfn(LPC32XX_AHB0_START),
                .length         = LPC32XX_AHB0_SIZE,
                .type           = MT_DEVICE
        },
        {
-               .virtual        = IO_ADDRESS(LPC32XX_AHB1_START),
+               .virtual        = (unsigned long)IO_ADDRESS(LPC32XX_AHB1_START),
                .pfn            = __phys_to_pfn(LPC32XX_AHB1_START),
                .length         = LPC32XX_AHB1_SIZE,
                .type           = MT_DEVICE
        },
        {
-               .virtual        = IO_ADDRESS(LPC32XX_FABAPB_START),
+               .virtual        = (unsigned long)IO_ADDRESS(LPC32XX_FABAPB_START),
                .pfn            = __phys_to_pfn(LPC32XX_FABAPB_START),
                .length         = LPC32XX_FABAPB_SIZE,
                .type           = MT_DEVICE
        },
        {
-               .virtual        = IO_ADDRESS(LPC32XX_IRAM_BASE),
+               .virtual        = (unsigned long)IO_ADDRESS(LPC32XX_IRAM_BASE),
                .pfn            = __phys_to_pfn(LPC32XX_IRAM_BASE),
                .length         = (LPC32XX_IRAM_BANK_SIZE * 2),
                .type           = MT_DEVICE
index 33e1dde..69065de 100644 (file)
@@ -25,7 +25,7 @@
 /*
  * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0
  */
-#define IO_ADDRESS(x)  (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
+#define IO_ADDRESS(x)  IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
                         IO_BASE)
 
 #define io_p2v(x)      ((void __iomem *) (unsigned long) IO_ADDRESS(x))
index b786f7e..095c155 100644 (file)
@@ -2,13 +2,19 @@
 # Makefile for Marvell's PXA168 processors line
 #
 
-obj-y                          += common.o clock.o devices.o time.o irq.o
+obj-y                          += common.o devices.o time.o irq.o
 
 # SoC support
 obj-$(CONFIG_CPU_PXA168)       += pxa168.o
 obj-$(CONFIG_CPU_PXA910)       += pxa910.o
 obj-$(CONFIG_CPU_MMP2)         += mmp2.o sram.o
 
+ifeq ($(CONFIG_COMMON_CLK), )
+obj-y                          += clock.o
+obj-$(CONFIG_CPU_PXA168)       += clock-pxa168.o
+obj-$(CONFIG_CPU_PXA910)       += clock-pxa910.o
+obj-$(CONFIG_CPU_MMP2)         += clock-mmp2.o
+endif
 ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_CPU_PXA910)       += pm-pxa910.o
 obj-$(CONFIG_CPU_MMP2)         += pm-mmp2.o
diff --git a/arch/arm/mach-mmp/clock-mmp2.c b/arch/arm/mach-mmp/clock-mmp2.c
new file mode 100644 (file)
index 0000000..21d2200
--- /dev/null
@@ -0,0 +1,111 @@
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+
+#include <mach/addr-map.h>
+
+#include "common.h"
+#include "clock.h"
+
+/*
+ * APB Clock register offsets for MMP2
+ */
+#define APBC_RTC       APBC_REG(0x000)
+#define APBC_TWSI1     APBC_REG(0x004)
+#define APBC_TWSI2     APBC_REG(0x008)
+#define APBC_TWSI3     APBC_REG(0x00c)
+#define APBC_TWSI4     APBC_REG(0x010)
+#define APBC_KPC       APBC_REG(0x018)
+#define APBC_UART1     APBC_REG(0x02c)
+#define APBC_UART2     APBC_REG(0x030)
+#define APBC_UART3     APBC_REG(0x034)
+#define APBC_GPIO      APBC_REG(0x038)
+#define APBC_PWM0      APBC_REG(0x03c)
+#define APBC_PWM1      APBC_REG(0x040)
+#define APBC_PWM2      APBC_REG(0x044)
+#define APBC_PWM3      APBC_REG(0x048)
+#define APBC_SSP0      APBC_REG(0x04c)
+#define APBC_SSP1      APBC_REG(0x050)
+#define APBC_SSP2      APBC_REG(0x054)
+#define APBC_SSP3      APBC_REG(0x058)
+#define APBC_SSP4      APBC_REG(0x05c)
+#define APBC_SSP5      APBC_REG(0x060)
+#define APBC_TWSI5     APBC_REG(0x07c)
+#define APBC_TWSI6     APBC_REG(0x080)
+#define APBC_UART4     APBC_REG(0x088)
+
+#define APMU_USB       APMU_REG(0x05c)
+#define APMU_NAND      APMU_REG(0x060)
+#define APMU_SDH0      APMU_REG(0x054)
+#define APMU_SDH1      APMU_REG(0x058)
+#define APMU_SDH2      APMU_REG(0x0e8)
+#define APMU_SDH3      APMU_REG(0x0ec)
+
+static void sdhc_clk_enable(struct clk *clk)
+{
+       uint32_t clk_rst;
+
+       clk_rst  =  __raw_readl(clk->clk_rst);
+       clk_rst |= clk->enable_val;
+       __raw_writel(clk_rst, clk->clk_rst);
+}
+
+static void sdhc_clk_disable(struct clk *clk)
+{
+       uint32_t clk_rst;
+
+       clk_rst  =  __raw_readl(clk->clk_rst);
+       clk_rst &= ~clk->enable_val;
+       __raw_writel(clk_rst, clk->clk_rst);
+}
+
+struct clkops sdhc_clk_ops = {
+       .enable         = sdhc_clk_enable,
+       .disable        = sdhc_clk_disable,
+};
+
+/* APB peripheral clocks */
+static APBC_CLK(uart1, UART1, 1, 26000000);
+static APBC_CLK(uart2, UART2, 1, 26000000);
+static APBC_CLK(uart3, UART3, 1, 26000000);
+static APBC_CLK(uart4, UART4, 1, 26000000);
+static APBC_CLK(twsi1, TWSI1, 0, 26000000);
+static APBC_CLK(twsi2, TWSI2, 0, 26000000);
+static APBC_CLK(twsi3, TWSI3, 0, 26000000);
+static APBC_CLK(twsi4, TWSI4, 0, 26000000);
+static APBC_CLK(twsi5, TWSI5, 0, 26000000);
+static APBC_CLK(twsi6, TWSI6, 0, 26000000);
+static APBC_CLK(gpio, GPIO, 0, 26000000);
+
+static APMU_CLK(nand, NAND, 0xbf, 100000000);
+static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
+static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops);
+static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops);
+static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops);
+
+static struct clk_lookup mmp2_clkregs[] = {
+       INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
+       INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
+       INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
+       INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL),
+       INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL),
+       INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL),
+       INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL),
+       INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL),
+       INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
+       INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
+       INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
+       INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
+       INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
+       INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
+       INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),
+       INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"),
+};
+
+void __init mmp2_clk_init(void)
+{
+       clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs));
+}
diff --git a/arch/arm/mach-mmp/clock-pxa168.c b/arch/arm/mach-mmp/clock-pxa168.c
new file mode 100644 (file)
index 0000000..5e6c18c
--- /dev/null
@@ -0,0 +1,91 @@
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+
+#include <mach/addr-map.h>
+
+#include "common.h"
+#include "clock.h"
+
+/*
+ * APB clock register offsets for PXA168
+ */
+#define APBC_UART1     APBC_REG(0x000)
+#define APBC_UART2     APBC_REG(0x004)
+#define APBC_GPIO      APBC_REG(0x008)
+#define APBC_PWM1      APBC_REG(0x00c)
+#define APBC_PWM2      APBC_REG(0x010)
+#define APBC_PWM3      APBC_REG(0x014)
+#define APBC_PWM4      APBC_REG(0x018)
+#define APBC_RTC       APBC_REG(0x028)
+#define APBC_TWSI0     APBC_REG(0x02c)
+#define APBC_KPC       APBC_REG(0x030)
+#define APBC_TWSI1     APBC_REG(0x06c)
+#define APBC_UART3     APBC_REG(0x070)
+#define APBC_SSP1      APBC_REG(0x81c)
+#define APBC_SSP2      APBC_REG(0x820)
+#define APBC_SSP3      APBC_REG(0x84c)
+#define APBC_SSP4      APBC_REG(0x858)
+#define APBC_SSP5      APBC_REG(0x85c)
+
+#define APMU_NAND      APMU_REG(0x060)
+#define APMU_LCD       APMU_REG(0x04c)
+#define APMU_ETH       APMU_REG(0x0fc)
+#define APMU_USB       APMU_REG(0x05c)
+
+/* APB peripheral clocks */
+static APBC_CLK(uart1, UART1, 1, 14745600);
+static APBC_CLK(uart2, UART2, 1, 14745600);
+static APBC_CLK(uart3, UART3, 1, 14745600);
+static APBC_CLK(twsi0, TWSI0, 1, 33000000);
+static APBC_CLK(twsi1, TWSI1, 1, 33000000);
+static APBC_CLK(pwm1, PWM1, 1, 13000000);
+static APBC_CLK(pwm2, PWM2, 1, 13000000);
+static APBC_CLK(pwm3, PWM3, 1, 13000000);
+static APBC_CLK(pwm4, PWM4, 1, 13000000);
+static APBC_CLK(ssp1, SSP1, 4, 0);
+static APBC_CLK(ssp2, SSP2, 4, 0);
+static APBC_CLK(ssp3, SSP3, 4, 0);
+static APBC_CLK(ssp4, SSP4, 4, 0);
+static APBC_CLK(ssp5, SSP5, 4, 0);
+static APBC_CLK(gpio, GPIO, 0, 13000000);
+static APBC_CLK(keypad, KPC, 0, 32000);
+static APBC_CLK(rtc, RTC, 8, 32768);
+
+static APMU_CLK(nand, NAND, 0x19b, 156000000);
+static APMU_CLK(lcd, LCD, 0x7f, 312000000);
+static APMU_CLK(eth, ETH, 0x09, 0);
+static APMU_CLK(usb, USB, 0x12, 0);
+
+/* device and clock bindings */
+static struct clk_lookup pxa168_clkregs[] = {
+       INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
+       INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
+       INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
+       INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
+       INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
+       INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL),
+       INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL),
+       INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL),
+       INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL),
+       INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL),
+       INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL),
+       INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL),
+       INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
+       INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
+       INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
+       INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
+       INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
+       INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
+       INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
+       INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"),
+       INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
+};
+
+void __init pxa168_clk_init(void)
+{
+       clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs));
+}
diff --git a/arch/arm/mach-mmp/clock-pxa910.c b/arch/arm/mach-mmp/clock-pxa910.c
new file mode 100644 (file)
index 0000000..933ea71
--- /dev/null
@@ -0,0 +1,67 @@
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+
+#include <mach/addr-map.h>
+
+#include "common.h"
+#include "clock.h"
+
+/*
+ * APB Clock register offsets for PXA910
+ */
+#define APBC_UART0     APBC_REG(0x000)
+#define APBC_UART1     APBC_REG(0x004)
+#define APBC_GPIO      APBC_REG(0x008)
+#define APBC_PWM1      APBC_REG(0x00c)
+#define APBC_PWM2      APBC_REG(0x010)
+#define APBC_PWM3      APBC_REG(0x014)
+#define APBC_PWM4      APBC_REG(0x018)
+#define APBC_SSP1      APBC_REG(0x01c)
+#define APBC_SSP2      APBC_REG(0x020)
+#define APBC_RTC       APBC_REG(0x028)
+#define APBC_TWSI0     APBC_REG(0x02c)
+#define APBC_KPC       APBC_REG(0x030)
+#define APBC_SSP3      APBC_REG(0x04c)
+#define APBC_TWSI1     APBC_REG(0x06c)
+
+#define APMU_NAND      APMU_REG(0x060)
+#define APMU_USB       APMU_REG(0x05c)
+
+static APBC_CLK(uart1, UART0, 1, 14745600);
+static APBC_CLK(uart2, UART1, 1, 14745600);
+static APBC_CLK(twsi0, TWSI0, 1, 33000000);
+static APBC_CLK(twsi1, TWSI1, 1, 33000000);
+static APBC_CLK(pwm1, PWM1, 1, 13000000);
+static APBC_CLK(pwm2, PWM2, 1, 13000000);
+static APBC_CLK(pwm3, PWM3, 1, 13000000);
+static APBC_CLK(pwm4, PWM4, 1, 13000000);
+static APBC_CLK(gpio, GPIO, 0, 13000000);
+static APBC_CLK(rtc, RTC, 8, 32768);
+
+static APMU_CLK(nand, NAND, 0x19b, 156000000);
+static APMU_CLK(u2o, USB, 0x1b, 480000000);
+
+/* device and clock bindings */
+static struct clk_lookup pxa910_clkregs[] = {
+       INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
+       INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
+       INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
+       INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
+       INIT_CLKREG(&clk_pwm1, "pxa910-pwm.0", NULL),
+       INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL),
+       INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL),
+       INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
+       INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
+       INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
+       INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"),
+       INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
+};
+
+void __init pxa910_clk_init(void)
+{
+       clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs));
+}
index 1c9d6c1..bd45327 100644 (file)
@@ -7,3 +7,6 @@ extern void timer_init(int irq);
 extern void __init icu_init_irq(void);
 extern void __init mmp_map_io(void);
 extern void mmp_restart(char, const char *);
+extern void __init pxa168_clk_init(void);
+extern void __init pxa910_clk_init(void);
+extern void __init mmp2_clk_init(void);
index 68b0c93..ddc812f 100644 (file)
 
 #include <mach/addr-map.h>
 
-/*
- * APB clock register offsets for PXA168
- */
-#define APBC_PXA168_UART1      APBC_REG(0x000)
-#define APBC_PXA168_UART2      APBC_REG(0x004)
-#define APBC_PXA168_GPIO       APBC_REG(0x008)
-#define APBC_PXA168_PWM1       APBC_REG(0x00c)
-#define APBC_PXA168_PWM2       APBC_REG(0x010)
-#define APBC_PXA168_PWM3       APBC_REG(0x014)
-#define APBC_PXA168_PWM4       APBC_REG(0x018)
-#define APBC_PXA168_RTC                APBC_REG(0x028)
-#define APBC_PXA168_TWSI0      APBC_REG(0x02c)
-#define APBC_PXA168_KPC                APBC_REG(0x030)
-#define APBC_PXA168_TIMERS     APBC_REG(0x034)
-#define APBC_PXA168_AIB                APBC_REG(0x03c)
-#define APBC_PXA168_SW_JTAG    APBC_REG(0x040)
-#define APBC_PXA168_ONEWIRE    APBC_REG(0x048)
-#define APBC_PXA168_ASFAR      APBC_REG(0x050)
-#define APBC_PXA168_ASSAR      APBC_REG(0x054)
-#define APBC_PXA168_TWSI1      APBC_REG(0x06c)
-#define APBC_PXA168_UART3      APBC_REG(0x070)
-#define APBC_PXA168_AC97       APBC_REG(0x084)
-#define APBC_PXA168_SSP1       APBC_REG(0x81c)
-#define APBC_PXA168_SSP2       APBC_REG(0x820)
-#define APBC_PXA168_SSP3       APBC_REG(0x84c)
-#define APBC_PXA168_SSP4       APBC_REG(0x858)
-#define APBC_PXA168_SSP5       APBC_REG(0x85c)
-
-/*
- * APB Clock register offsets for PXA910
- */
-#define APBC_PXA910_UART0      APBC_REG(0x000)
-#define APBC_PXA910_UART1      APBC_REG(0x004)
-#define APBC_PXA910_GPIO       APBC_REG(0x008)
-#define APBC_PXA910_PWM1       APBC_REG(0x00c)
-#define APBC_PXA910_PWM2       APBC_REG(0x010)
-#define APBC_PXA910_PWM3       APBC_REG(0x014)
-#define APBC_PXA910_PWM4       APBC_REG(0x018)
-#define APBC_PXA910_SSP1       APBC_REG(0x01c)
-#define APBC_PXA910_SSP2       APBC_REG(0x020)
-#define APBC_PXA910_IPC                APBC_REG(0x024)
-#define APBC_PXA910_RTC                APBC_REG(0x028)
-#define APBC_PXA910_TWSI0      APBC_REG(0x02c)
-#define APBC_PXA910_KPC                APBC_REG(0x030)
-#define APBC_PXA910_TIMERS     APBC_REG(0x034)
-#define APBC_PXA910_TBROT      APBC_REG(0x038)
-#define APBC_PXA910_AIB                APBC_REG(0x03c)
-#define APBC_PXA910_SW_JTAG    APBC_REG(0x040)
-#define APBC_PXA910_TIMERS1    APBC_REG(0x044)
-#define APBC_PXA910_ONEWIRE    APBC_REG(0x048)
-#define APBC_PXA910_SSP3       APBC_REG(0x04c)
-#define APBC_PXA910_ASFAR      APBC_REG(0x050)
-#define APBC_PXA910_ASSAR      APBC_REG(0x054)
-
-/*
- * APB Clock register offsets for MMP2
- */
-#define APBC_MMP2_RTC          APBC_REG(0x000)
-#define APBC_MMP2_TWSI1                APBC_REG(0x004)
-#define APBC_MMP2_TWSI2                APBC_REG(0x008)
-#define APBC_MMP2_TWSI3                APBC_REG(0x00c)
-#define APBC_MMP2_TWSI4                APBC_REG(0x010)
-#define APBC_MMP2_ONEWIRE      APBC_REG(0x014)
-#define APBC_MMP2_KPC          APBC_REG(0x018)
-#define APBC_MMP2_TB_ROTARY    APBC_REG(0x01c)
-#define APBC_MMP2_SW_JTAG      APBC_REG(0x020)
-#define APBC_MMP2_TIMERS       APBC_REG(0x024)
-#define APBC_MMP2_UART1                APBC_REG(0x02c)
-#define APBC_MMP2_UART2                APBC_REG(0x030)
-#define APBC_MMP2_UART3                APBC_REG(0x034)
-#define APBC_MMP2_GPIO         APBC_REG(0x038)
-#define APBC_MMP2_PWM0         APBC_REG(0x03c)
-#define APBC_MMP2_PWM1         APBC_REG(0x040)
-#define APBC_MMP2_PWM2         APBC_REG(0x044)
-#define APBC_MMP2_PWM3         APBC_REG(0x048)
-#define APBC_MMP2_SSP0         APBC_REG(0x04c)
-#define APBC_MMP2_SSP1         APBC_REG(0x050)
-#define APBC_MMP2_SSP2         APBC_REG(0x054)
-#define APBC_MMP2_SSP3         APBC_REG(0x058)
-#define APBC_MMP2_SSP4         APBC_REG(0x05c)
-#define APBC_MMP2_SSP5         APBC_REG(0x060)
-#define APBC_MMP2_AIB          APBC_REG(0x064)
-#define APBC_MMP2_ASFAR                APBC_REG(0x068)
-#define APBC_MMP2_ASSAR                APBC_REG(0x06c)
-#define APBC_MMP2_USIM         APBC_REG(0x070)
-#define APBC_MMP2_MPMU         APBC_REG(0x074)
-#define APBC_MMP2_IPC          APBC_REG(0x078)
-#define APBC_MMP2_TWSI5                APBC_REG(0x07c)
-#define APBC_MMP2_TWSI6                APBC_REG(0x080)
-#define APBC_MMP2_TWSI_INTSTS  APBC_REG(0x084)
-#define APBC_MMP2_UART4                APBC_REG(0x088)
-#define APBC_MMP2_RIPC         APBC_REG(0x08c)
-#define APBC_MMP2_THSENS1      APBC_REG(0x090) /* Thermal Sensor */
-#define APBC_MMP2_THSENS_INTSTS        APBC_REG(0x0a4)
-
 /* Common APB clock register bit definitions */
 #define APBC_APBCLK    (1 << 0)  /* APB Bus Clock Enable */
 #define APBC_FNCLK     (1 << 1)  /* Functional Clock Enable */
index 7af8deb..93c8d0e 100644 (file)
 
 #include <mach/addr-map.h>
 
-/* Clock Reset Control */
-#define APMU_IRE       APMU_REG(0x048)
-#define APMU_LCD       APMU_REG(0x04c)
-#define APMU_CCIC      APMU_REG(0x050)
-#define APMU_SDH0      APMU_REG(0x054)
-#define APMU_SDH1      APMU_REG(0x058)
-#define APMU_USB       APMU_REG(0x05c)
-#define APMU_NAND      APMU_REG(0x060)
-#define APMU_DMA       APMU_REG(0x064)
-#define APMU_GEU       APMU_REG(0x068)
-#define APMU_BUS       APMU_REG(0x06c)
-#define APMU_SDH2      APMU_REG(0x0e8)
-#define APMU_SDH3      APMU_REG(0x0ec)
-#define APMU_ETH       APMU_REG(0x0fc)
-
 #define APMU_FNCLK_EN  (1 << 4)
 #define APMU_AXICLK_EN (1 << 3)
 #define APMU_FNRST_DIS (1 << 1)
index e60c7d9..3c71246 100644 (file)
@@ -153,10 +153,8 @@ static void icu_mux_irq_demux(unsigned int irq, struct irq_desc *desc)
                status = readl_relaxed(data->reg_status) & ~mask;
                if (status == 0)
                        break;
-               n = find_first_bit(&status, BITS_PER_LONG);
-               while (n < BITS_PER_LONG) {
+               for_each_set_bit(n, &status, BITS_PER_LONG) {
                        generic_handle_irq(icu_data[i].virq_base + n);
-                       n = find_next_bit(&status, BITS_PER_LONG, n + 1);
                }
        }
 }
index c709a24..c2ce3d0 100644 (file)
@@ -20,7 +20,6 @@
 #include <asm/mach/time.h>
 #include <mach/addr-map.h>
 #include <mach/regs-apbc.h>
-#include <mach/regs-apmu.h>
 #include <mach/cputype.h>
 #include <mach/irqs.h>
 #include <mach/dma.h>
@@ -29,7 +28,6 @@
 #include <mach/mmp2.h>
 
 #include "common.h"
-#include "clock.h"
 
 #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
 
@@ -98,67 +96,6 @@ void __init mmp2_init_irq(void)
        mmp2_init_icu();
 }
 
-static void sdhc_clk_enable(struct clk *clk)
-{
-       uint32_t clk_rst;
-
-       clk_rst  =  __raw_readl(clk->clk_rst);
-       clk_rst |= clk->enable_val;
-       __raw_writel(clk_rst, clk->clk_rst);
-}
-
-static void sdhc_clk_disable(struct clk *clk)
-{
-       uint32_t clk_rst;
-
-       clk_rst  =  __raw_readl(clk->clk_rst);
-       clk_rst &= ~clk->enable_val;
-       __raw_writel(clk_rst, clk->clk_rst);
-}
-
-struct clkops sdhc_clk_ops = {
-       .enable         = sdhc_clk_enable,
-       .disable        = sdhc_clk_disable,
-};
-
-/* APB peripheral clocks */
-static APBC_CLK(uart1, MMP2_UART1, 1, 26000000);
-static APBC_CLK(uart2, MMP2_UART2, 1, 26000000);
-static APBC_CLK(uart3, MMP2_UART3, 1, 26000000);
-static APBC_CLK(uart4, MMP2_UART4, 1, 26000000);
-static APBC_CLK(twsi1, MMP2_TWSI1, 0, 26000000);
-static APBC_CLK(twsi2, MMP2_TWSI2, 0, 26000000);
-static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000);
-static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000);
-static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000);
-static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000);
-static APBC_CLK(gpio, MMP2_GPIO, 0, 26000000);
-
-static APMU_CLK(nand, NAND, 0xbf, 100000000);
-static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
-static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops);
-static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops);
-static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops);
-
-static struct clk_lookup mmp2_clkregs[] = {
-       INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
-       INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
-       INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
-       INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL),
-       INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL),
-       INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL),
-       INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL),
-       INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL),
-       INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
-       INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
-       INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
-       INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
-       INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
-       INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
-       INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),
-       INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"),
-};
-
 static int __init mmp2_init(void)
 {
        if (cpu_is_mmp2()) {
@@ -168,25 +105,27 @@ static int __init mmp2_init(void)
                mfp_init_base(MFPR_VIRT_BASE);
                mfp_init_addr(mmp2_addr_map);
                pxa_init_dma(IRQ_MMP2_DMA_RIQ, 16);
-               clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs));
+               mmp2_clk_init();
        }
 
        return 0;
 }
 postcore_initcall(mmp2_init);
 
+#define APBC_TIMERS    APBC_REG(0x024)
+
 static void __init mmp2_timer_init(void)
 {
        unsigned long clk_rst;
 
-       __raw_writel(APBC_APBCLK | APBC_RST, APBC_MMP2_TIMERS);
+       __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
 
        /*
         * enable bus/functional clock, enable 6.5MHz (divider 4),
         * release reset
         */
        clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1);
-       __raw_writel(clk_rst, APBC_MMP2_TIMERS);
+       __raw_writel(clk_rst, APBC_TIMERS);
 
        timer_init(IRQ_MMP2_TIMER1);
 }
index 62d787c..b7f074f 100644 (file)
@@ -18,8 +18,8 @@
 
 #include <asm/mach/time.h>
 #include <asm/system_misc.h>
-#include <mach/addr-map.h>
 #include <mach/cputype.h>
+#include <mach/addr-map.h>
 #include <mach/regs-apbc.h>
 #include <mach/regs-apmu.h>
 #include <mach/irqs.h>
@@ -50,62 +50,13 @@ void __init pxa168_init_irq(void)
        icu_init_irq();
 }
 
-/* APB peripheral clocks */
-static APBC_CLK(uart1, PXA168_UART1, 1, 14745600);
-static APBC_CLK(uart2, PXA168_UART2, 1, 14745600);
-static APBC_CLK(uart3, PXA168_UART3, 1, 14745600);
-static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000);
-static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000);
-static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000);
-static APBC_CLK(pwm2, PXA168_PWM2, 1, 13000000);
-static APBC_CLK(pwm3, PXA168_PWM3, 1, 13000000);
-static APBC_CLK(pwm4, PXA168_PWM4, 1, 13000000);
-static APBC_CLK(ssp1, PXA168_SSP1, 4, 0);
-static APBC_CLK(ssp2, PXA168_SSP2, 4, 0);
-static APBC_CLK(ssp3, PXA168_SSP3, 4, 0);
-static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
-static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
-static APBC_CLK(gpio, PXA168_GPIO, 0, 13000000);
-static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
-static APBC_CLK(rtc, PXA168_RTC, 8, 32768);
-
-static APMU_CLK(nand, NAND, 0x19b, 156000000);
-static APMU_CLK(lcd, LCD, 0x7f, 312000000);
-static APMU_CLK(eth, ETH, 0x09, 0);
-static APMU_CLK(usb, USB, 0x12, 0);
-
-/* device and clock bindings */
-static struct clk_lookup pxa168_clkregs[] = {
-       INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
-       INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
-       INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
-       INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
-       INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
-       INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL),
-       INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL),
-       INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL),
-       INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL),
-       INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL),
-       INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL),
-       INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL),
-       INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
-       INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
-       INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
-       INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
-       INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
-       INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
-       INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
-       INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"),
-       INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
-};
-
 static int __init pxa168_init(void)
 {
        if (cpu_is_pxa168()) {
                mfp_init_base(MFPR_VIRT_BASE);
                mfp_init_addr(pxa168_mfp_addr_map);
                pxa_init_dma(IRQ_PXA168_DMA_INT0, 32);
-               clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs));
+               pxa168_clk_init();
        }
 
        return 0;
@@ -114,6 +65,7 @@ postcore_initcall(pxa168_init);
 
 /* system timer - clock enabled, 3.25MHz */
 #define TIMER_CLK_RST  (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
+#define APBC_TIMERS    APBC_REG(0x34)
 
 static void __init pxa168_timer_init(void)
 {
@@ -121,10 +73,10 @@ static void __init pxa168_timer_init(void)
         * ourselves instead of using clk_* API. Clock rate is defined
         * by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running
         */
-       __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA168_TIMERS);
+       __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
 
        /* 3.25MHz, bus/functional clock enabled, release reset */
-       __raw_writel(TIMER_CLK_RST, APBC_PXA168_TIMERS);
+       __raw_writel(TIMER_CLK_RST, APBC_TIMERS);
 
        timer_init(IRQ_PXA168_TIMER1);
 }
index 6da52e9..7d84521 100644 (file)
@@ -17,7 +17,6 @@
 #include <asm/mach/time.h>
 #include <mach/addr-map.h>
 #include <mach/regs-apbc.h>
-#include <mach/regs-apmu.h>
 #include <mach/cputype.h>
 #include <mach/irqs.h>
 #include <mach/dma.h>
@@ -25,7 +24,6 @@
 #include <mach/devices.h>
 
 #include "common.h"
-#include "clock.h"
 
 #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
 
@@ -82,44 +80,13 @@ void __init pxa910_init_irq(void)
        icu_init_irq();
 }
 
-/* APB peripheral clocks */
-static APBC_CLK(uart1, PXA910_UART0, 1, 14745600);
-static APBC_CLK(uart2, PXA910_UART1, 1, 14745600);
-static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000);
-static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000);
-static APBC_CLK(pwm1, PXA910_PWM1, 1, 13000000);
-static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000);
-static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000);
-static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000);
-static APBC_CLK(gpio, PXA910_GPIO, 0, 13000000);
-static APBC_CLK(rtc, PXA910_RTC, 8, 32768);
-
-static APMU_CLK(nand, NAND, 0x19b, 156000000);
-static APMU_CLK(u2o, USB, 0x1b, 480000000);
-
-/* device and clock bindings */
-static struct clk_lookup pxa910_clkregs[] = {
-       INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
-       INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
-       INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
-       INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
-       INIT_CLKREG(&clk_pwm1, "pxa910-pwm.0", NULL),
-       INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL),
-       INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL),
-       INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
-       INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
-       INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
-       INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"),
-       INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
-};
-
 static int __init pxa910_init(void)
 {
        if (cpu_is_pxa910()) {
                mfp_init_base(MFPR_VIRT_BASE);
                mfp_init_addr(pxa910_mfp_addr_map);
                pxa_init_dma(IRQ_PXA910_DMA_INT0, 32);
-               clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs));
+               pxa910_clk_init();
        }
 
        return 0;
@@ -128,12 +95,13 @@ postcore_initcall(pxa910_init);
 
 /* system timer - clock enabled, 3.25MHz */
 #define TIMER_CLK_RST  (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
+#define APBC_TIMERS    APBC_REG(0x34)
 
 static void __init pxa910_timer_init(void)
 {
        /* reset and configure */
-       __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA910_TIMERS);
-       __raw_writel(TIMER_CLK_RST, APBC_PXA910_TIMERS);
+       __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
+       __raw_writel(TIMER_CLK_RST, APBC_TIMERS);
 
        timer_init(IRQ_PXA910_AP1_TIMER1);
 }
index 4ad3969..6a6c197 100644 (file)
@@ -1,11 +1,11 @@
-obj-y += io.o idle.o timer.o
+obj-y += io.o timer.o
 obj-y += clock.o
 obj-$(CONFIG_DEBUG_FS) += clock-debug.o
 
 obj-$(CONFIG_MSM_VIC) += irq-vic.o
 obj-$(CONFIG_MSM_IOMMU) += devices-iommu.o
 
-obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o
+obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o
 obj-$(CONFIG_ARCH_MSM7X30) += dma.o
 obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o
 
diff --git a/arch/arm/mach-msm/acpuclock-arm11.c b/arch/arm/mach-msm/acpuclock-arm11.c
deleted file mode 100644 (file)
index 805d4ee..0000000
+++ /dev/null
@@ -1,525 +0,0 @@
-/* arch/arm/mach-msm/acpuclock.c
- *
- * MSM architecture clock driver
- *
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007 QUALCOMM Incorporated
- * Author: San Mehat <san@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/cpufreq.h>
-#include <linux/mutex.h>
-#include <linux/io.h>
-#include <mach/board.h>
-#include <mach/msm_iomap.h>
-
-#include "proc_comm.h"
-#include "acpuclock.h"
-
-
-#define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100)
-#define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104)
-#define A11S_VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124)
-
-/*
- * ARM11 clock configuration for specific ACPU speeds
- */
-
-#define ACPU_PLL_TCXO  -1
-#define ACPU_PLL_0     0
-#define ACPU_PLL_1     1
-#define ACPU_PLL_2     2
-#define ACPU_PLL_3     3
-
-#define PERF_SWITCH_DEBUG 0
-#define PERF_SWITCH_STEP_DEBUG 0
-
-struct clock_state
-{
-       struct clkctl_acpu_speed        *current_speed;
-       struct mutex                    lock;
-       uint32_t                        acpu_switch_time_us;
-       uint32_t                        max_speed_delta_khz;
-       uint32_t                        vdd_switch_time_us;
-       unsigned long                   power_collapse_khz;
-       unsigned long                   wait_for_irq_khz;
-};
-
-static struct clk *ebi1_clk;
-static struct clock_state drv_state = { 0 };
-
-static void __init acpuclk_init(void);
-
-/* MSM7201A Levels 3-6 all correspond to 1.2V, level 7 corresponds to 1.325V. */
-enum {
-       VDD_0 = 0,
-       VDD_1 = 1,
-       VDD_2 = 2,
-       VDD_3 = 3,
-       VDD_4 = 3,
-       VDD_5 = 3,
-       VDD_6 = 3,
-       VDD_7 = 7,
-       VDD_END
-};
-
-struct clkctl_acpu_speed {
-       unsigned int    a11clk_khz;
-       int             pll;
-       unsigned int    a11clk_src_sel;
-       unsigned int    a11clk_src_div;
-       unsigned int    ahbclk_khz;
-       unsigned int    ahbclk_div;
-       int             vdd;
-       unsigned int    axiclk_khz;
-       unsigned long   lpj; /* loops_per_jiffy */
-/* Index in acpu_freq_tbl[] for steppings. */
-       short           down;
-       short           up;
-};
-
-/*
- * ACPU speed table. Complete table is shown but certain speeds are commented
- * out to optimized speed switching. Initialize loops_per_jiffy to 0.
- *
- * Table stepping up/down is optimized for 256mhz jumps while staying on the
- * same PLL.
- */
-#if (0)
-static struct clkctl_acpu_speed  acpu_freq_tbl[] = {
-       { 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 8 },
-       { 61440, ACPU_PLL_0,  4, 3, 61440,  0, VDD_0, 30720,  0, 0, 8 },
-       { 81920, ACPU_PLL_0,  4, 2, 40960,  1, VDD_0, 61440,  0, 0, 8 },
-       { 96000, ACPU_PLL_1,  1, 7, 48000,  1, VDD_0, 61440,  0, 0, 9 },
-       { 122880, ACPU_PLL_0, 4, 1, 61440,  1, VDD_3, 61440,  0, 0, 8 },
-       { 128000, ACPU_PLL_1, 1, 5, 64000,  1, VDD_3, 61440,  0, 0, 12 },
-       { 176000, ACPU_PLL_2, 2, 5, 88000,  1, VDD_3, 61440,  0, 0, 11 },
-       { 192000, ACPU_PLL_1, 1, 3, 64000,  2, VDD_3, 61440,  0, 0, 12 },
-       { 245760, ACPU_PLL_0, 4, 0, 81920,  2, VDD_4, 61440,  0, 0, 12 },
-       { 256000, ACPU_PLL_1, 1, 2, 128000, 2, VDD_5, 128000, 0, 0, 12 },
-       { 264000, ACPU_PLL_2, 2, 3, 88000,  2, VDD_5, 128000, 0, 6, 13 },
-       { 352000, ACPU_PLL_2, 2, 2, 88000,  3, VDD_5, 128000, 0, 6, 13 },
-       { 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 5, -1 },
-       { 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 11, -1 },
-       { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
-};
-#else /* Table of freq we currently use. */
-static struct clkctl_acpu_speed  acpu_freq_tbl[] = {
-       { 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 4 },
-       { 122880, ACPU_PLL_0, 4, 1, 61440, 1, VDD_3, 61440, 0, 0, 4 },
-       { 128000, ACPU_PLL_1, 1, 5, 64000, 1, VDD_3, 61440, 0, 0, 6 },
-       { 176000, ACPU_PLL_2, 2, 5, 88000, 1, VDD_3, 61440, 0, 0, 5 },
-       { 245760, ACPU_PLL_0, 4, 0, 81920, 2, VDD_4, 61440, 0, 0, 5 },
-       { 352000, ACPU_PLL_2, 2, 2, 88000, 3, VDD_5, 128000, 0, 3, 7 },
-       { 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 2, -1 },
-       { 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 5, -1 },
-       { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
-};
-#endif
-
-
-#ifdef CONFIG_CPU_FREQ_TABLE
-static struct cpufreq_frequency_table freq_table[] = {
-       { 0, 122880 },
-       { 1, 128000 },
-       { 2, 245760 },
-       { 3, 384000 },
-       { 4, 528000 },
-       { 5, CPUFREQ_TABLE_END },
-};
-#endif
-
-static int pc_pll_request(unsigned id, unsigned on)
-{
-       int res;
-       on = !!on;
-
-#if PERF_SWITCH_DEBUG
-       if (on)
-               printk(KERN_DEBUG "Enabling PLL %d\n", id);
-       else
-               printk(KERN_DEBUG "Disabling PLL %d\n", id);
-#endif
-
-       res = msm_proc_comm(PCOM_CLKCTL_RPC_PLL_REQUEST, &id, &on);
-       if (res < 0)
-               return res;
-
-#if PERF_SWITCH_DEBUG
-       if (on)
-               printk(KERN_DEBUG "PLL %d enabled\n", id);
-       else
-               printk(KERN_DEBUG "PLL %d disabled\n", id);
-#endif
-       return res;
-}
-
-
-/*----------------------------------------------------------------------------
- * ARM11 'owned' clock control
- *---------------------------------------------------------------------------*/
-
-unsigned long acpuclk_power_collapse(void) {
-       int ret = acpuclk_get_rate();
-       ret *= 1000;
-       if (ret > drv_state.power_collapse_khz)
-               acpuclk_set_rate(drv_state.power_collapse_khz, 1);
-       return ret;
-}
-
-unsigned long acpuclk_get_wfi_rate(void)
-{
-       return drv_state.wait_for_irq_khz;
-}
-
-unsigned long acpuclk_wait_for_irq(void) {
-       int ret = acpuclk_get_rate();
-       ret *= 1000;
-       if (ret > drv_state.wait_for_irq_khz)
-               acpuclk_set_rate(drv_state.wait_for_irq_khz, 1);
-       return ret;
-}
-
-static int acpuclk_set_vdd_level(int vdd)
-{
-       uint32_t current_vdd;
-
-       current_vdd = readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x07;
-
-#if PERF_SWITCH_DEBUG
-       printk(KERN_DEBUG "acpuclock: Switching VDD from %u -> %d\n",
-              current_vdd, vdd);
-#endif
-       writel((1 << 7) | (vdd << 3), A11S_VDD_SVS_PLEVEL_ADDR);
-       udelay(drv_state.vdd_switch_time_us);
-       if ((readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x7) != vdd) {
-#if PERF_SWITCH_DEBUG
-               printk(KERN_ERR "acpuclock: VDD set failed\n");
-#endif
-               return -EIO;
-       }
-
-#if PERF_SWITCH_DEBUG
-       printk(KERN_DEBUG "acpuclock: VDD switched\n");
-#endif
-       return 0;
-}
-
-/* Set proper dividers for the given clock speed. */
-static void acpuclk_set_div(const struct clkctl_acpu_speed *hunt_s) {
-       uint32_t reg_clkctl, reg_clksel, clk_div;
-
-       /* AHB_CLK_DIV */
-       clk_div = (readl(A11S_CLK_SEL_ADDR) >> 1) & 0x03;
-       /*
-        * If the new clock divider is higher than the previous, then
-        * program the divider before switching the clock
-        */
-       if (hunt_s->ahbclk_div > clk_div) {
-               reg_clksel = readl(A11S_CLK_SEL_ADDR);
-               reg_clksel &= ~(0x3 << 1);
-               reg_clksel |= (hunt_s->ahbclk_div << 1);
-               writel(reg_clksel, A11S_CLK_SEL_ADDR);
-       }
-       if ((readl(A11S_CLK_SEL_ADDR) & 0x01) == 0) {
-               /* SRC0 */
-
-               /* Program clock source */
-               reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
-               reg_clkctl &= ~(0x07 << 4);
-               reg_clkctl |= (hunt_s->a11clk_src_sel << 4);
-               writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
-
-               /* Program clock divider */
-               reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
-               reg_clkctl &= ~0xf;
-               reg_clkctl |= hunt_s->a11clk_src_div;
-               writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
-
-               /* Program clock source selection */
-               reg_clksel = readl(A11S_CLK_SEL_ADDR);
-               reg_clksel |= 1; /* CLK_SEL_SRC1NO  == SRC1 */
-               writel(reg_clksel, A11S_CLK_SEL_ADDR);
-       } else {
-               /* SRC1 */
-
-               /* Program clock source */
-               reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
-               reg_clkctl &= ~(0x07 << 12);
-               reg_clkctl |= (hunt_s->a11clk_src_sel << 12);
-               writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
-
-               /* Program clock divider */
-               reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
-               reg_clkctl &= ~(0xf << 8);
-               reg_clkctl |= (hunt_s->a11clk_src_div << 8);
-               writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
-
-               /* Program clock source selection */
-               reg_clksel = readl(A11S_CLK_SEL_ADDR);
-               reg_clksel &= ~1; /* CLK_SEL_SRC1NO  == SRC0 */
-               writel(reg_clksel, A11S_CLK_SEL_ADDR);
-       }
-
-       /*
-        * If the new clock divider is lower than the previous, then
-        * program the divider after switching the clock
-        */
-       if (hunt_s->ahbclk_div < clk_div) {
-               reg_clksel = readl(A11S_CLK_SEL_ADDR);
-               reg_clksel &= ~(0x3 << 1);
-               reg_clksel |= (hunt_s->ahbclk_div << 1);
-               writel(reg_clksel, A11S_CLK_SEL_ADDR);
-       }
-}
-
-int acpuclk_set_rate(unsigned long rate, int for_power_collapse)
-{
-       uint32_t reg_clkctl;
-       struct clkctl_acpu_speed *cur_s, *tgt_s, *strt_s;
-       int rc = 0;
-       unsigned int plls_enabled = 0, pll;
-
-       strt_s = cur_s = drv_state.current_speed;
-
-       WARN_ONCE(cur_s == NULL, "acpuclk_set_rate: not initialized\n");
-       if (cur_s == NULL)
-               return -ENOENT;
-
-       if (rate == (cur_s->a11clk_khz * 1000))
-               return 0;
-
-       for (tgt_s = acpu_freq_tbl; tgt_s->a11clk_khz != 0; tgt_s++) {
-               if (tgt_s->a11clk_khz == (rate / 1000))
-                       break;
-       }
-
-       if (tgt_s->a11clk_khz == 0)
-               return -EINVAL;
-
-       /* Choose the highest speed speed at or below 'rate' with same PLL. */
-       if (for_power_collapse && tgt_s->a11clk_khz < cur_s->a11clk_khz) {
-               while (tgt_s->pll != ACPU_PLL_TCXO && tgt_s->pll != cur_s->pll)
-                       tgt_s--;
-       }
-
-       if (strt_s->pll != ACPU_PLL_TCXO)
-               plls_enabled |= 1 << strt_s->pll;
-
-       if (!for_power_collapse) {
-               mutex_lock(&drv_state.lock);
-               if (strt_s->pll != tgt_s->pll && tgt_s->pll != ACPU_PLL_TCXO) {
-                       rc = pc_pll_request(tgt_s->pll, 1);
-                       if (rc < 0) {
-                               pr_err("PLL%d enable failed (%d)\n",
-                                       tgt_s->pll, rc);
-                               goto out;
-                       }
-                       plls_enabled |= 1 << tgt_s->pll;
-               }
-               /* Increase VDD if needed. */
-               if (tgt_s->vdd > cur_s->vdd) {
-                       if ((rc = acpuclk_set_vdd_level(tgt_s->vdd)) < 0) {
-                               printk(KERN_ERR "Unable to switch ACPU vdd\n");
-                               goto out;
-                       }
-               }
-       }
-
-       /* Set wait states for CPU between frequency changes */
-       reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
-       reg_clkctl |= (100 << 16); /* set WT_ST_CNT */
-       writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
-
-#if PERF_SWITCH_DEBUG
-       printk(KERN_INFO "acpuclock: Switching from ACPU rate %u -> %u\n",
-              strt_s->a11clk_khz * 1000, tgt_s->a11clk_khz * 1000);
-#endif
-
-       while (cur_s != tgt_s) {
-               /*
-                * Always jump to target freq if within 256mhz, regulardless of
-                * PLL. If differnece is greater, use the predefinied
-                * steppings in the table.
-                */
-               int d = abs((int)(cur_s->a11clk_khz - tgt_s->a11clk_khz));
-               if (d > drv_state.max_speed_delta_khz) {
-                       /* Step up or down depending on target vs current. */
-                       int clk_index = tgt_s->a11clk_khz > cur_s->a11clk_khz ?
-                               cur_s->up : cur_s->down;
-                       if (clk_index < 0) { /* This should not happen. */
-                               printk(KERN_ERR "cur:%u target: %u\n",
-                                       cur_s->a11clk_khz, tgt_s->a11clk_khz);
-                               rc = -EINVAL;
-                               goto out;
-                       }
-                       cur_s = &acpu_freq_tbl[clk_index];
-               } else {
-                       cur_s = tgt_s;
-               }
-#if PERF_SWITCH_STEP_DEBUG
-               printk(KERN_DEBUG "%s: STEP khz = %u, pll = %d\n",
-                       __FUNCTION__, cur_s->a11clk_khz, cur_s->pll);
-#endif
-               if (!for_power_collapse&& cur_s->pll != ACPU_PLL_TCXO
-                   && !(plls_enabled & (1 << cur_s->pll))) {
-                       rc = pc_pll_request(cur_s->pll, 1);
-                       if (rc < 0) {
-                               pr_err("PLL%d enable failed (%d)\n",
-                                       cur_s->pll, rc);
-                               goto out;
-                       }
-                       plls_enabled |= 1 << cur_s->pll;
-               }
-
-               acpuclk_set_div(cur_s);
-               drv_state.current_speed = cur_s;
-               /* Re-adjust lpj for the new clock speed. */
-               loops_per_jiffy = cur_s->lpj;
-               udelay(drv_state.acpu_switch_time_us);
-       }
-
-       /* Nothing else to do for power collapse. */
-       if (for_power_collapse)
-               return 0;
-
-       /* Disable PLLs we are not using anymore. */
-       plls_enabled &= ~(1 << tgt_s->pll);
-       for (pll = ACPU_PLL_0; pll <= ACPU_PLL_2; pll++)
-               if (plls_enabled & (1 << pll)) {
-                       rc = pc_pll_request(pll, 0);
-                       if (rc < 0) {
-                               pr_err("PLL%d disable failed (%d)\n", pll, rc);
-                               goto out;
-                       }
-               }
-
-       /* Change the AXI bus frequency if we can. */
-       if (strt_s->axiclk_khz != tgt_s->axiclk_khz) {
-               rc = clk_set_rate(ebi1_clk, tgt_s->axiclk_khz * 1000);
-               if (rc < 0)
-                       pr_err("Setting AXI min rate failed!\n");
-       }
-
-       /* Drop VDD level if we can. */
-       if (tgt_s->vdd < strt_s->vdd) {
-               if (acpuclk_set_vdd_level(tgt_s->vdd) < 0)
-                       printk(KERN_ERR "acpuclock: Unable to drop ACPU vdd\n");
-       }
-
-#if PERF_SWITCH_DEBUG
-       printk(KERN_DEBUG "%s: ACPU speed change complete\n", __FUNCTION__);
-#endif
-out:
-       if (!for_power_collapse)
-               mutex_unlock(&drv_state.lock);
-       return rc;
-}
-
-static void __init acpuclk_init(void)
-{
-       struct clkctl_acpu_speed *speed;
-       uint32_t div, sel;
-       int rc;
-
-       /*
-        * Determine the rate of ACPU clock
-        */
-
-       if (!(readl(A11S_CLK_SEL_ADDR) & 0x01)) { /* CLK_SEL_SRC1N0 */
-               /* CLK_SRC0_SEL */
-               sel = (readl(A11S_CLK_CNTL_ADDR) >> 12) & 0x7;
-               /* CLK_SRC0_DIV */
-               div = (readl(A11S_CLK_CNTL_ADDR) >> 8) & 0x0f;
-       } else {
-               /* CLK_SRC1_SEL */
-               sel = (readl(A11S_CLK_CNTL_ADDR) >> 4) & 0x07;
-               /* CLK_SRC1_DIV */
-               div = readl(A11S_CLK_CNTL_ADDR) & 0x0f;
-       }
-
-       for (speed = acpu_freq_tbl; speed->a11clk_khz != 0; speed++) {
-               if (speed->a11clk_src_sel == sel
-                && (speed->a11clk_src_div == div))
-                       break;
-       }
-       if (speed->a11clk_khz == 0) {
-               printk(KERN_WARNING "Warning - ACPU clock reports invalid speed\n");
-               return;
-       }
-
-       drv_state.current_speed = speed;
-
-       rc = clk_set_rate(ebi1_clk, speed->axiclk_khz * 1000);
-       if (rc < 0)
-               pr_err("Setting AXI min rate failed!\n");
-
-       printk(KERN_INFO "ACPU running at %d KHz\n", speed->a11clk_khz);
-}
-
-unsigned long acpuclk_get_rate(void)
-{
-       WARN_ONCE(drv_state.current_speed == NULL,
-                 "acpuclk_get_rate: not initialized\n");
-       if (drv_state.current_speed)
-               return drv_state.current_speed->a11clk_khz;
-       else
-               return 0;
-}
-
-uint32_t acpuclk_get_switch_time(void)
-{
-       return drv_state.acpu_switch_time_us;
-}
-
-/*----------------------------------------------------------------------------
- * Clock driver initialization
- *---------------------------------------------------------------------------*/
-
-/* Initialize the lpj field in the acpu_freq_tbl. */
-static void __init lpj_init(void)
-{
-       int i;
-       const struct clkctl_acpu_speed *base_clk = drv_state.current_speed;
-       for (i = 0; acpu_freq_tbl[i].a11clk_khz; i++) {
-               acpu_freq_tbl[i].lpj = cpufreq_scale(loops_per_jiffy,
-                                               base_clk->a11clk_khz,
-                                               acpu_freq_tbl[i].a11clk_khz);
-       }
-}
-
-void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *clkdata)
-{
-       pr_info("acpu_clock_init()\n");
-
-       ebi1_clk = clk_get(NULL, "ebi1_clk");
-
-       mutex_init(&drv_state.lock);
-       drv_state.acpu_switch_time_us = clkdata->acpu_switch_time_us;
-       drv_state.max_speed_delta_khz = clkdata->max_speed_delta_khz;
-       drv_state.vdd_switch_time_us = clkdata->vdd_switch_time_us;
-       drv_state.power_collapse_khz = clkdata->power_collapse_khz;
-       drv_state.wait_for_irq_khz = clkdata->wait_for_irq_khz;
-       acpuclk_init();
-       lpj_init();
-#ifdef CONFIG_CPU_FREQ_TABLE
-       cpufreq_frequency_table_get_attr(freq_table, smp_processor_id());
-#endif
-}
diff --git a/arch/arm/mach-msm/acpuclock.h b/arch/arm/mach-msm/acpuclock.h
deleted file mode 100644 (file)
index 415de2e..0000000
+++ /dev/null
@@ -1,32 +0,0 @@
-/* arch/arm/mach-msm/acpuclock.h
- *
- * MSM architecture clock driver header
- *
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007 QUALCOMM Incorporated
- * Author: San Mehat <san@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ARCH_ARM_MACH_MSM_ACPUCLOCK_H
-#define __ARCH_ARM_MACH_MSM_ACPUCLOCK_H
-
-int acpuclk_set_rate(unsigned long rate, int for_power_collapse);
-unsigned long acpuclk_get_rate(void);
-uint32_t acpuclk_get_switch_time(void);
-unsigned long acpuclk_wait_for_irq(void);
-unsigned long acpuclk_power_collapse(void);
-unsigned long acpuclk_get_wfi_rate(void);
-
-
-#endif
-
index cf1f89a..df00bc0 100644 (file)
@@ -30,7 +30,6 @@
 
 #include <mach/board.h>
 #include <mach/hardware.h>
-#include <mach/system.h>
 
 #include "board-mahimahi.h"
 #include "devices.h"
diff --git a/arch/arm/mach-msm/board-msm7x27.c b/arch/arm/mach-msm/board-msm7x27.c
deleted file mode 100644 (file)
index 451ab1d..0000000
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/power_supply.h>
-
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/setup.h>
-#ifdef CONFIG_CACHE_L2X0
-#include <asm/hardware/cache-l2x0.h>
-#endif
-
-#include <mach/vreg.h>
-#include <mach/mpp.h>
-#include <mach/board.h>
-#include <mach/msm_iomap.h>
-
-#include <linux/mtd/nand.h>
-#include <linux/mtd/partitions.h>
-
-#include "devices.h"
-#include "socinfo.h"
-#include "clock.h"
-
-static struct resource smc91x_resources[] = {
-       [0] = {
-               .start  = 0x9C004300,
-               .end    = 0x9C0043ff,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = MSM_GPIO_TO_INT(132),
-               .end    = MSM_GPIO_TO_INT(132),
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device smc91x_device = {
-       .name           = "smc91x",
-       .id             = 0,
-       .num_resources  = ARRAY_SIZE(smc91x_resources),
-       .resource       = smc91x_resources,
-};
-
-static struct platform_device *devices[] __initdata = {
-       &msm_device_uart3,
-       &msm_device_smd,
-       &msm_device_dmov,
-       &msm_device_nand,
-       &smc91x_device,
-};
-
-extern struct sys_timer msm_timer;
-
-static void __init msm7x2x_init_irq(void)
-{
-       msm_init_irq();
-}
-
-static void __init msm7x2x_init(void)
-{
-       if (socinfo_init() < 0)
-               BUG();
-
-       if (machine_is_msm7x25_ffa() || machine_is_msm7x27_ffa()) {
-               smc91x_resources[0].start = 0x98000300;
-               smc91x_resources[0].end = 0x980003ff;
-               smc91x_resources[1].start = MSM_GPIO_TO_INT(85);
-               smc91x_resources[1].end = MSM_GPIO_TO_INT(85);
-               if (gpio_tlmm_config(GPIO_CFG(85, 0,
-                                             GPIO_INPUT,
-                                             GPIO_PULL_DOWN,
-                                             GPIO_2MA),
-                                    GPIO_ENABLE)) {
-                       printk(KERN_ERR
-                              "%s: Err: Config GPIO-85 INT\n",
-                               __func__);
-               }
-       }
-
-       platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-
-static void __init msm7x2x_map_io(void)
-{
-       msm_map_common_io();
-       /* Technically dependent on the SoC but using machine_is
-        * macros since socinfo is not available this early and there
-        * are plans to restructure the code which will eliminate the
-        * need for socinfo.
-        */
-       if (machine_is_msm7x27_surf() || machine_is_msm7x27_ffa())
-               msm_clock_init(msm_clocks_7x27, msm_num_clocks_7x27);
-
-       if (machine_is_msm7x25_surf() || machine_is_msm7x25_ffa())
-               msm_clock_init(msm_clocks_7x25, msm_num_clocks_7x25);
-
-#ifdef CONFIG_CACHE_L2X0
-       if (machine_is_msm7x27_surf() || machine_is_msm7x27_ffa()) {
-               /* 7x27 has 256KB L2 cache:
-                       64Kb/Way and 4-Way Associativity;
-                       R/W latency: 3 cycles;
-                       evmon/parity/share disabled. */
-               l2x0_init(MSM_L2CC_BASE, 0x00068012, 0xfe000000);
-       }
-#endif
-}
-
-static void __init msm7x2x_init_late(void)
-{
-       smd_debugfs_init();
-}
-
-MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF")
-       .atag_offset    = 0x100,
-       .map_io         = msm7x2x_map_io,
-       .init_irq       = msm7x2x_init_irq,
-       .init_machine   = msm7x2x_init,
-       .init_late      = msm7x2x_init_late,
-       .timer          = &msm_timer,
-MACHINE_END
-
-MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA")
-       .atag_offset    = 0x100,
-       .map_io         = msm7x2x_map_io,
-       .init_irq       = msm7x2x_init_irq,
-       .init_machine   = msm7x2x_init,
-       .init_late      = msm7x2x_init_late,
-       .timer          = &msm_timer,
-MACHINE_END
-
-MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF")
-       .atag_offset    = 0x100,
-       .map_io         = msm7x2x_map_io,
-       .init_irq       = msm7x2x_init_irq,
-       .init_machine   = msm7x2x_init,
-       .init_late      = msm7x2x_init_late,
-       .timer          = &msm_timer,
-MACHINE_END
-
-MACHINE_START(MSM7X25_FFA, "QCT MSM7x25 FFA")
-       .atag_offset    = 0x100,
-       .map_io         = msm7x2x_map_io,
-       .init_irq       = msm7x2x_init_irq,
-       .init_machine   = msm7x2x_init,
-       .init_late      = msm7x2x_init_late,
-       .timer          = &msm_timer,
-MACHINE_END
index 2e569ab..b7b0fc7 100644 (file)
@@ -27,7 +27,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
-#include <mach/system.h>
 #include <mach/vreg.h>
 #include <mach/board.h>
 
index 63b7113..a52c970 100644 (file)
@@ -25,7 +25,7 @@
 /*
  * glue for the proc_comm interface
  */
-int pc_clk_enable(unsigned id)
+static int pc_clk_enable(unsigned id)
 {
        int rc = msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL);
        if (rc < 0)
@@ -34,7 +34,7 @@ int pc_clk_enable(unsigned id)
                return (int)id < 0 ? -EINVAL : 0;
 }
 
-void pc_clk_disable(unsigned id)
+static void pc_clk_disable(unsigned id)
 {
        msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL);
 }
@@ -54,7 +54,7 @@ int pc_clk_reset(unsigned id, enum clk_reset_action action)
                return (int)id < 0 ? -EINVAL : 0;
 }
 
-int pc_clk_set_rate(unsigned id, unsigned rate)
+static int pc_clk_set_rate(unsigned id, unsigned rate)
 {
        /* The rate _might_ be rounded off to the nearest KHz value by the
         * remote function. So a return value of 0 doesn't necessarily mean
@@ -67,7 +67,7 @@ int pc_clk_set_rate(unsigned id, unsigned rate)
                return (int)id < 0 ? -EINVAL : 0;
 }
 
-int pc_clk_set_min_rate(unsigned id, unsigned rate)
+static int pc_clk_set_min_rate(unsigned id, unsigned rate)
 {
        int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate);
        if (rc < 0)
@@ -76,7 +76,7 @@ int pc_clk_set_min_rate(unsigned id, unsigned rate)
                return (int)id < 0 ? -EINVAL : 0;
 }
 
-int pc_clk_set_max_rate(unsigned id, unsigned rate)
+static int pc_clk_set_max_rate(unsigned id, unsigned rate)
 {
        int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MAX_RATE, &id, &rate);
        if (rc < 0)
@@ -85,7 +85,7 @@ int pc_clk_set_max_rate(unsigned id, unsigned rate)
                return (int)id < 0 ? -EINVAL : 0;
 }
 
-int pc_clk_set_flags(unsigned id, unsigned flags)
+static int pc_clk_set_flags(unsigned id, unsigned flags)
 {
        int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_FLAGS, &id, &flags);
        if (rc < 0)
@@ -94,7 +94,7 @@ int pc_clk_set_flags(unsigned id, unsigned flags)
                return (int)id < 0 ? -EINVAL : 0;
 }
 
-unsigned pc_clk_get_rate(unsigned id)
+static unsigned pc_clk_get_rate(unsigned id)
 {
        if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL))
                return 0;
@@ -102,7 +102,7 @@ unsigned pc_clk_get_rate(unsigned id)
                return id;
 }
 
-unsigned pc_clk_is_enabled(unsigned id)
+static unsigned pc_clk_is_enabled(unsigned id)
 {
        if (msm_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL))
                return 0;
@@ -110,7 +110,7 @@ unsigned pc_clk_is_enabled(unsigned id)
                return id;
 }
 
-long pc_clk_round_rate(unsigned id, unsigned rate)
+static long pc_clk_round_rate(unsigned id, unsigned rate)
 {
 
        /* Not really supported; pc_clk_set_rate() does rounding on it's own. */
index 02cae5e..354b91d 100644 (file)
@@ -223,8 +223,7 @@ static irqreturn_t msm_datamover_irq_handler(int irq, void *dev_id)
                        PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status);
                        if ((ch_status & DMOV_STATUS_CMD_PTR_RDY) && !list_empty(&ready_commands[id])) {
                                cmd = list_entry(ready_commands[id].next, typeof(*cmd), list);
-                               list_del(&cmd->list);
-                               list_add_tail(&cmd->list, &active_commands[id]);
+                               list_move_tail(&cmd->list, &active_commands[id]);
                                if (cmd->execute_func)
                                        cmd->execute_func(cmd);
                                PRINT_FLOW("msm_datamover_irq_handler id %d, start command\n", id);
diff --git a/arch/arm/mach-msm/idle.c b/arch/arm/mach-msm/idle.c
deleted file mode 100644 (file)
index 0c9e13c..0000000
+++ /dev/null
@@ -1,49 +0,0 @@
-/* arch/arm/mach-msm/idle.c
- *
- * Idle processing for MSM7K - work around bugs with SWFI.
- *
- * Copyright (c) 2007 QUALCOMM Incorporated.
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/init.h>
-#include <asm/system.h>
-
-static void msm_idle(void)
-{
-#ifdef CONFIG_MSM7X00A_IDLE
-       asm volatile (
-
-       "mrc     p15, 0, r1, c1, c0, 0    /* read current CR    */ \n\t"
-       "bic     r0, r1, #(1 << 2)        /* clear dcache bit   */ \n\t"
-       "bic     r0, r0, #(1 << 12)       /* clear icache bit   */ \n\t"
-       "mcr     p15, 0, r0, c1, c0, 0    /* disable d/i cache  */ \n\t"
-
-       "mov     r0, #0                   /* prepare wfi value  */ \n\t"
-       "mcr     p15, 0, r0, c7, c10, 0   /* flush the cache    */ \n\t"
-       "mcr     p15, 0, r0, c7, c10, 4   /* memory barrier     */ \n\t"
-       "mcr     p15, 0, r0, c7, c0, 4    /* wait for interrupt */ \n\t"
-
-       "mcr     p15, 0, r1, c1, c0, 0    /* restore d/i cache  */ \n\t"
-
-       : : : "r0","r1" );
-#endif
-}
-
-static int __init msm_idle_init(void)
-{
-       arm_pm_idle = msm_idle;
-       return 0;
-}
-
-arch_initcall(msm_idle_init);
index 435f8ed..5a0811a 100644 (file)
 
 /* platform device data structures */
 
-struct msm_acpu_clock_platform_data
-{
-       uint32_t acpu_switch_time_us;
-       uint32_t max_speed_delta_khz;
-       uint32_t vdd_switch_time_us;
-       unsigned long power_collapse_khz;
-       unsigned long wait_for_irq_khz;
-};
-
 struct clk_lookup;
 
 extern struct sys_timer msm_timer;
@@ -42,7 +33,6 @@ void __init msm_map_common_io(void);
 void __init msm_init_irq(void);
 void __init msm_init_gpio(void);
 void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks);
-void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *);
 int __init msm_add_sdcc(unsigned int controller,
                        struct msm_mmc_platform_data *plat,
                        unsigned int stat_irq, unsigned long stat_irq_flags);
diff --git a/arch/arm/mach-msm/include/mach/system.h b/arch/arm/mach-msm/include/mach/system.h
deleted file mode 100644 (file)
index f5fb2ec..0000000
+++ /dev/null
@@ -1,19 +0,0 @@
-/* arch/arm/mach-msm/include/mach/system.h
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-/* low level hardware reset hook -- for example, hitting the
- * PSHOLD line on the PMIC to hard reset the system
- */
-extern void (*msm_hw_reset_hook)(void);
index af43f6a..3cb4f4c 100644 (file)
@@ -42,8 +42,7 @@
                MSM_CHIP_DEVICE_TYPE(name, chip, MT_DEVICE)
 #define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM)
 
-#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X27) \
-       || defined(CONFIG_ARCH_MSM7X25)
+#if defined(CONFIG_ARCH_MSM7X00A)
 static struct map_desc msm_io_desc[] __initdata = {
        MSM_DEVICE_TYPE(VIC, MT_DEVICE_NONSHARED),
        MSM_CHIP_DEVICE_TYPE(CSR, MSM7X00, MT_DEVICE_NONSHARED),
index 9980dc7..8f1eecd 100644 (file)
@@ -19,7 +19,6 @@
 #include <linux/io.h>
 #include <linux/spinlock.h>
 #include <mach/msm_iomap.h>
-#include <mach/system.h>
 
 #include "proc_comm.h"
 
index 657be73..c5a2edd 100644 (file)
@@ -30,7 +30,6 @@
 #include <linux/delay.h>
 
 #include <mach/msm_smd.h>
-#include <mach/system.h>
 
 #include "smd_private.h"
 #include "proc_comm.h"
@@ -39,8 +38,6 @@
 #define CONFIG_QDSP6 1
 #endif
 
-void (*msm_hw_reset_hook)(void);
-
 #define MODULE_NAME "msm_smd"
 
 enum {
@@ -52,13 +49,14 @@ static int msm_smd_debug_mask;
 
 struct shared_info {
        int ready;
-       unsigned state;
+       void __iomem *state;
 };
 
 static unsigned dummy_state[SMSM_STATE_COUNT];
 
 static struct shared_info smd_info = {
-       .state = (unsigned) &dummy_state,
+       /* FIXME: not a real __iomem pointer */
+       .state = &dummy_state,
 };
 
 module_param_named(debug_mask, msm_smd_debug_mask,
@@ -101,10 +99,6 @@ static void handle_modem_crash(void)
        pr_err("ARM9 has CRASHED\n");
        smd_diag();
 
-       /* hard reboot if possible */
-       if (msm_hw_reset_hook)
-               msm_hw_reset_hook();
-
        /* in this case the modem or watchdog should reboot us */
        for (;;)
                ;
@@ -796,22 +790,22 @@ void *smem_alloc(unsigned id, unsigned size)
        return smem_find(id, size);
 }
 
-void *smem_item(unsigned id, unsigned *size)
+void __iomem *smem_item(unsigned id, unsigned *size)
 {
        struct smem_shared *shared = (void *) MSM_SHARED_RAM_BASE;
        struct smem_heap_entry *toc = shared->heap_toc;
 
        if (id >= SMEM_NUM_ITEMS)
-               return 0;
+               return NULL;
 
        if (toc[id].allocated) {
                *size = toc[id].size;
-               return (void *) (MSM_SHARED_RAM_BASE + toc[id].offset);
+               return (MSM_SHARED_RAM_BASE + toc[id].offset);
        } else {
                *size = 0;
        }
 
-       return 0;
+       return NULL;
 }
 
 void *smem_find(unsigned id, unsigned size_in)
@@ -857,7 +851,7 @@ static irqreturn_t smsm_irq_handler(int irq, void *data)
 int smsm_change_state(enum smsm_state_item item,
                      uint32_t clear_mask, uint32_t set_mask)
 {
-       unsigned long addr = smd_info.state + item * 4;
+       void __iomem *addr = smd_info.state + item * 4;
        unsigned long flags;
        unsigned state;
 
@@ -943,10 +937,10 @@ int smd_core_init(void)
        /* wait for essential items to be initialized */
        for (;;) {
                unsigned size;
-               void *state;
+               void __iomem *state;
                state = smem_item(SMEM_SMSM_SHARED_STATE, &size);
                if (size == SMSM_V1_SIZE || size == SMSM_V2_SIZE) {
-                       smd_info.state = (unsigned)state;
+                       smd_info.state = state;
                        break;
                }
        }
index 8128082..004f935 100644 (file)
@@ -101,7 +101,7 @@ static struct clock_event_device msm_clockevent = {
 
 static union {
        struct clock_event_device *evt;
-       struct clock_event_device __percpu **percpu_evt;
+       struct clock_event_device * __percpu *percpu_evt;
 } msm_evt;
 
 static void __iomem *source_base;
index a9bc841..137e479 100644 (file)
@@ -13,6 +13,7 @@
 #include <linux/mbus.h>
 #include <linux/io.h>
 #include <plat/addr-map.h>
+#include <mach/mv78xx0.h>
 #include "common.h"
 
 /*
@@ -81,7 +82,7 @@ void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
                                      int maj, int min)
 {
        orion_setup_cpu_win(&addr_map_cfg, window, base, size,
-                           TARGET_PCIE(maj), ATTR_PCIE_IO(min), -1);
+                           TARGET_PCIE(maj), ATTR_PCIE_IO(min), 0);
 }
 
 void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
index 3057f7d..6b0c387 100644 (file)
@@ -135,11 +135,6 @@ static struct map_desc mv78xx0_io_desc[] __initdata = {
                .length         = MV78XX0_CORE_REGS_SIZE,
                .type           = MT_DEVICE,
        }, {
-               .virtual        = MV78XX0_PCIE_IO_VIRT_BASE(0),
-               .pfn            = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)),
-               .length         = MV78XX0_PCIE_IO_SIZE * 8,
-               .type           = MT_DEVICE,
-       }, {
                .virtual        = MV78XX0_REGS_VIRT_BASE,
                .pfn            = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
                .length         = MV78XX0_REGS_SIZE,
diff --git a/arch/arm/mach-mv78xx0/include/mach/io.h b/arch/arm/mach-mv78xx0/include/mach/io.h
deleted file mode 100644 (file)
index c7d9d00..0000000
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * arch/arm/mach-mv78xx0/include/mach/io.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#include "mv78xx0.h"
-
-#define IO_SPACE_LIMIT         0xffffffff
-
-static inline void __iomem *__io(unsigned long addr)
-{
-       return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0))
-                                       + MV78XX0_PCIE_IO_VIRT_BASE(0));
-}
-
-#define __io(a)                        __io(a)
-
-#endif
index e807c4c..bd03fed 100644 (file)
  *
  * virt                phys            size
  * fe400000    f102x000        16K     core-specific peripheral registers
- * fe700000    f0800000        1M      PCIe #0 I/O space
- * fe800000    f0900000        1M      PCIe #1 I/O space
- * fe900000    f0a00000        1M      PCIe #2 I/O space
- * fea00000    f0b00000        1M      PCIe #3 I/O space
- * feb00000    f0c00000        1M      PCIe #4 I/O space
- * fec00000    f0d00000        1M      PCIe #5 I/O space
- * fed00000    f0e00000        1M      PCIe #6 I/O space
- * fee00000    f0f00000        1M      PCIe #7 I/O space
- * fef00000    f1000000        1M      on-chip peripheral registers
+ * fee00000    f0800000        64K     PCIe #0 I/O space
+ * fee10000    f0900000        64K     PCIe #1 I/O space
+ * fee20000    f0a00000        64K     PCIe #2 I/O space
+ * fee30000    f0b00000        64K     PCIe #3 I/O space
+ * fee40000    f0c00000        64K     PCIe #4 I/O space
+ * fee50000    f0d00000        64K     PCIe #5 I/O space
+ * fee60000    f0e00000        64K     PCIe #6 I/O space
+ * fee70000    f0f00000        64K     PCIe #7 I/O space
+ * fd000000    f1000000        1M      on-chip peripheral registers
  */
 #define MV78XX0_CORE0_REGS_PHYS_BASE   0xf1020000
 #define MV78XX0_CORE1_REGS_PHYS_BASE   0xf1024000
 #define MV78XX0_CORE_REGS_SIZE         SZ_16K
 
 #define MV78XX0_PCIE_IO_PHYS_BASE(i)   (0xf0800000 + ((i) << 20))
-#define MV78XX0_PCIE_IO_VIRT_BASE(i)   (0xfe700000 + ((i) << 20))
 #define MV78XX0_PCIE_IO_SIZE           SZ_1M
 
 #define MV78XX0_REGS_PHYS_BASE         0xf1000000
-#define MV78XX0_REGS_VIRT_BASE         0xfef00000
+#define MV78XX0_REGS_VIRT_BASE         0xfd000000
 #define MV78XX0_REGS_SIZE              SZ_1M
 
 #define MV78XX0_PCIE_MEM_PHYS_BASE     0xc0000000
index 2e56e86..26a059b 100644 (file)
@@ -15,6 +15,7 @@
 #include <asm/mach/pci.h>
 #include <plat/pcie.h>
 #include <plat/addr-map.h>
+#include <mach/mv78xx0.h>
 #include "common.h"
 
 struct pcie_port {
@@ -23,16 +24,13 @@ struct pcie_port {
        u8                      root_bus_nr;
        void __iomem            *base;
        spinlock_t              conf_lock;
-       char                    io_space_name[16];
        char                    mem_space_name[16];
-       struct resource         res[2];
+       struct resource         res;
 };
 
 static struct pcie_port pcie_port[8];
 static int num_pcie_ports;
 static struct resource pcie_io_space;
-static struct resource pcie_mem_space;
-
 
 void __init mv78xx0_pcie_id(u32 *dev, u32 *rev)
 {
@@ -40,102 +38,59 @@ void __init mv78xx0_pcie_id(u32 *dev, u32 *rev)
        *rev = orion_pcie_rev((void __iomem *)PCIE00_VIRT_BASE);
 }
 
+u32 pcie_port_size[8] = {
+       0,
+       0x30000000,
+       0x10000000,
+       0x10000000,
+       0x08000000,
+       0x08000000,
+       0x08000000,
+       0x04000000,
+};
+
 static void __init mv78xx0_pcie_preinit(void)
 {
        int i;
        u32 size_each;
        u32 start;
-       int win;
+       int win = 0;
 
        pcie_io_space.name = "PCIe I/O Space";
        pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0);
        pcie_io_space.end =
                MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1;
-       pcie_io_space.flags = IORESOURCE_IO;
+       pcie_io_space.flags = IORESOURCE_MEM;
        if (request_resource(&iomem_resource, &pcie_io_space))
                panic("can't allocate PCIe I/O space");
 
-       pcie_mem_space.name = "PCIe MEM Space";
-       pcie_mem_space.start = MV78XX0_PCIE_MEM_PHYS_BASE;
-       pcie_mem_space.end =
-               MV78XX0_PCIE_MEM_PHYS_BASE + MV78XX0_PCIE_MEM_SIZE - 1;
-       pcie_mem_space.flags = IORESOURCE_MEM;
-       if (request_resource(&iomem_resource, &pcie_mem_space))
-               panic("can't allocate PCIe MEM space");
+       if (num_pcie_ports > 7)
+               panic("invalid number of PCIe ports");
+
+       size_each = pcie_port_size[num_pcie_ports];
 
+       start = MV78XX0_PCIE_MEM_PHYS_BASE;
        for (i = 0; i < num_pcie_ports; i++) {
                struct pcie_port *pp = pcie_port + i;
 
-               snprintf(pp->io_space_name, sizeof(pp->io_space_name),
-                       "PCIe %d.%d I/O", pp->maj, pp->min);
-               pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
-               pp->res[0].name = pp->io_space_name;
-               pp->res[0].start = MV78XX0_PCIE_IO_PHYS_BASE(i);
-               pp->res[0].end = pp->res[0].start + MV78XX0_PCIE_IO_SIZE - 1;
-               pp->res[0].flags = IORESOURCE_IO;
-
                snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
                        "PCIe %d.%d MEM", pp->maj, pp->min);
                pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
-               pp->res[1].name = pp->mem_space_name;
-               pp->res[1].flags = IORESOURCE_MEM;
-       }
-
-       switch (num_pcie_ports) {
-       case 0:
-               size_each = 0;
-               break;
-
-       case 1:
-               size_each = 0x30000000;
-               break;
-
-       case 2 ... 3:
-               size_each = 0x10000000;
-               break;
-
-       case 4 ... 6:
-               size_each = 0x08000000;
-               break;
-
-       case 7:
-               size_each = 0x04000000;
-               break;
-
-       default:
-               panic("invalid number of PCIe ports");
-       }
-
-       start = MV78XX0_PCIE_MEM_PHYS_BASE;
-       for (i = 0; i < num_pcie_ports; i++) {
-               struct pcie_port *pp = pcie_port + i;
-
-               pp->res[1].start = start;
-               pp->res[1].end = start + size_each - 1;
+               pp->res.name = pp->mem_space_name;
+               pp->res.flags = IORESOURCE_MEM;
+               pp->res.start = start;
+               pp->res.end = start + size_each - 1;
                start += size_each;
-       }
-
-       for (i = 0; i < num_pcie_ports; i++) {
-               struct pcie_port *pp = pcie_port + i;
 
-               if (request_resource(&pcie_io_space, &pp->res[0]))
-                       panic("can't allocate PCIe I/O sub-space");
-
-               if (request_resource(&pcie_mem_space, &pp->res[1]))
+               if (request_resource(&iomem_resource, &pp->res))
                        panic("can't allocate PCIe MEM sub-space");
-       }
 
-       win = 0;
-       for (i = 0; i < num_pcie_ports; i++) {
-               struct pcie_port *pp = pcie_port + i;
+               mv78xx0_setup_pcie_mem_win(win + i + 8, pp->res.start,
+                                          resource_size(&pp->res),
+                                          pp->maj, pp->min);
 
-               mv78xx0_setup_pcie_io_win(win++, pp->res[0].start,
-                                         resource_size(&pp->res[0]),
+               mv78xx0_setup_pcie_io_win(win + i, i * SZ_64K, SZ_64K,
                                          pp->maj, pp->min);
-
-               mv78xx0_setup_pcie_mem_win(win++, pp->res[1].start,
-                                          resource_size(&pp->res[1]),
-                                          pp->maj, pp->min);
        }
 }
 
@@ -156,8 +111,9 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
        orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
        orion_pcie_setup(pp->base);
 
-       pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
-       pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
+       pci_ioremap_io(nr * SZ_64K, MV78XX0_PCIE_IO_PHYS_BASE(nr));
+
+       pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
 
        return 1;
 }
@@ -281,7 +237,7 @@ static void __init add_pcie_port(int maj, int min, unsigned long base)
                pp->root_bus_nr = -1;
                pp->base = (void __iomem *)base;
                spin_lock_init(&pp->conf_lock);
-               memset(pp->res, 0, sizeof(pp->res));
+               memset(&pp->res, 0, sizeof(pp->res));
        } else {
                printk("link down, ignoring\n");
        }
index 6316dba..02035e4 100644 (file)
@@ -30,7 +30,7 @@
                        - NOMADIK_IO_VIRTUAL + NOMADIK_IO_PHYSICAL)
 
 /* used in asm code, so no casts */
-#define IO_ADDRESS(x) ((x) - NOMADIK_IO_PHYSICAL + NOMADIK_IO_VIRTUAL)
+#define IO_ADDRESS(x) IOMEM((x) - NOMADIK_IO_PHYSICAL + NOMADIK_IO_VIRTUAL)
 
 /*
  *   Base address defination for Nomadik Onchip Logic Block
index 071003b..7d4687e 100644 (file)
 struct amba_device;
 #include <linux/amba/serial.h>
 
-#define NOMADIK_UART_DR                0x101FB000
-#define NOMADIK_UART_LCRH      0x101FB02c
-#define NOMADIK_UART_CR                0x101FB030
-#define NOMADIK_UART_FR                0x101FB018
+#define NOMADIK_UART_DR                (void __iomem *)0x101FB000
+#define NOMADIK_UART_LCRH      (void __iomem *)0x101FB02c
+#define NOMADIK_UART_CR                (void __iomem *)0x101FB030
+#define NOMADIK_UART_FR                (void __iomem *)0x101FB018
 
 static void putc(const char c)
 {
index a051cb8..3d1e1c2 100644 (file)
@@ -16,8 +16,9 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
-#include <plat/board-ams-delta.h>
+#include <mach/board-ams-delta.h>
 
+#include <mach/irqs.h>
 #include <mach/ams-delta-fiq.h>
 
 #include "iomap.h"
index 68e8e56..f12a12a 100644 (file)
@@ -19,7 +19,7 @@
 #include <linux/module.h>
 #include <linux/io.h>
 
-#include <plat/board-ams-delta.h>
+#include <mach/board-ams-delta.h>
 
 #include <asm/fiq.h>
 
index c534698..9518bf5 100644 (file)
@@ -26,6 +26,7 @@
 #include <linux/export.h>
 #include <linux/omapfb.h>
 #include <linux/io.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <media/soc_camera.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board-ams-delta.h>
-#include <plat/keypad.h>
-#include <plat/mux.h>
-#include <plat/board.h>
+#include <mach/board-ams-delta.h>
+#include <linux/platform_data/keypad-omap.h>
+#include <mach/mux.h>
 
 #include <mach/hardware.h>
 #include <mach/ams-delta-fiq.h>
index 6872f3f..4b6de70 100644 (file)
 #include <asm/mach/map.h>
 
 #include <plat/tc.h>
-#include <plat/mux.h>
-#include <plat/flash.h>
+#include <mach/mux.h>
+#include <mach/flash.h>
 #include <plat/fpga.h>
-#include <plat/keypad.h>
-#include <plat/board.h>
+#include <linux/platform_data/keypad-omap.h>
 
 #include <mach/hardware.h>
 
index 6ec385e..4ec579f 100644 (file)
@@ -22,8 +22,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/mux.h>
-#include <plat/board.h>
+#include <mach/mux.h>
 
 #include <mach/usb.h>
 
@@ -52,9 +51,6 @@ static struct omap_usb_config generic1610_usb_config __initdata = {
 };
 #endif
 
-static struct omap_board_config_kernel generic_config[] __initdata = {
-};
-
 static void __init omap_generic_init(void)
 {
 #ifdef CONFIG_ARCH_OMAP15XX
@@ -76,8 +72,6 @@ static void __init omap_generic_init(void)
        }
 #endif
 
-       omap_board_config = generic_config;
-       omap_board_config_size = ARRAY_SIZE(generic_config);
        omap_serial_init();
        omap_register_i2c_bus(1, 100, NULL, 0);
 }
index 44a4ab1..af283a2 100644 (file)
 #include <linux/i2c/tps65010.h>
 #include <linux/smc91x.h>
 #include <linux/omapfb.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/dma.h>
 #include <plat/tc.h>
-#include <plat/irda.h>
-#include <plat/keypad.h>
-#include <plat/flash.h>
+#include <mach/irda.h>
+#include <linux/platform_data/keypad-omap.h>
+#include <mach/flash.h>
 
 #include <mach/hardware.h>
 #include <mach/usb.h>
index 86cb5a0..06d11b1 100644 (file)
@@ -31,6 +31,7 @@
 #include <linux/i2c/tps65010.h>
 #include <linux/smc91x.h>
 #include <linux/omapfb.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <asm/setup.h>
 #include <asm/page.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/tc.h>
-#include <plat/keypad.h>
+#include <linux/platform_data/keypad-omap.h>
 #include <plat/dma.h>
-#include <plat/flash.h>
+#include <mach/flash.h>
 
 #include <mach/hardware.h>
 #include <mach/irqs.h>
index b3f6e94..87ab208 100644 (file)
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 #include <linux/omapfb.h>
+#include <linux/platform_data/keypad-omap.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <plat/omap7xx.h>
-#include <plat/board.h>
-#include <plat/keypad.h>
+#include <mach/omap7xx.h>
 #include <plat/mmc.h>
 
 #include <mach/irqs.h>
@@ -476,8 +475,7 @@ static void __init htcherald_lcd_init(void)
                                break;
                }
                if (!tries)
-                       printk(KERN_WARNING "Timeout waiting for end of frame "
-                              "-- LCD may not be available\n");
+                       pr_err("Timeout waiting for end of frame -- LCD may not be available\n");
 
                /* turn off DMA */
                reg = omap_readw(OMAP_DMA_LCD_CCR);
index f21c296..db5f7d2 100644 (file)
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/mux.h>
-#include <plat/flash.h>
+#include <mach/mux.h>
+#include <mach/flash.h>
 #include <plat/fpga.h>
 #include <plat/tc.h>
-#include <plat/keypad.h>
+#include <linux/platform_data/keypad-omap.h>
 #include <plat/mmc.h>
 
 #include <mach/hardware.h>
index 2c0ca8f..7d5c06d 100644 (file)
 #include <linux/workqueue.h>
 #include <linux/delay.h>
 
+#include <linux/platform_data/keypad-omap.h>
+#include <linux/platform_data/lcd-mipid.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/mux.h>
-#include <plat/board.h>
-#include <plat/keypad.h>
-#include <plat/lcd_mipid.h>
+#include <mach/mux.h>
 #include <plat/mmc.h>
 #include <plat/clock.h>
 
index 8784705..2f1f9b9 100644 (file)
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
 #include <linux/i2c/tps65010.h>
+#include <linux/platform_data/gpio-omap.h>
+#include <linux/platform_data/omap1_bl.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/flash.h>
-#include <plat/mux.h>
+#include <mach/flash.h>
+#include <mach/mux.h>
 #include <plat/tc.h>
 
 #include <mach/hardware.h>
@@ -302,7 +304,7 @@ static struct omap_lcd_config osk_lcd_config __initdata = {
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 
-#include <plat/keypad.h>
+#include <linux/platform_data/keypad-omap.h>
 
 static struct at24_platform_data at24c04 = {
        .byte_len       = SZ_4K / 8,
index 26bcb9d..1c578d5 100644 (file)
 #include <linux/interrupt.h>
 #include <linux/apm-emulation.h>
 #include <linux/omapfb.h>
+#include <linux/platform_data/omap1_bl.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/flash.h>
-#include <plat/mux.h>
+#include <mach/flash.h>
+#include <mach/mux.h>
 #include <plat/tc.h>
 #include <plat/dma.h>
-#include <plat/board.h>
-#include <plat/irda.h>
-#include <plat/keypad.h>
+#include <mach/irda.h>
+#include <linux/platform_data/keypad-omap.h>
 
 #include <mach/hardware.h>
 #include <mach/usb.h>
index 4d09944..9715809 100644 (file)
 #include <linux/omapfb.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
+#include <linux/platform_data/omap1_bl.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
 #include <plat/led.h>
-#include <plat/flash.h>
-#include <plat/mux.h>
+#include <mach/flash.h>
+#include <mach/mux.h>
 #include <plat/dma.h>
 #include <plat/tc.h>
-#include <plat/board.h>
-#include <plat/irda.h>
-#include <plat/keypad.h>
+#include <mach/irda.h>
+#include <linux/platform_data/keypad-omap.h>
 
 #include <mach/hardware.h>
 #include <mach/usb.h>
index 3559803..e311032 100644 (file)
 #include <linux/omapfb.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
+#include <linux/platform_data/omap1_bl.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/flash.h>
-#include <plat/mux.h>
+#include <mach/flash.h>
+#include <mach/mux.h>
 #include <plat/dma.h>
 #include <plat/tc.h>
-#include <plat/board.h>
-#include <plat/irda.h>
-#include <plat/keypad.h>
+#include <mach/irda.h>
+#include <linux/platform_data/keypad-omap.h>
 
 #include <mach/hardware.h>
 #include <mach/usb.h>
index 703d55e..198b054 100644 (file)
 #include <linux/input.h>
 #include <linux/smc91x.h>
 #include <linux/omapfb.h>
+#include <linux/platform_data/keypad-omap.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
 #include <plat/tc.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/fpga.h>
-#include <plat/flash.h>
-#include <plat/keypad.h>
-#include <plat/board.h>
+#include <mach/flash.h>
 
 #include <mach/hardware.h>
 
index b59f788..5932d56 100644 (file)
@@ -17,7 +17,7 @@
 
 #include <mach/hardware.h>
 #include <plat/mmc.h>
-#include <plat/board-sx1.h>
+#include <mach/board-sx1.h>
 
 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
 
index 8c665bd..13bf2cc 100644 (file)
 #include <linux/errno.h>
 #include <linux/export.h>
 #include <linux/omapfb.h>
+#include <linux/platform_data/keypad-omap.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/flash.h>
-#include <plat/mux.h>
+#include <mach/flash.h>
+#include <mach/mux.h>
 #include <plat/dma.h>
-#include <plat/irda.h>
+#include <mach/irda.h>
 #include <plat/tc.h>
-#include <plat/board.h>
-#include <plat/keypad.h>
-#include <plat/board-sx1.h>
+#include <mach/board-sx1.h>
 
 #include <mach/hardware.h>
 #include <mach/usb.h>
index 3497769..ad75e34 100644 (file)
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board-voiceblue.h>
-#include <plat/flash.h>
-#include <plat/mux.h>
+#include <mach/board-voiceblue.h>
+#include <mach/flash.h>
+#include <mach/mux.h>
 #include <plat/tc.h>
-#include <plat/board.h>
 
 #include <mach/hardware.h>
 #include <mach/usb.h>
@@ -155,9 +154,6 @@ static struct omap_usb_config voiceblue_usb_config __initdata = {
        .pins[2]        = 6,
 };
 
-static struct omap_board_config_kernel voiceblue_config[] = {
-};
-
 #define MACHINE_PANICED                1
 #define MACHINE_REBOOTING      2
 #define MACHINE_REBOOT         4
@@ -275,8 +271,6 @@ static void __init voiceblue_init(void)
        voiceblue_smc91x_resources[1].start = gpio_to_irq(8);
        voiceblue_smc91x_resources[1].end = gpio_to_irq(8);
        platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices));
-       omap_board_config = voiceblue_config;
-       omap_board_config_size = ARRAY_SIZE(voiceblue_config);
        omap_serial_init();
        omap1_usb_init(&voiceblue_usb_config);
        omap_register_i2c_bus(1, 100, NULL, 0);
index a9ee06b..638f407 100644 (file)
@@ -587,8 +587,8 @@ void omap1_clk_disable_unused(struct clk *clk)
        /* Clocks in the DSP domain need api_ck. Just assume bootloader
         * has not enabled any DSP clocks */
        if (clk->enable_reg == DSP_IDLECT2) {
-               printk(KERN_INFO "Skipping reset check for DSP domain "
-                      "clock \"%s\"\n", clk->name);
+               pr_info("Skipping reset check for DSP domain clock \"%s\"\n",
+                       clk->name);
                return;
        }
 
index c007d80..9b45f4b 100644 (file)
@@ -25,7 +25,6 @@
 #include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/clkdev_omap.h>
-#include <plat/board.h>
 #include <plat/sram.h> /* for omap_sram_reprogram_clock() */
 
 #include <mach/hardware.h>
@@ -776,11 +775,10 @@ static struct clk_functions omap1_clk_functions = {
 
 static void __init omap1_show_rates(void)
 {
-       pr_notice("Clocking rate (xtal/DPLL1/MPU): "
-                       "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
-               ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
-               ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
-               arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
+       pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
+                 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
+                 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
+                 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
 }
 
 u32 cpu_mask;
@@ -788,7 +786,6 @@ u32 cpu_mask;
 int __init omap1_clk_init(void)
 {
        struct omap_clk *c;
-       const struct omap_clock_config *info;
        int crystal_type = 0; /* Default 12 MHz */
        u32 reg;
 
@@ -837,19 +834,13 @@ int __init omap1_clk_init(void)
        ck_dpll1_p = clk_get(NULL, "ck_dpll1");
        ck_ref_p = clk_get(NULL, "ck_ref");
 
-       info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
-       if (info != NULL) {
-               if (!cpu_is_omap15xx())
-                       crystal_type = info->system_clock_type;
-       }
-
        if (cpu_is_omap7xx())
                ck_ref.rate = 13000000;
        if (cpu_is_omap16xx() && crystal_type == 2)
                ck_ref.rate = 19200000;
 
-       pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: "
-               "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
+       pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
+               omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
                omap_readw(ARM_CKCTL));
 
        /* We want to be in syncronous scalable mode */
index fa1fa4d..0cc54dd 100644 (file)
 #include <asm/mach/map.h>
 
 #include <plat/tc.h>
-#include <plat/board.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/dma.h>
 #include <plat/mmc.h>
-#include <plat/omap7xx.h>
 
+#include <mach/omap7xx.h>
 #include <mach/camera.h>
 #include <mach/hardware.h>
 
index 3ef7d52..29007fe 100644 (file)
@@ -27,7 +27,8 @@
 
 #include <plat/dma.h>
 #include <plat/tc.h>
-#include <plat/irqs.h>
+
+#include <mach/irqs.h>
 
 #define OMAP1_DMA_BASE                 (0xfffed800)
 #define OMAP1_LOGICAL_DMA_CH_COUNT     17
@@ -330,8 +331,9 @@ static int __init omap1_system_dma_init(void)
        d->chan = kzalloc(sizeof(struct omap_dma_lch) *
                                        (d->lch_count), GFP_KERNEL);
        if (!d->chan) {
-               dev_err(&pdev->dev, "%s: Memory allocation failed"
-                                       "for d->chan!!!\n", __func__);
+               dev_err(&pdev->dev,
+                       "%s: Memory allocation failed for d->chan!\n",
+                       __func__);
                goto exit_release_d;
        }
 
index 401eb3c..73ae616 100644 (file)
@@ -11,7 +11,7 @@
 #include <linux/mtd/map.h>
 
 #include <plat/tc.h>
-#include <plat/flash.h>
+#include <mach/flash.h>
 
 #include <mach/hardware.h>
 
index ebef15e..98e6f39 100644 (file)
@@ -17,6 +17,7 @@
  */
 
 #include <linux/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #define OMAP1_MPUIO_VBASE              OMAP1_MPUIO_BASE
 #define OMAP1510_GPIO_BASE             0xFFFCE000
index 2a48cd2..33f4192 100644 (file)
@@ -17,6 +17,7 @@
  */
 
 #include <linux/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #define OMAP1610_GPIO1_BASE            0xfffbe400
 #define OMAP1610_GPIO2_BASE            0xfffbec00
index acf12b7..958ce9a 100644 (file)
@@ -17,6 +17,7 @@
  */
 
 #include <linux/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #define OMAP7XX_GPIO1_BASE             0xfffbc000
 #define OMAP7XX_GPIO2_BASE             0xfffbc800
index 5446c99..a0551a6 100644 (file)
@@ -20,7 +20,7 @@
  */
 
 #include <plat/i2c.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/cpu.h>
 
 void __init omap1_i2c_mux_pins(int bus_id)
index 23eed00..adb5e76 100644 (file)
@@ -14,8 +14,6 @@
 #ifndef __AMS_DELTA_FIQ_H
 #define __AMS_DELTA_FIQ_H
 
-#include <plat/irqs.h>
-
 /*
  * Interrupt number used for passing control from FIQ to IRQ.
  * IRQ12, described as reserved, has been selected.
index e737706..ebf86c0 100644 (file)
@@ -1,5 +1,3 @@
 /*
  * arch/arm/mach-omap1/include/mach/gpio.h
  */
-
-#include <plat/gpio.h>
index 01e35fa..84248d2 100644 (file)
@@ -1,11 +1,46 @@
 /*
  * arch/arm/mach-omap1/include/mach/hardware.h
+ *
+ * Hardware definitions for TI OMAP processors and boards
+ *
+ * NOTE: Please put device driver specific defines into a separate header
+ *      file for each driver.
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
+ *                          and Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
-#ifndef __MACH_HARDWARE_H
-#define __MACH_HARDWARE_H
+#ifndef __ASM_ARCH_OMAP_HARDWARE_H
+#define __ASM_ARCH_OMAP_HARDWARE_H
 
+#include <asm/sizes.h>
 #ifndef __ASSEMBLER__
+#include <asm/types.h>
+#include <plat/cpu.h>
+
 /*
  * NOTE: Please use ioremap + __raw_read/write where possible instead of these
  */
@@ -35,7 +70,249 @@ static inline u32 omap_cs3_phys(void)
                        ? 0 : OMAP_CS3_PHYS;
 }
 
+#endif /* ifndef __ASSEMBLER__ */
+
+#include <plat/serial.h>
+
+/*
+ * ---------------------------------------------------------------------------
+ * Common definitions for all OMAP processors
+ * NOTE: Put all processor or board specific parts to the special header
+ *      files.
+ * ---------------------------------------------------------------------------
+ */
+
+/*
+ * ----------------------------------------------------------------------------
+ * Timers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP_MPU_TIMER1_BASE   (0xfffec500)
+#define OMAP_MPU_TIMER2_BASE   (0xfffec600)
+#define OMAP_MPU_TIMER3_BASE   (0xfffec700)
+#define MPU_TIMER_FREE         (1 << 6)
+#define MPU_TIMER_CLOCK_ENABLE (1 << 5)
+#define MPU_TIMER_AR           (1 << 1)
+#define MPU_TIMER_ST           (1 << 0)
+
+/*
+ * ----------------------------------------------------------------------------
+ * Clocks
+ * ----------------------------------------------------------------------------
+ */
+#define CLKGEN_REG_BASE                (0xfffece00)
+#define ARM_CKCTL              (CLKGEN_REG_BASE + 0x0)
+#define ARM_IDLECT1            (CLKGEN_REG_BASE + 0x4)
+#define ARM_IDLECT2            (CLKGEN_REG_BASE + 0x8)
+#define ARM_EWUPCT             (CLKGEN_REG_BASE + 0xC)
+#define ARM_RSTCT1             (CLKGEN_REG_BASE + 0x10)
+#define ARM_RSTCT2             (CLKGEN_REG_BASE + 0x14)
+#define ARM_SYSST              (CLKGEN_REG_BASE + 0x18)
+#define ARM_IDLECT3            (CLKGEN_REG_BASE + 0x24)
+
+#define CK_RATEF               1
+#define CK_IDLEF               2
+#define CK_ENABLEF             4
+#define CK_SELECTF             8
+#define SETARM_IDLE_SHIFT
+
+/* DPLL control registers */
+#define DPLL_CTL               (0xfffecf00)
+
+/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
+#define DSP_CONFIG_REG_BASE     IOMEM(0xe1008000)
+#define DSP_CKCTL              (DSP_CONFIG_REG_BASE + 0x0)
+#define DSP_IDLECT1            (DSP_CONFIG_REG_BASE + 0x4)
+#define DSP_IDLECT2            (DSP_CONFIG_REG_BASE + 0x8)
+#define DSP_RSTCT2             (DSP_CONFIG_REG_BASE + 0x14)
+
+/*
+ * ---------------------------------------------------------------------------
+ * UPLD
+ * ---------------------------------------------------------------------------
+ */
+#define ULPD_REG_BASE          (0xfffe0800)
+#define ULPD_IT_STATUS         (ULPD_REG_BASE + 0x14)
+#define ULPD_SETUP_ANALOG_CELL_3       (ULPD_REG_BASE + 0x24)
+#define ULPD_CLOCK_CTRL                (ULPD_REG_BASE + 0x30)
+#      define DIS_USB_PVCI_CLK         (1 << 5)        /* no USB/FAC synch */
+#      define USB_MCLK_EN              (1 << 4)        /* enable W4_USB_CLKO */
+#define ULPD_SOFT_REQ          (ULPD_REG_BASE + 0x34)
+#      define SOFT_UDC_REQ             (1 << 4)
+#      define SOFT_USB_CLK_REQ         (1 << 3)
+#      define SOFT_DPLL_REQ            (1 << 0)
+#define ULPD_DPLL_CTRL         (ULPD_REG_BASE + 0x3c)
+#define ULPD_STATUS_REQ                (ULPD_REG_BASE + 0x40)
+#define ULPD_APLL_CTRL         (ULPD_REG_BASE + 0x4c)
+#define ULPD_POWER_CTRL                (ULPD_REG_BASE + 0x50)
+#define ULPD_SOFT_DISABLE_REQ_REG      (ULPD_REG_BASE + 0x68)
+#      define DIS_MMC2_DPLL_REQ        (1 << 11)
+#      define DIS_MMC1_DPLL_REQ        (1 << 10)
+#      define DIS_UART3_DPLL_REQ       (1 << 9)
+#      define DIS_UART2_DPLL_REQ       (1 << 8)
+#      define DIS_UART1_DPLL_REQ       (1 << 7)
+#      define DIS_USB_HOST_DPLL_REQ    (1 << 6)
+#define ULPD_SDW_CLK_DIV_CTRL_SEL      (ULPD_REG_BASE + 0x74)
+#define ULPD_CAM_CLK_CTRL      (ULPD_REG_BASE + 0x7c)
+
+/*
+ * ---------------------------------------------------------------------------
+ * Watchdog timer
+ * ---------------------------------------------------------------------------
+ */
+
+/* Watchdog timer within the OMAP3.2 gigacell */
+#define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
+#define OMAP_WDT_TIMER         (OMAP_MPU_WATCHDOG_BASE + 0x0)
+#define OMAP_WDT_LOAD_TIM      (OMAP_MPU_WATCHDOG_BASE + 0x4)
+#define OMAP_WDT_READ_TIM      (OMAP_MPU_WATCHDOG_BASE + 0x4)
+#define OMAP_WDT_TIMER_MODE    (OMAP_MPU_WATCHDOG_BASE + 0x8)
+
+/*
+ * ---------------------------------------------------------------------------
+ * Interrupts
+ * ---------------------------------------------------------------------------
+ */
+#ifdef CONFIG_ARCH_OMAP1
+
+/*
+ * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
+ * or something similar.. -- PFM.
+ */
+
+#define OMAP_IH1_BASE          0xfffecb00
+#define OMAP_IH2_BASE          0xfffe0000
+
+#define OMAP_IH1_ITR           (OMAP_IH1_BASE + 0x00)
+#define OMAP_IH1_MIR           (OMAP_IH1_BASE + 0x04)
+#define OMAP_IH1_SIR_IRQ       (OMAP_IH1_BASE + 0x10)
+#define OMAP_IH1_SIR_FIQ       (OMAP_IH1_BASE + 0x14)
+#define OMAP_IH1_CONTROL       (OMAP_IH1_BASE + 0x18)
+#define OMAP_IH1_ILR0          (OMAP_IH1_BASE + 0x1c)
+#define OMAP_IH1_ISR           (OMAP_IH1_BASE + 0x9c)
+
+#define OMAP_IH2_ITR           (OMAP_IH2_BASE + 0x00)
+#define OMAP_IH2_MIR           (OMAP_IH2_BASE + 0x04)
+#define OMAP_IH2_SIR_IRQ       (OMAP_IH2_BASE + 0x10)
+#define OMAP_IH2_SIR_FIQ       (OMAP_IH2_BASE + 0x14)
+#define OMAP_IH2_CONTROL       (OMAP_IH2_BASE + 0x18)
+#define OMAP_IH2_ILR0          (OMAP_IH2_BASE + 0x1c)
+#define OMAP_IH2_ISR           (OMAP_IH2_BASE + 0x9c)
+
+#define IRQ_ITR_REG_OFFSET     0x00
+#define IRQ_MIR_REG_OFFSET     0x04
+#define IRQ_SIR_IRQ_REG_OFFSET 0x10
+#define IRQ_SIR_FIQ_REG_OFFSET 0x14
+#define IRQ_CONTROL_REG_OFFSET 0x18
+#define IRQ_ISR_REG_OFFSET     0x9c
+#define IRQ_ILR0_REG_OFFSET    0x1c
+#define IRQ_GMR_REG_OFFSET     0xa0
+
 #endif
-#endif
 
-#include <plat/hardware.h>
+/*
+ * ----------------------------------------------------------------------------
+ * System control registers
+ * ----------------------------------------------------------------------------
+ */
+#define MOD_CONF_CTRL_0                0xfffe1080
+#define MOD_CONF_CTRL_1                0xfffe1110
+
+/*
+ * ----------------------------------------------------------------------------
+ * Pin multiplexing registers
+ * ----------------------------------------------------------------------------
+ */
+#define FUNC_MUX_CTRL_0                0xfffe1000
+#define FUNC_MUX_CTRL_1                0xfffe1004
+#define FUNC_MUX_CTRL_2                0xfffe1008
+#define COMP_MODE_CTRL_0       0xfffe100c
+#define FUNC_MUX_CTRL_3                0xfffe1010
+#define FUNC_MUX_CTRL_4                0xfffe1014
+#define FUNC_MUX_CTRL_5                0xfffe1018
+#define FUNC_MUX_CTRL_6                0xfffe101C
+#define FUNC_MUX_CTRL_7                0xfffe1020
+#define FUNC_MUX_CTRL_8                0xfffe1024
+#define FUNC_MUX_CTRL_9                0xfffe1028
+#define FUNC_MUX_CTRL_A                0xfffe102C
+#define FUNC_MUX_CTRL_B                0xfffe1030
+#define FUNC_MUX_CTRL_C                0xfffe1034
+#define FUNC_MUX_CTRL_D                0xfffe1038
+#define PULL_DWN_CTRL_0                0xfffe1040
+#define PULL_DWN_CTRL_1                0xfffe1044
+#define PULL_DWN_CTRL_2                0xfffe1048
+#define PULL_DWN_CTRL_3                0xfffe104c
+#define PULL_DWN_CTRL_4                0xfffe10ac
+
+/* OMAP-1610 specific multiplexing registers */
+#define FUNC_MUX_CTRL_E                0xfffe1090
+#define FUNC_MUX_CTRL_F                0xfffe1094
+#define FUNC_MUX_CTRL_10       0xfffe1098
+#define FUNC_MUX_CTRL_11       0xfffe109c
+#define FUNC_MUX_CTRL_12       0xfffe10a0
+#define PU_PD_SEL_0            0xfffe10b4
+#define PU_PD_SEL_1            0xfffe10b8
+#define PU_PD_SEL_2            0xfffe10bc
+#define PU_PD_SEL_3            0xfffe10c0
+#define PU_PD_SEL_4            0xfffe10c4
+
+/* Timer32K for 1610 and 1710*/
+#define OMAP_TIMER32K_BASE     0xFFFBC400
+
+/*
+ * ---------------------------------------------------------------------------
+ * TIPB bus interface
+ * ---------------------------------------------------------------------------
+ */
+#define TIPB_PUBLIC_CNTL_BASE          0xfffed300
+#define MPU_PUBLIC_TIPB_CNTL           (TIPB_PUBLIC_CNTL_BASE + 0x8)
+#define TIPB_PRIVATE_CNTL_BASE         0xfffeca00
+#define MPU_PRIVATE_TIPB_CNTL          (TIPB_PRIVATE_CNTL_BASE + 0x8)
+
+/*
+ * ----------------------------------------------------------------------------
+ * MPUI interface
+ * ----------------------------------------------------------------------------
+ */
+#define MPUI_BASE                      (0xfffec900)
+#define MPUI_CTRL                      (MPUI_BASE + 0x0)
+#define MPUI_DEBUG_ADDR                        (MPUI_BASE + 0x4)
+#define MPUI_DEBUG_DATA                        (MPUI_BASE + 0x8)
+#define MPUI_DEBUG_FLAG                        (MPUI_BASE + 0xc)
+#define MPUI_STATUS_REG                        (MPUI_BASE + 0x10)
+#define MPUI_DSP_STATUS                        (MPUI_BASE + 0x14)
+#define MPUI_DSP_BOOT_CONFIG           (MPUI_BASE + 0x18)
+#define MPUI_DSP_API_CONFIG            (MPUI_BASE + 0x1c)
+
+/*
+ * ----------------------------------------------------------------------------
+ * LED Pulse Generator
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP_LPG1_BASE                 0xfffbd000
+#define OMAP_LPG2_BASE                 0xfffbd800
+#define OMAP_LPG1_LCR                  (OMAP_LPG1_BASE + 0x00)
+#define OMAP_LPG1_PMR                  (OMAP_LPG1_BASE + 0x04)
+#define OMAP_LPG2_LCR                  (OMAP_LPG2_BASE + 0x00)
+#define OMAP_LPG2_PMR                  (OMAP_LPG2_BASE + 0x04)
+
+/*
+ * ----------------------------------------------------------------------------
+ * Pulse-Width Light
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP_PWL_BASE                  0xfffb5800
+#define OMAP_PWL_ENABLE                        (OMAP_PWL_BASE + 0x00)
+#define OMAP_PWL_CLK_ENABLE            (OMAP_PWL_BASE + 0x04)
+
+/*
+ * ---------------------------------------------------------------------------
+ * Processor specific defines
+ * ---------------------------------------------------------------------------
+ */
+
+#include "omap7xx.h"
+#include "omap1510.h"
+#include "omap16xx.h"
+
+#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
index 9292fdc..729992d 100644 (file)
@@ -1,5 +1,268 @@
 /*
- * arch/arm/mach-omap1/include/mach/irqs.h
+ *  arch/arm/plat-omap/include/mach/irqs.h
+ *
+ *  Copyright (C) Greg Lonnon 2001
+ *  Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
+ *
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
+ *      are different.
  */
 
-#include <plat/irqs.h>
+#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
+#define __ASM_ARCH_OMAP15XX_IRQS_H
+
+/*
+ * IRQ numbers for interrupt handler 1
+ *
+ * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
+ *
+ */
+#define INT_CAMERA             1
+#define INT_FIQ                        3
+#define INT_RTDX               6
+#define INT_DSP_MMU_ABORT      7
+#define INT_HOST               8
+#define INT_ABORT              9
+#define INT_BRIDGE_PRIV                13
+#define INT_GPIO_BANK1         14
+#define INT_UART3              15
+#define INT_TIMER3             16
+#define INT_DMA_CH0_6          19
+#define INT_DMA_CH1_7          20
+#define INT_DMA_CH2_8          21
+#define INT_DMA_CH3            22
+#define INT_DMA_CH4            23
+#define INT_DMA_CH5            24
+#define INT_TIMER1             26
+#define INT_WD_TIMER           27
+#define INT_BRIDGE_PUB         28
+#define INT_TIMER2             30
+#define INT_LCD_CTRL           31
+
+/*
+ * OMAP-1510 specific IRQ numbers for interrupt handler 1
+ */
+#define INT_1510_IH2_IRQ       0
+#define INT_1510_RES2          2
+#define INT_1510_SPI_TX                4
+#define INT_1510_SPI_RX                5
+#define INT_1510_DSP_MAILBOX1  10
+#define INT_1510_DSP_MAILBOX2  11
+#define INT_1510_RES12         12
+#define INT_1510_LB_MMU                17
+#define INT_1510_RES18         18
+#define INT_1510_LOCAL_BUS     29
+
+/*
+ * OMAP-1610 specific IRQ numbers for interrupt handler 1
+ */
+#define INT_1610_IH2_IRQ       INT_1510_IH2_IRQ
+#define INT_1610_IH2_FIQ       2
+#define INT_1610_McBSP2_TX     4
+#define INT_1610_McBSP2_RX     5
+#define INT_1610_DSP_MAILBOX1  10
+#define INT_1610_DSP_MAILBOX2  11
+#define INT_1610_LCD_LINE      12
+#define INT_1610_GPTIMER1      17
+#define INT_1610_GPTIMER2      18
+#define INT_1610_SSR_FIFO_0    29
+
+/*
+ * OMAP-7xx specific IRQ numbers for interrupt handler 1
+ */
+#define INT_7XX_IH2_FIQ                0
+#define INT_7XX_IH2_IRQ                1
+#define INT_7XX_USB_NON_ISO    2
+#define INT_7XX_USB_ISO                3
+#define INT_7XX_ICR            4
+#define INT_7XX_EAC            5
+#define INT_7XX_GPIO_BANK1     6
+#define INT_7XX_GPIO_BANK2     7
+#define INT_7XX_GPIO_BANK3     8
+#define INT_7XX_McBSP2TX       10
+#define INT_7XX_McBSP2RX       11
+#define INT_7XX_McBSP2RX_OVF   12
+#define INT_7XX_LCD_LINE       14
+#define INT_7XX_GSM_PROTECT    15
+#define INT_7XX_TIMER3         16
+#define INT_7XX_GPIO_BANK5     17
+#define INT_7XX_GPIO_BANK6     18
+#define INT_7XX_SPGIO_WR       29
+
+/*
+ * IRQ numbers for interrupt handler 2
+ *
+ * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
+ */
+#define IH2_BASE               32
+
+#define INT_KEYBOARD           (1 + IH2_BASE)
+#define INT_uWireTX            (2 + IH2_BASE)
+#define INT_uWireRX            (3 + IH2_BASE)
+#define INT_I2C                        (4 + IH2_BASE)
+#define INT_MPUIO              (5 + IH2_BASE)
+#define INT_USB_HHC_1          (6 + IH2_BASE)
+#define INT_McBSP3TX           (10 + IH2_BASE)
+#define INT_McBSP3RX           (11 + IH2_BASE)
+#define INT_McBSP1TX           (12 + IH2_BASE)
+#define INT_McBSP1RX           (13 + IH2_BASE)
+#define INT_UART1              (14 + IH2_BASE)
+#define INT_UART2              (15 + IH2_BASE)
+#define INT_BT_MCSI1TX         (16 + IH2_BASE)
+#define INT_BT_MCSI1RX         (17 + IH2_BASE)
+#define INT_SOSSI_MATCH                (19 + IH2_BASE)
+#define INT_USB_W2FC           (20 + IH2_BASE)
+#define INT_1WIRE              (21 + IH2_BASE)
+#define INT_OS_TIMER           (22 + IH2_BASE)
+#define INT_MMC                        (23 + IH2_BASE)
+#define INT_GAUGE_32K          (24 + IH2_BASE)
+#define INT_RTC_TIMER          (25 + IH2_BASE)
+#define INT_RTC_ALARM          (26 + IH2_BASE)
+#define INT_MEM_STICK          (27 + IH2_BASE)
+
+/*
+ * OMAP-1510 specific IRQ numbers for interrupt handler 2
+ */
+#define INT_1510_DSP_MMU       (28 + IH2_BASE)
+#define INT_1510_COM_SPI_RO    (31 + IH2_BASE)
+
+/*
+ * OMAP-1610 specific IRQ numbers for interrupt handler 2
+ */
+#define INT_1610_FAC           (0 + IH2_BASE)
+#define INT_1610_USB_HHC_2     (7 + IH2_BASE)
+#define INT_1610_USB_OTG       (8 + IH2_BASE)
+#define INT_1610_SoSSI         (9 + IH2_BASE)
+#define INT_1610_SoSSI_MATCH   (19 + IH2_BASE)
+#define INT_1610_DSP_MMU       (28 + IH2_BASE)
+#define INT_1610_McBSP2RX_OF   (31 + IH2_BASE)
+#define INT_1610_STI           (32 + IH2_BASE)
+#define INT_1610_STI_WAKEUP    (33 + IH2_BASE)
+#define INT_1610_GPTIMER3      (34 + IH2_BASE)
+#define INT_1610_GPTIMER4      (35 + IH2_BASE)
+#define INT_1610_GPTIMER5      (36 + IH2_BASE)
+#define INT_1610_GPTIMER6      (37 + IH2_BASE)
+#define INT_1610_GPTIMER7      (38 + IH2_BASE)
+#define INT_1610_GPTIMER8      (39 + IH2_BASE)
+#define INT_1610_GPIO_BANK2    (40 + IH2_BASE)
+#define INT_1610_GPIO_BANK3    (41 + IH2_BASE)
+#define INT_1610_MMC2          (42 + IH2_BASE)
+#define INT_1610_CF            (43 + IH2_BASE)
+#define INT_1610_WAKE_UP_REQ   (46 + IH2_BASE)
+#define INT_1610_GPIO_BANK4    (48 + IH2_BASE)
+#define INT_1610_SPI           (49 + IH2_BASE)
+#define INT_1610_DMA_CH6       (53 + IH2_BASE)
+#define INT_1610_DMA_CH7       (54 + IH2_BASE)
+#define INT_1610_DMA_CH8       (55 + IH2_BASE)
+#define INT_1610_DMA_CH9       (56 + IH2_BASE)
+#define INT_1610_DMA_CH10      (57 + IH2_BASE)
+#define INT_1610_DMA_CH11      (58 + IH2_BASE)
+#define INT_1610_DMA_CH12      (59 + IH2_BASE)
+#define INT_1610_DMA_CH13      (60 + IH2_BASE)
+#define INT_1610_DMA_CH14      (61 + IH2_BASE)
+#define INT_1610_DMA_CH15      (62 + IH2_BASE)
+#define INT_1610_NAND          (63 + IH2_BASE)
+#define INT_1610_SHA1MD5       (91 + IH2_BASE)
+
+/*
+ * OMAP-7xx specific IRQ numbers for interrupt handler 2
+ */
+#define INT_7XX_HW_ERRORS      (0 + IH2_BASE)
+#define INT_7XX_NFIQ_PWR_FAIL  (1 + IH2_BASE)
+#define INT_7XX_CFCD           (2 + IH2_BASE)
+#define INT_7XX_CFIREQ         (3 + IH2_BASE)
+#define INT_7XX_I2C            (4 + IH2_BASE)
+#define INT_7XX_PCC            (5 + IH2_BASE)
+#define INT_7XX_MPU_EXT_NIRQ   (6 + IH2_BASE)
+#define INT_7XX_SPI_100K_1     (7 + IH2_BASE)
+#define INT_7XX_SYREN_SPI      (8 + IH2_BASE)
+#define INT_7XX_VLYNQ          (9 + IH2_BASE)
+#define INT_7XX_GPIO_BANK4     (10 + IH2_BASE)
+#define INT_7XX_McBSP1TX       (11 + IH2_BASE)
+#define INT_7XX_McBSP1RX       (12 + IH2_BASE)
+#define INT_7XX_McBSP1RX_OF    (13 + IH2_BASE)
+#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
+#define INT_7XX_UART_MODEM_1   (15 + IH2_BASE)
+#define INT_7XX_MCSI           (16 + IH2_BASE)
+#define INT_7XX_uWireTX                (17 + IH2_BASE)
+#define INT_7XX_uWireRX                (18 + IH2_BASE)
+#define INT_7XX_SMC_CD         (19 + IH2_BASE)
+#define INT_7XX_SMC_IREQ       (20 + IH2_BASE)
+#define INT_7XX_HDQ_1WIRE      (21 + IH2_BASE)
+#define INT_7XX_TIMER32K       (22 + IH2_BASE)
+#define INT_7XX_MMC_SDIO       (23 + IH2_BASE)
+#define INT_7XX_UPLD           (24 + IH2_BASE)
+#define INT_7XX_USB_HHC_1      (27 + IH2_BASE)
+#define INT_7XX_USB_HHC_2      (28 + IH2_BASE)
+#define INT_7XX_USB_GENI       (29 + IH2_BASE)
+#define INT_7XX_USB_OTG                (30 + IH2_BASE)
+#define INT_7XX_CAMERA_IF      (31 + IH2_BASE)
+#define INT_7XX_RNG            (32 + IH2_BASE)
+#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
+#define INT_7XX_DBB_RF_EN      (34 + IH2_BASE)
+#define INT_7XX_MPUIO_KEYPAD   (35 + IH2_BASE)
+#define INT_7XX_SHA1_MD5       (36 + IH2_BASE)
+#define INT_7XX_SPI_100K_2     (37 + IH2_BASE)
+#define INT_7XX_RNG_IDLE       (38 + IH2_BASE)
+#define INT_7XX_MPUIO          (39 + IH2_BASE)
+#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF       (40 + IH2_BASE)
+#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
+#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE)
+#define INT_7XX_LLPC_VSYNC     (43 + IH2_BASE)
+#define INT_7XX_WAKE_UP_REQ    (46 + IH2_BASE)
+#define INT_7XX_DMA_CH6                (53 + IH2_BASE)
+#define INT_7XX_DMA_CH7                (54 + IH2_BASE)
+#define INT_7XX_DMA_CH8                (55 + IH2_BASE)
+#define INT_7XX_DMA_CH9                (56 + IH2_BASE)
+#define INT_7XX_DMA_CH10       (57 + IH2_BASE)
+#define INT_7XX_DMA_CH11       (58 + IH2_BASE)
+#define INT_7XX_DMA_CH12       (59 + IH2_BASE)
+#define INT_7XX_DMA_CH13       (60 + IH2_BASE)
+#define INT_7XX_DMA_CH14       (61 + IH2_BASE)
+#define INT_7XX_DMA_CH15       (62 + IH2_BASE)
+#define INT_7XX_NAND           (63 + IH2_BASE)
+
+/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
+ * 16 MPUIO lines */
+#define OMAP_MAX_GPIO_LINES    192
+#define IH_GPIO_BASE           (128 + IH2_BASE)
+#define IH_MPUIO_BASE          (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
+#define OMAP_IRQ_END           (IH_MPUIO_BASE + 16)
+
+/* External FPGA handles interrupts on Innovator boards */
+#define        OMAP_FPGA_IRQ_BASE      (OMAP_IRQ_END)
+#ifdef CONFIG_MACH_OMAP_INNOVATOR
+#define OMAP_FPGA_NR_IRQS      24
+#else
+#define OMAP_FPGA_NR_IRQS      0
+#endif
+#define OMAP_FPGA_IRQ_END      (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
+
+#define NR_IRQS                        OMAP_FPGA_IRQ_END
+
+#define OMAP_IRQ_BIT(irq)      (1 << ((irq) % 32))
+
+#include <mach/hardware.h>
+
+#ifdef CONFIG_FIQ
+#define FIQ_START              1024
+#endif
+
+#endif
similarity index 97%
rename from arch/arm/plat-omap/include/plat/omap1510.h
rename to arch/arm/mach-omap1/include/mach/omap1510.h
index d240046..8fe05d6 100644 (file)
@@ -1,5 +1,4 @@
-/* arch/arm/plat-omap/include/mach/omap1510.h
- *
+/*
  * Hardware definitions for TI OMAP1510 processor.
  *
  * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
similarity index 99%
rename from arch/arm/plat-omap/include/plat/omap16xx.h
rename to arch/arm/mach-omap1/include/mach/omap16xx.h
index e69e1d8..cd1c724 100644 (file)
@@ -1,5 +1,4 @@
-/* arch/arm/plat-omap/include/mach/omap16xx.h
- *
+/*
  * Hardware definitions for TI OMAP1610/5912/1710 processors.
  *
  * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
similarity index 98%
rename from arch/arm/plat-omap/include/plat/omap7xx.h
rename to arch/arm/mach-omap1/include/mach/omap7xx.h
index 48e4757..63da994 100644 (file)
@@ -1,5 +1,4 @@
-/* arch/arm/plat-omap/include/mach/omap7xx.h
- *
+/*
  * Hardware definitions for TI OMAP7XX processor.
  *
  * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
diff --git a/arch/arm/mach-omap1/include/mach/smp.h b/arch/arm/mach-omap1/include/mach/smp.h
deleted file mode 100644 (file)
index 80a371c..0000000
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-omap1/include/mach/smp.h
- */
-
-#include <plat/smp.h>
index 6c95a59..6a5baab 100644 (file)
@@ -16,7 +16,7 @@
 #include <asm/tlb.h>
 #include <asm/mach/map.h>
 
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/tc.h>
 #include <plat/dma.h>
 
index 5769c71..ed42628 100644 (file)
@@ -113,8 +113,7 @@ EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
 {
        if (cpu_is_omap15xx()) {
-               printk(KERN_ERR "DMA virtual resolution is not supported "
-                               "in 1510 mode\n");
+               pr_err("DMA virtual resolution is not supported in 1510 mode\n");
                BUG();
        }
        lcd_dma.vxres = vxres;
@@ -437,8 +436,7 @@ static int __init omap_init_lcd_dma(void)
        r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
                        "LCD DMA", NULL);
        if (r != 0)
-               printk(KERN_ERR "unable to request IRQ for LCD DMA "
-                              "(error %d)\n", r);
+               pr_err("unable to request IRQ for LCD DMA (error %d)\n", r);
 
        return r;
 }
index f6b14a1..6f958ae 100644 (file)
@@ -14,6 +14,7 @@
 #include <linux/kernel_stat.h>
 #include <linux/sched.h>
 #include <linux/io.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
@@ -68,11 +69,13 @@ void h2p2_dbg_leds_event(led_event_t evt)
                        gpio_set_value(GPIO_IDLE, 0);
                }
 
-               __raw_writew(~0, &fpga->leds);
                led_state &= ~LED_STATE_ENABLED;
-               if (evt == led_halted) {
-                       iounmap(fpga);
-                       fpga = NULL;
+               if (fpga) {
+                       __raw_writew(~0, &fpga->leds);
+                       if (evt == led_halted) {
+                               iounmap(fpga);
+                               fpga = NULL;
+                       }
                }
 
                goto done;
@@ -158,7 +161,7 @@ void h2p2_dbg_leds_event(led_event_t evt)
        /*
         *  Actually burn the LEDs
         */
-       if (led_state & LED_STATE_ENABLED)
+       if (led_state & LED_STATE_ENABLED && fpga)
                __raw_writew(~hw_led_state, &fpga->leds);
 
 done:
index ae6dd93..4071479 100644 (file)
@@ -6,11 +6,12 @@
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <asm/leds.h>
 #include <asm/mach-types.h>
 
-#include <plat/mux.h>
+#include <mach/mux.h>
 
 #include "leds.h"
 
index adf0097..bdc2e75 100644 (file)
@@ -20,9 +20,9 @@
 #include <linux/slab.h>
 
 #include <plat/dma.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/cpu.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
 #include <mach/irqs.h>
 
index e9cc52d..667ce50 100644 (file)
@@ -29,7 +29,7 @@
 
 #include <mach/hardware.h>
 
-#include <plat/mux.h>
+#include <mach/mux.h>
 
 #ifdef CONFIG_OMAP_MUX
 
@@ -451,6 +451,56 @@ static int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
 #endif
 }
 
+static struct omap_mux_cfg *mux_cfg;
+
+int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
+{
+       if (!arch_mux_cfg || !arch_mux_cfg->pins || arch_mux_cfg->size == 0
+                       || !arch_mux_cfg->cfg_reg) {
+               printk(KERN_ERR "Invalid pin table\n");
+               return -EINVAL;
+       }
+
+       mux_cfg = arch_mux_cfg;
+
+       return 0;
+}
+
+/*
+ * Sets the Omap MUX and PULL_DWN registers based on the table
+ */
+int __init_or_module omap_cfg_reg(const unsigned long index)
+{
+       struct pin_config *reg;
+
+       if (!cpu_class_is_omap1()) {
+               printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n",
+                               index);
+               WARN_ON(1);
+               return -EINVAL;
+       }
+
+       if (mux_cfg == NULL) {
+               printk(KERN_ERR "Pin mux table not initialized\n");
+               return -ENODEV;
+       }
+
+       if (index >= mux_cfg->size) {
+               printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
+                      index, mux_cfg->size);
+               dump_stack();
+               return -ENODEV;
+       }
+
+       reg = &mux_cfg->pins[index];
+
+       if (!mux_cfg->cfg_reg)
+               return -ENODEV;
+
+       return mux_cfg->cfg_reg(reg);
+}
+EXPORT_SYMBOL(omap_cfg_reg);
+
 int __init omap1_mux_init(void)
 {
        if (cpu_is_omap7xx()) {
@@ -468,4 +518,8 @@ int __init omap1_mux_init(void)
        return omap_mux_register(&arch_mux_cfg);
 }
 
-#endif
+#else
+#define omap_mux_init() do {} while(0)
+#define omap_cfg_reg(x)        do {} while(0)
+#endif /* CONFIG_OMAP_MUX */
+
index b2560d3..47ec161 100644 (file)
@@ -53,7 +53,7 @@
 #include <plat/clock.h>
 #include <plat/sram.h>
 #include <plat/tc.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/dma.h>
 #include <plat/dmtimer.h>
 
index 6809c9e..b9d6834 100644 (file)
@@ -22,8 +22,7 @@
 
 #include <asm/mach-types.h>
 
-#include <plat/board.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/fpga.h>
 
 #include "pm.h"
index 65f8817..84267ed 100644 (file)
@@ -26,7 +26,7 @@
 
 #include <asm/irq.h>
 
-#include <plat/mux.h>
+#include <mach/mux.h>
 
 #include <mach/usb.h>
 
index 34c2c7f..7706fdf 100644 (file)
@@ -4,36 +4,30 @@
 
 # Common support
 obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
-        common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o
+        common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o
 
-omap-2-3-common                                = irq.o
-hwmod-common                           = omap_hwmod.o \
-                                         omap_hwmod_common_data.o
-clock-common                           = clock.o clock_common_data.o \
-                                         clkt_dpll.o clkt_clksel.o
-secure-common                          = omap-smc.o omap-secure.o
+# INTCPS IP block support - XXX should be moved to drivers/
+obj-$(CONFIG_ARCH_OMAP2)               += irq.o
+obj-$(CONFIG_ARCH_OMAP3)               += irq.o
+obj-$(CONFIG_SOC_AM33XX)               += irq.o
 
-obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
-obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
-obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
-obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
-obj-$(CONFIG_SOC_OMAP5)         += prm44xx.o $(hwmod-common) $(secure-common)
+# Secure monitor API support
+obj-$(CONFIG_ARCH_OMAP3)               += omap-smc.o omap-secure.o
+obj-$(CONFIG_ARCH_OMAP4)               += omap-smc.o omap-secure.o
+obj-$(CONFIG_SOC_OMAP5)                        += omap-smc.o omap-secure.o
 
 ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
 obj-y += mcbsp.o
 endif
 
-obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
-obj-$(CONFIG_SOC_HAS_OMAP2_SDRC)       += sdrc.o
+obj-$(CONFIG_TWL4030_CORE)             += omap_twl.o
 
 # SMP support ONLY available for OMAP4
 
 obj-$(CONFIG_SMP)                      += omap-smp.o omap-headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)              += omap-hotplug.o
-omap-4-5-common                                =  omap4-common.o omap-wakeupgen.o \
-                                          sleep44xx.o
-obj-$(CONFIG_ARCH_OMAP4)               += $(omap-4-5-common)
-obj-$(CONFIG_SOC_OMAP5)                        += $(omap-4-5-common)
+obj-$(CONFIG_ARCH_OMAP4)               += omap4-common.o omap-wakeupgen.o
+obj-$(CONFIG_SOC_OMAP5)                        += omap4-common.o omap-wakeupgen.o
 
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_omap-headsmp.o                  :=-Wa,-march=armv7-a$(plus_sec)
@@ -58,6 +52,7 @@ obj-$(CONFIG_ARCH_OMAP4)              += mux44xx.o
 # SMS/SDRC
 obj-$(CONFIG_ARCH_OMAP2)               += sdrc2xxx.o
 # obj-$(CONFIG_ARCH_OMAP3)             += sdrc3xxx.o
+obj-$(CONFIG_SOC_HAS_OMAP2_SDRC)       += sdrc.o
 
 # OPP table initialization
 ifeq ($(CONFIG_PM_OPP),y)
@@ -68,15 +63,15 @@ endif
 
 # Power Management
 ifeq ($(CONFIG_PM),y)
-obj-$(CONFIG_ARCH_OMAP2)               += pm24xx.o
-obj-$(CONFIG_ARCH_OMAP2)               += sleep24xx.o
+obj-$(CONFIG_ARCH_OMAP2)               += pm24xx.o sleep24xx.o
 obj-$(CONFIG_ARCH_OMAP3)               += pm34xx.o sleep34xx.o
 obj-$(CONFIG_ARCH_OMAP4)               += pm44xx.o omap-mpuss-lowpower.o
-obj-$(CONFIG_SOC_OMAP5)                        += omap-mpuss-lowpower.o
+obj-$(CONFIG_ARCH_OMAP4)               += sleep44xx.o
+obj-$(CONFIG_SOC_OMAP5)                        += omap-mpuss-lowpower.o sleep44xx.o
 obj-$(CONFIG_PM_DEBUG)                 += pm-debug.o
 
 obj-$(CONFIG_POWER_AVS_OMAP)           += sr_device.o
-obj-$(CONFIG_POWER_AVS_OMAP_CLASS3)    += smartreflex-class3.o
+obj-$(CONFIG_POWER_AVS_OMAP_CLASS3)    += smartreflex-class3.o
 
 AFLAGS_sleep24xx.o                     :=-Wa,-march=armv6
 AFLAGS_sleep34xx.o                     :=-Wa,-march=armv7-a$(plus_sec)
@@ -88,92 +83,76 @@ endif
 endif
 
 ifeq ($(CONFIG_CPU_IDLE),y)
-obj-$(CONFIG_ARCH_OMAP3)                += cpuidle34xx.o
-obj-$(CONFIG_ARCH_OMAP4)                += cpuidle44xx.o
+obj-$(CONFIG_ARCH_OMAP3)               += cpuidle34xx.o
+obj-$(CONFIG_ARCH_OMAP4)               += cpuidle44xx.o
 endif
 
 # PRCM
-omap-prcm-4-5-common                   =  prcm.o cminst44xx.o cm44xx.o \
-                                          prcm_mpu44xx.o prminst44xx.o \
-                                          vc44xx_data.o vp44xx_data.o
-obj-y                                  += prm_common.o
-obj-$(CONFIG_ARCH_OMAP2)               += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
-obj-$(CONFIG_ARCH_OMAP3)               += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
+obj-y                                  += prcm.o prm_common.o
+obj-$(CONFIG_ARCH_OMAP2)               += cm2xxx_3xxx.o prm2xxx_3xxx.o
+obj-$(CONFIG_ARCH_OMAP3)               += cm2xxx_3xxx.o prm2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)               += vc3xxx_data.o vp3xxx_data.o
-obj-$(CONFIG_SOC_AM33XX)               += prcm.o prm33xx.o cm33xx.o
-obj-$(CONFIG_ARCH_OMAP4)               += $(omap-prcm-4-5-common) prm44xx.o
+obj-$(CONFIG_SOC_AM33XX)               += prm33xx.o cm33xx.o
+omap-prcm-4-5-common                   =  cminst44xx.o cm44xx.o prm44xx.o \
+                                          prcm_mpu44xx.o prminst44xx.o \
+                                          vc44xx_data.o vp44xx_data.o \
+                                          prm44xx.o
+obj-$(CONFIG_ARCH_OMAP4)               += $(omap-prcm-4-5-common)
 obj-$(CONFIG_SOC_OMAP5)                        += $(omap-prcm-4-5-common)
 
 # OMAP voltage domains
-voltagedomain-common                   := voltage.o vc.o vp.o
-obj-$(CONFIG_ARCH_OMAP2)               += $(voltagedomain-common)
+obj-y                                  += voltage.o vc.o vp.o
 obj-$(CONFIG_ARCH_OMAP2)               += voltagedomains2xxx_data.o
-obj-$(CONFIG_ARCH_OMAP3)               += $(voltagedomain-common)
 obj-$(CONFIG_ARCH_OMAP3)               += voltagedomains3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4)               += $(voltagedomain-common)
 obj-$(CONFIG_ARCH_OMAP4)               += voltagedomains44xx_data.o
-obj-$(CONFIG_SOC_AM33XX)               += $(voltagedomain-common)
-obj-$(CONFIG_SOC_AM33XX)                += voltagedomains33xx_data.o
-obj-$(CONFIG_SOC_OMAP5)                        += $(voltagedomain-common)
+obj-$(CONFIG_SOC_AM33XX)               += voltagedomains33xx_data.o
 
 # OMAP powerdomain framework
-powerdomain-common                     += powerdomain.o powerdomain-common.o
-obj-$(CONFIG_ARCH_OMAP2)               += $(powerdomain-common)
+obj-y                                  += powerdomain.o powerdomain-common.o
 obj-$(CONFIG_ARCH_OMAP2)               += powerdomains2xxx_data.o
 obj-$(CONFIG_ARCH_OMAP2)               += powerdomain2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP2)               += powerdomains2xxx_3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP3)               += $(powerdomain-common)
 obj-$(CONFIG_ARCH_OMAP3)               += powerdomain2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)               += powerdomains3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP3)               += powerdomains2xxx_3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4)               += $(powerdomain-common)
 obj-$(CONFIG_ARCH_OMAP4)               += powerdomain44xx.o
 obj-$(CONFIG_ARCH_OMAP4)               += powerdomains44xx_data.o
-obj-$(CONFIG_SOC_AM33XX)               += $(powerdomain-common)
 obj-$(CONFIG_SOC_AM33XX)               += powerdomain33xx.o
 obj-$(CONFIG_SOC_AM33XX)               += powerdomains33xx_data.o
-obj-$(CONFIG_SOC_OMAP5)                        += $(powerdomain-common)
 obj-$(CONFIG_SOC_OMAP5)                        += powerdomain44xx.o
 
 # PRCM clockdomain control
-clockdomain-common                     += clockdomain.o
-obj-$(CONFIG_ARCH_OMAP2)               += $(clockdomain-common)
+obj-y                                  += clockdomain.o
 obj-$(CONFIG_ARCH_OMAP2)               += clockdomain2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP2)               += clockdomains2xxx_3xxx_data.o
 obj-$(CONFIG_SOC_OMAP2420)             += clockdomains2420_data.o
 obj-$(CONFIG_SOC_OMAP2430)             += clockdomains2430_data.o
-obj-$(CONFIG_ARCH_OMAP3)               += $(clockdomain-common)
 obj-$(CONFIG_ARCH_OMAP3)               += clockdomain2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)               += clockdomains2xxx_3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP3)               += clockdomains3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4)               += $(clockdomain-common)
 obj-$(CONFIG_ARCH_OMAP4)               += clockdomain44xx.o
 obj-$(CONFIG_ARCH_OMAP4)               += clockdomains44xx_data.o
-obj-$(CONFIG_SOC_AM33XX)               += $(clockdomain-common)
 obj-$(CONFIG_SOC_AM33XX)               += clockdomain33xx.o
 obj-$(CONFIG_SOC_AM33XX)               += clockdomains33xx_data.o
-obj-$(CONFIG_SOC_OMAP5)                        += $(clockdomain-common)
 obj-$(CONFIG_SOC_OMAP5)                        += clockdomain44xx.o
 
 # Clock framework
-obj-$(CONFIG_ARCH_OMAP2)               += $(clock-common) clock2xxx.o
-obj-$(CONFIG_ARCH_OMAP2)               += clkt2xxx_sys.o
-obj-$(CONFIG_ARCH_OMAP2)               += clkt2xxx_dpllcore.o
+obj-y                                  += clock.o clock_common_data.o \
+                                          clkt_dpll.o clkt_clksel.o
+obj-$(CONFIG_ARCH_OMAP2)               += clock2xxx.o
+obj-$(CONFIG_ARCH_OMAP2)               += clkt2xxx_dpllcore.o clkt2xxx_sys.o
 obj-$(CONFIG_ARCH_OMAP2)               += clkt2xxx_virt_prcm_set.o
 obj-$(CONFIG_ARCH_OMAP2)               += clkt2xxx_apll.o clkt2xxx_osc.o
 obj-$(CONFIG_ARCH_OMAP2)               += clkt2xxx_dpll.o clkt_iclk.o
 obj-$(CONFIG_SOC_OMAP2420)             += clock2420_data.o
 obj-$(CONFIG_SOC_OMAP2430)             += clock2430.o clock2430_data.o
-obj-$(CONFIG_ARCH_OMAP3)               += $(clock-common) clock3xxx.o
+obj-$(CONFIG_ARCH_OMAP3)               += clock3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)               += clock34xx.o clkt34xx_dpll3m2.o
-obj-$(CONFIG_ARCH_OMAP3)               += clock3517.o clock36xx.o
+obj-$(CONFIG_ARCH_OMAP3)               += clock3517.o clock36xx.o clkt_iclk.o
 obj-$(CONFIG_ARCH_OMAP3)               += dpll3xxx.o clock3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP3)               += clkt_iclk.o
-obj-$(CONFIG_ARCH_OMAP4)               += $(clock-common) clock44xx_data.o
+obj-$(CONFIG_ARCH_OMAP4)               += clock44xx_data.o
 obj-$(CONFIG_ARCH_OMAP4)               += dpll3xxx.o dpll44xx.o
-obj-$(CONFIG_SOC_AM33XX)               += $(clock-common) dpll3xxx.o
-obj-$(CONFIG_SOC_AM33XX)               += clock33xx_data.o
-obj-$(CONFIG_SOC_OMAP5)                        += $(clock-common)
+obj-$(CONFIG_SOC_AM33XX)               += dpll3xxx.o clock33xx_data.o
 obj-$(CONFIG_SOC_OMAP5)                        += dpll3xxx.o dpll44xx.o
 
 # OMAP2 clock rate set data (old "OPP" data)
@@ -181,6 +160,7 @@ obj-$(CONFIG_SOC_OMAP2420)          += opp2420_data.o
 obj-$(CONFIG_SOC_OMAP2430)             += opp2430_data.o
 
 # hwmod data
+obj-y                                  += omap_hwmod_common_data.o
 obj-$(CONFIG_SOC_OMAP2420)             += omap_hwmod_2xxx_ipblock_data.o
 obj-$(CONFIG_SOC_OMAP2420)             += omap_hwmod_2xxx_3xxx_ipblock_data.o
 obj-$(CONFIG_SOC_OMAP2420)             += omap_hwmod_2xxx_interconnect_data.o
@@ -229,10 +209,10 @@ obj-$(CONFIG_MACH_OMAP_H4)                += board-h4.o
 obj-$(CONFIG_MACH_OMAP_2430SDP)                += board-2430sdp.o
 obj-$(CONFIG_MACH_OMAP_APOLLON)                += board-apollon.o
 obj-$(CONFIG_MACH_OMAP3_BEAGLE)                += board-omap3beagle.o
-obj-$(CONFIG_MACH_DEVKIT8000)          += board-devkit8000.o
+obj-$(CONFIG_MACH_DEVKIT8000)          += board-devkit8000.o
 obj-$(CONFIG_MACH_OMAP_LDP)            += board-ldp.o
-obj-$(CONFIG_MACH_OMAP3530_LV_SOM)      += board-omap3logic.o
-obj-$(CONFIG_MACH_OMAP3_TORPEDO)        += board-omap3logic.o
+obj-$(CONFIG_MACH_OMAP3530_LV_SOM)     += board-omap3logic.o
+obj-$(CONFIG_MACH_OMAP3_TORPEDO)       += board-omap3logic.o
 obj-$(CONFIG_MACH_ENCORE)              += board-omap3encore.o
 obj-$(CONFIG_MACH_OVERO)               += board-overo.o
 obj-$(CONFIG_MACH_OMAP3EVM)            += board-omap3evm.o
index 2c90ac6..d0c54c5 100644 (file)
@@ -19,7 +19,7 @@
 #include <linux/davinci_emac.h>
 #include <asm/system.h>
 #include <plat/omap_device.h>
-#include <mach/am35xx.h>
+#include "am35xx.h"
 #include "control.h"
 #include "am35xx-emac.h"
 
index 9511584..95b384d 100644 (file)
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
 #include <plat/usb.h>
-#include <plat/gpmc-smc91x.h>
+#include "gpmc-smc91x.h"
 
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
@@ -212,9 +211,6 @@ static struct regulator_init_data sdp2430_vmmc1 = {
 };
 
 static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
-       .gpio_base      = OMAP_MAX_GPIO_LINES,
-       .irq_base       = TWL4030_GPIO_IRQ_BASE,
-       .irq_end        = TWL4030_GPIO_IRQ_END,
 };
 
 static struct twl4030_platform_data sdp2430_twldata = {
@@ -235,7 +231,7 @@ static int __init omap2430_i2c_init(void)
        sdp2430_i2c1_boardinfo[0].irq = gpio_to_irq(78);
        omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo,
                        ARRAY_SIZE(sdp2430_i2c1_boardinfo));
-       omap_pmic_init(2, 100, "twl4030", INT_24XX_SYS_NIRQ,
+       omap_pmic_init(2, 100, "twl4030", 7 + OMAP_INTC_START,
                        &sdp2430_twldata);
        return 0;
 }
index a98c688..96cd369 100644 (file)
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/mmc/host.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/mcspi.h>
-#include <plat/board.h>
 #include <plat/usb.h>
 #include "common.h"
 #include <plat/dma.h>
@@ -39,7 +37,7 @@
 #include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
 
-#include <plat/gpmc-smc91x.h>
+#include "gpmc-smc91x.h"
 
 #include "board-flash.h"
 #include "mux.h"
@@ -191,9 +189,6 @@ static struct omap_dss_board_info sdp3430_dss_data = {
        .default_device = &sdp3430_lcd_device,
 };
 
-static struct omap_board_config_kernel sdp3430_config[] __initdata = {
-};
-
 static struct omap2_hsmmc_info mmc[] = {
        {
                .mmc            = 1,
@@ -233,9 +228,6 @@ static int sdp3430_twl_gpio_setup(struct device *dev,
 }
 
 static struct twl4030_gpio_platform_data sdp3430_gpio_data = {
-       .gpio_base      = OMAP_MAX_GPIO_LINES,
-       .irq_base       = TWL4030_GPIO_IRQ_BASE,
-       .irq_end        = TWL4030_GPIO_IRQ_END,
        .pulldowns      = BIT(2) | BIT(6) | BIT(8) | BIT(13)
                                | BIT(16) | BIT(17),
        .setup          = sdp3430_twl_gpio_setup,
@@ -576,8 +568,6 @@ static void __init omap_3430sdp_init(void)
        int gpio_pendown;
 
        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
-       omap_board_config = sdp3430_config;
-       omap_board_config_size = ARRAY_SIZE(sdp3430_config);
        omap_hsmmc_init(mmc);
        omap3430_i2c_init();
        omap_display_init(&sdp3430_dss_data);
index 2dc9ba5..fc224ad 100644 (file)
@@ -17,8 +17,7 @@
 #include <asm/mach/arch.h>
 
 #include "common.h"
-#include <plat/board.h>
-#include <plat/gpmc-smc91x.h>
+#include "gpmc-smc91x.h"
 #include <plat/usb.h>
 
 #include <mach/board-zoom.h>
@@ -67,9 +66,6 @@ static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
        .reset_gpio_port[2]  = -EINVAL
 };
 
-static struct omap_board_config_kernel sdp_config[] __initdata = {
-};
-
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
        { .reg_offset = OMAP_MUX_TERMINATOR },
@@ -197,8 +193,6 @@ static struct flash_partitions sdp_flash_partitions[] = {
 static void __init omap_sdp_init(void)
 {
        omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
-       omap_board_config = sdp_config;
-       omap_board_config_size = ARRAY_SIZE(sdp_config);
        zoom_peripherals_init();
        omap_sdrc_init(h8mbx00u0mer0em_sdrc_params,
                                  h8mbx00u0mer0em_sdrc_params);
index ad8a7d9..749ce96 100644 (file)
 #include <linux/leds_pwm.h>
 #include <linux/platform_data/omap4-keypad.h>
 
-#include <mach/hardware.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/usb.h>
 #include <plat/mmc.h>
-#include <plat/omap4-keypad.h>
+#include "omap4-keypad.h"
 #include <video/omapdss.h>
 #include <video/omap-panel-nokia-dsi.h>
 #include <video/omap-panel-picodlp.h>
 #include <linux/wl12xx.h>
 #include <linux/platform_data/omap-abe-twl6040.h>
 
+#include "soc.h"
 #include "mux.h"
 #include "hsmmc.h"
 #include "control.h"
@@ -544,7 +543,14 @@ static struct twl6040_platform_data twl6040_data = {
        .codec          = &twl6040_codec,
        .vibra          = &twl6040_vibra,
        .audpwron_gpio  = 127,
-       .irq_base       = TWL6040_CODEC_IRQ_BASE,
+};
+
+static struct i2c_board_info __initdata sdp4430_i2c_1_boardinfo[] = {
+       {
+               I2C_BOARD_INFO("twl6040", 0x4b),
+               .irq = 119 + OMAP44XX_IRQ_GIC_START,
+               .platform_data = &twl6040_data,
+       },
 };
 
 static struct twl4030_platform_data sdp4430_twldata = {
@@ -580,8 +586,8 @@ static int __init omap4_i2c_init(void)
                        TWL_COMMON_REGULATOR_CLK32KG |
                        TWL_COMMON_REGULATOR_V1V8 |
                        TWL_COMMON_REGULATOR_V2V1);
-       omap4_pmic_init("twl6030", &sdp4430_twldata,
-                       &twl6040_data, OMAP44XX_IRQ_SYS_2N);
+       omap4_pmic_init("twl6030", &sdp4430_twldata, sdp4430_i2c_1_boardinfo,
+                       ARRAY_SIZE(sdp4430_i2c_1_boardinfo));
        omap_register_i2c_bus(2, 400, NULL, 0);
        omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo,
                                ARRAY_SIZE(sdp4430_i2c_3_boardinfo));
index 92432c2..318fead 100644 (file)
 #include <linux/init.h>
 #include <linux/gpio.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/usb.h>
 
 #define GPIO_USB_POWER         35
 #define GPIO_USB_NRESET                38
 
-
-/* Board initialization */
-static struct omap_board_config_kernel am3517_crane_config[] __initdata = {
-};
-
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
        { .reg_offset = OMAP_MUX_TERMINATOR },
@@ -67,9 +60,6 @@ static void __init am3517_crane_init(void)
        omap_serial_init();
        omap_sdrc_init(NULL, NULL);
 
-       omap_board_config = am3517_crane_config;
-       omap_board_config_size = ARRAY_SIZE(am3517_crane_config);
-
        /* Configure GPIO for EHCI port */
        if (omap_mux_init_gpio(GPIO_USB_NRESET, OMAP_PIN_OUTPUT)) {
                pr_err("Can not configure mux for GPIO_USB_NRESET %d\n",
index 18f6010..0d99c91 100644 (file)
 #include <linux/can/platform/ti_hecc.h>
 #include <linux/davinci_emac.h>
 #include <linux/mmc/host.h>
+#include <linux/platform_data/gpio-omap.h>
 
-#include <mach/hardware.h>
-#include <mach/am35xx.h>
+#include "am35xx.h"
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/usb.h>
 #include <video/omapdss.h>
@@ -296,8 +295,7 @@ static struct resource am3517_hecc_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        {
-               .start  = INT_35XX_HECC0_IRQ,
-               .end    = INT_35XX_HECC0_IRQ,
+               .start  = 24 + OMAP_INTC_START,
                .flags  = IORESOURCE_IRQ,
        },
 };
@@ -324,9 +322,6 @@ static void am3517_evm_hecc_init(struct ti_hecc_platform_data *pdata)
        platform_device_register(&am3517_hecc_device);
 }
 
-static struct omap_board_config_kernel am3517_evm_config[] __initdata = {
-};
-
 static struct omap2_hsmmc_info mmc[] = {
        {
                .mmc            = 1,
@@ -346,8 +341,6 @@ static struct omap2_hsmmc_info mmc[] = {
 
 static void __init am3517_evm_init(void)
 {
-       omap_board_config = am3517_evm_config;
-       omap_board_config_size = ARRAY_SIZE(am3517_evm_config);
        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
 
        am3517_evm_i2c_init();
index e5fa46b..3e2d76f 100644 (file)
 #include <linux/smc91x.h>
 #include <linux/gpio.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 
 #include <plat/led.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
 
index 97d7190..8ffd612 100644 (file)
@@ -23,6 +23,7 @@
 #include <linux/input/matrix_keypad.h>
 #include <linux/delay.h>
 #include <linux/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <linux/i2c/at24.h>
 #include <linux/i2c/twl.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
 #include "common.h"
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/gpmc.h>
 #include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
 #include <mach/hardware.h>
 
@@ -64,7 +64,7 @@
 
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 #include <linux/smsc911x.h>
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 
 static struct omap_smsc911x_platform_data cm_t35_smsc911x_cfg = {
        .id             = 0,
@@ -470,9 +470,6 @@ static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
 }
 
 static struct twl4030_gpio_platform_data cm_t35_gpio_data = {
-       .gpio_base      = OMAP_MAX_GPIO_LINES,
-       .irq_base       = TWL4030_GPIO_IRQ_BASE,
-       .irq_end        = TWL4030_GPIO_IRQ_END,
        .setup          = cm_t35_twl_gpio_setup,
 };
 
@@ -714,13 +711,8 @@ static inline void cm_t35_init_mux(void) {}
 static inline void cm_t3730_init_mux(void) {}
 #endif
 
-static struct omap_board_config_kernel cm_t35_config[] __initdata = {
-};
-
 static void __init cm_t3x_common_init(void)
 {
-       omap_board_config = cm_t35_config;
-       omap_board_config_size = ARRAY_SIZE(cm_t35_config);
        omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
        omap_serial_init();
        omap_sdrc_init(mt46h32m32lf6_sdrc_params,
index a33ad46..59c0a45 100644 (file)
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/usb.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/gpmc.h>
 
-#include <mach/am35xx.h>
+#include "am35xx.h"
 
 #include "mux.h"
 #include "control.h"
@@ -90,8 +89,7 @@ static struct resource cm_t3517_hecc_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        {
-               .start  = INT_35XX_HECC0_IRQ,
-               .end    = INT_35XX_HECC0_IRQ,
+               .start  = 24 + OMAP_INTC_START,
                .flags  = IORESOURCE_IRQ,
        },
 };
@@ -249,9 +247,6 @@ static void __init cm_t3517_init_nand(void)
 static inline void cm_t3517_init_nand(void) {}
 #endif
 
-static struct omap_board_config_kernel cm_t3517_config[] __initdata = {
-};
-
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
        /* GPIO186 - Green LED */
@@ -285,8 +280,6 @@ static void __init cm_t3517_init(void)
        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
        omap_serial_init();
        omap_sdrc_init(NULL, NULL);
-       omap_board_config = cm_t3517_config;
-       omap_board_config_size = ARRAY_SIZE(cm_t3517_config);
        cm_t3517_init_leds();
        cm_t3517_init_nand();
        cm_t3517_init_rtc();
index 6567c1c..7bb8056 100644 (file)
 
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
-
-#include <mach/hardware.h>
-#include <mach/id.h>
+#include "id.h"
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
 
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/spi/spi.h>
 #include <linux/dm9000.h>
 #include <linux/interrupt.h>
 
 #include "sdram-micron-mt46h32m32lf-6.h"
-
 #include "mux.h"
 #include "hsmmc.h"
 #include "common-board-devices.h"
@@ -236,9 +232,6 @@ static int devkit8000_twl_gpio_setup(struct device *dev,
 }
 
 static struct twl4030_gpio_platform_data devkit8000_gpio_data = {
-       .gpio_base      = OMAP_MAX_GPIO_LINES,
-       .irq_base       = TWL4030_GPIO_IRQ_BASE,
-       .irq_end        = TWL4030_GPIO_IRQ_END,
        .use_leds       = true,
        .pulldowns      = BIT(1) | BIT(2) | BIT(6) | BIT(8) | BIT(13)
                                | BIT(15) | BIT(16) | BIT(17),
index 53c39d2..0cabe61 100644 (file)
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
 #include <linux/io.h>
-#include <plat/irqs.h>
 
+#include <plat/cpu.h>
 #include <plat/gpmc.h>
-#include <plat/nand.h>
-#include <plat/onenand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
+#include <linux/platform_data/mtd-onenand-omap2.h>
 #include <plat/tc.h>
 
+#include "common.h"
 #include "board-flash.h"
 
 #define REG_FPGA_REV                   0x10
@@ -140,7 +141,6 @@ __init board_nand_init(struct mtd_partition *nand_parts,
        board_nand_data.devsize         = nand_type;
 
        board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
-       board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs;
        gpmc_nand_init(&board_nand_data);
 }
 #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
index 6f93a20..2ea7c57 100644 (file)
 #include <linux/of_platform.h>
 #include <linux/irqdomain.h>
 
-#include <mach/hardware.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include "common-board-devices.h"
 
index ace2048..f6c48dd 100644 (file)
 #include <linux/io.h>
 #include <linux/input/matrix_keypad.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
-#include "common.h"
 #include <plat/menelaus.h>
 #include <plat/dma.h>
 #include <plat/gpmc.h>
+#include "debug-devices.h"
 
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 
+#include "common.h"
 #include "mux.h"
 #include "control.h"
 
index 2821448..fb8bd83 100644 (file)
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
 #include <plat/usb.h>
+
 #include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
-#include <plat/onenand.h>
+#include <linux/platform_data/mtd-onenand-omap2.h>
 
 #include "mux.h"
 #include "hsmmc.h"
@@ -192,7 +192,7 @@ static void __init igep_flash_init(void) {}
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 
 #include <linux/smsc911x.h>
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 
 static struct omap_smsc911x_platform_data smsc911x_cfg = {
        .cs             = IGEP2_SMSC911X_CS,
@@ -425,9 +425,6 @@ static int igep_twl_gpio_setup(struct device *dev,
 };
 
 static struct twl4030_gpio_platform_data igep_twl4030_gpio_pdata = {
-       .gpio_base      = OMAP_MAX_GPIO_LINES,
-       .irq_base       = TWL4030_GPIO_IRQ_BASE,
-       .irq_end        = TWL4030_GPIO_IRQ_END,
        .use_leds       = true,
        .setup          = igep_twl_gpio_setup,
 };
index ef9e829..ee8c3cf 100644 (file)
 #include <linux/io.h>
 #include <linux/smsc911x.h>
 #include <linux/mmc/host.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/mcspi.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
 #include <mach/board-zoom.h>
-
-#include <asm/delay.h>
 #include <plat/usb.h>
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
@@ -275,9 +271,6 @@ static int ldp_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio)
 }
 
 static struct twl4030_gpio_platform_data ldp_gpio_data = {
-       .gpio_base      = OMAP_MAX_GPIO_LINES,
-       .irq_base       = TWL4030_GPIO_IRQ_BASE,
-       .irq_end        = TWL4030_GPIO_IRQ_END,
        .setup          = ldp_twl_gpio_setup,
 };
 
index 677357f..d95f727 100644 (file)
 #include <linux/i2c.h>
 #include <linux/spi/spi.h>
 #include <linux/usb/musb.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/platform_data/mtd-onenand-omap2.h>
 #include <sound/tlv320aic3x.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/menelaus.h>
-#include <mach/irqs.h>
-#include <plat/mcspi.h>
-#include <plat/onenand.h>
 #include <plat/mmc.h>
-#include <plat/serial.h>
 
 #include "mux.h"
 
@@ -553,8 +550,8 @@ static int n8x0_auto_sleep_regulators(void)
 
        ret = menelaus_set_regulator_sleep(1, val);
        if (ret < 0) {
-               printk(KERN_ERR "Could not set regulators to sleep on "
-                       "menelaus: %u\n", ret);
+               pr_err("Could not set regulators to sleep on menelaus: %u\n",
+                      ret);
                return ret;
        }
        return 0;
@@ -566,8 +563,7 @@ static int n8x0_auto_voltage_scale(void)
 
        ret = menelaus_set_vcore_hw(1400, 1050);
        if (ret < 0) {
-               printk(KERN_ERR "Could not set VCORE voltage on "
-                       "menelaus: %u\n", ret);
+               pr_err("Could not set VCORE voltage on menelaus: %u\n", ret);
                return ret;
        }
        return 0;
@@ -600,7 +596,7 @@ static struct menelaus_platform_data n8x0_menelaus_platform_data __initdata = {
 static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] __initdata = {
        {
                I2C_BOARD_INFO("menelaus", 0x72),
-               .irq = INT_24XX_SYS_NIRQ,
+               .irq = 7 + OMAP_INTC_START,
                .platform_data = &n8x0_menelaus_platform_data,
        },
 };
index 6202fc7..68ff8d5 100644 (file)
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
 #include <plat/gpmc.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/usb.h>
 #include <plat/omap_device.h>
 
@@ -297,9 +295,6 @@ static int beagle_twl_gpio_setup(struct device *dev,
 }
 
 static struct twl4030_gpio_platform_data beagle_gpio_data = {
-       .gpio_base      = OMAP_MAX_GPIO_LINES,
-       .irq_base       = TWL4030_GPIO_IRQ_BASE,
-       .irq_end        = TWL4030_GPIO_IRQ_END,
        .use_leds       = true,
        .pullups        = BIT(1),
        .pulldowns      = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13)
index 3d2a988..c64e565 100644 (file)
 #include <linux/mmc/host.h>
 #include <linux/export.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
 #include <plat/usb.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include "common.h"
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-tfp410.h>
 
 #define OMAP3EVM_GEN1_ETHR_GPIO_RST    64
 #define OMAP3EVM_GEN2_ETHR_GPIO_RST    7
 
+/*
+ * OMAP35x EVM revision
+ * Run time detection of EVM revision is done by reading Ethernet
+ * PHY ID -
+ *     GEN_1   = 0x01150000
+ *     GEN_2   = 0x92200000
+ */
+enum {
+       OMAP3EVM_BOARD_GEN_1 = 0,       /* EVM Rev between  A - D */
+       OMAP3EVM_BOARD_GEN_2,           /* EVM Rev >= Rev E */
+};
+
 static u8 omap3_evm_version;
 
 u8 get_omap3_evm_rev(void)
@@ -109,7 +119,7 @@ static void __init omap3_evm_get_revision(void)
 }
 
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 
 static struct omap_smsc911x_platform_data smsc911x_cfg = {
        .cs             = OMAP3EVM_SMSC911X_CS,
@@ -378,9 +388,6 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
 }
 
 static struct twl4030_gpio_platform_data omap3evm_gpio_data = {
-       .gpio_base      = OMAP_MAX_GPIO_LINES,
-       .irq_base       = TWL4030_GPIO_IRQ_BASE,
-       .irq_end        = TWL4030_GPIO_IRQ_END,
        .use_leds       = true,
        .setup          = omap3evm_twl_gpio_setup,
 };
@@ -527,9 +534,6 @@ static int __init omap3_evm_i2c_init(void)
        return 0;
 }
 
-static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
-};
-
 static struct usbhs_omap_board_data usbhs_bdata __initdata = {
 
        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
@@ -689,9 +693,6 @@ static void __init omap3_evm_init(void)
        obm = (cpu_is_omap3630()) ? omap36x_board_mux : omap35x_board_mux;
        omap3_mux_init(obm, OMAP_PACKAGE_CBB);
 
-       omap_board_config = omap3_evm_config;
-       omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
-
        omap_mux_init_gpio(63, OMAP_PIN_INPUT);
        omap_hsmmc_init(mmc);
 
index fca93d1..7bd8253 100644 (file)
 #include <linux/i2c/twl.h>
 #include <linux/mmc/host.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
+#include "gpmc-smsc911x.h"
+#include <plat/gpmc.h>
+#include <plat/sdrc.h>
+#include <plat/usb.h>
+
+#include "common.h"
 #include "mux.h"
 #include "hsmmc.h"
 #include "control.h"
 #include "common-board-devices.h"
 
-#include <plat/mux.h>
-#include <plat/board.h>
-#include "common.h"
-#include <plat/gpmc-smsc911x.h>
-#include <plat/gpmc.h>
-#include <plat/sdrc.h>
-#include <plat/usb.h>
-
 #define OMAP3LOGIC_SMSC911X_CS                 1
 
 #define OMAP3530_LV_SOM_MMC_GPIO_CD            110
@@ -78,9 +75,6 @@ static struct regulator_init_data omap3logic_vmmc1 = {
 };
 
 static struct twl4030_gpio_platform_data omap3logic_gpio_data = {
-       .gpio_base      = OMAP_MAX_GPIO_LINES,
-       .irq_base       = TWL4030_GPIO_IRQ_BASE,
-       .irq_end        = TWL4030_GPIO_IRQ_END,
        .use_leds       = true,
        .pullups        = BIT(1),
        .pulldowns      = BIT(2)  | BIT(6)  | BIT(7)  | BIT(8)
index 57aebee..00a1f4a 100644 (file)
 #include <linux/mmc/host.h>
 #include <linux/mmc/card.h>
 #include <linux/regulator/fixed.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
 #include "common.h"
-#include <mach/hardware.h>
-#include <plat/mcspi.h>
 #include <plat/usb.h>
 #include <video/omapdss.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
@@ -321,9 +319,6 @@ static int omap3pandora_twl_gpio_setup(struct device *dev,
 }
 
 static struct twl4030_gpio_platform_data omap3pandora_gpio_data = {
-       .gpio_base      = OMAP_MAX_GPIO_LINES,
-       .irq_base       = TWL4030_GPIO_IRQ_BASE,
-       .irq_end        = TWL4030_GPIO_IRQ_END,
        .setup          = omap3pandora_twl_gpio_setup,
 };
 
index b318f56..c7f3d02 100644 (file)
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
 #include <linux/mmc/host.h>
+#include <linux/input/matrix_keypad.h>
+#include <linux/spi/spi.h>
+#include <linux/interrupt.h>
+#include <linux/smsc911x.h>
+#include <linux/i2c/at24.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
 
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/spi/spi.h>
 #include <linux/interrupt.h>
@@ -57,7 +60,7 @@
 #include "common-board-devices.h"
 
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 
 #define OMAP3STALKER_ETHR_START        0x2c000000
 #define OMAP3STALKER_ETHR_SIZE 1024
@@ -279,9 +282,6 @@ omap3stalker_twl_gpio_setup(struct device *dev,
 }
 
 static struct twl4030_gpio_platform_data omap3stalker_gpio_data = {
-       .gpio_base      = OMAP_MAX_GPIO_LINES,
-       .irq_base       = TWL4030_GPIO_IRQ_BASE,
-       .irq_end        = TWL4030_GPIO_IRQ_END,
        .use_leds       = true,
        .setup          = omap3stalker_twl_gpio_setup,
 };
@@ -362,9 +362,6 @@ static int __init omap3_stalker_i2c_init(void)
 
 #define OMAP3_STALKER_TS_GPIO  175
 
-static struct omap_board_config_kernel omap3_stalker_config[] __initdata = {
-};
-
 static struct platform_device *omap3_stalker_devices[] __initdata = {
        &keys_gpio,
 };
@@ -399,8 +396,6 @@ static void __init omap3_stalker_init(void)
 {
        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
        omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
-       omap_board_config = omap3_stalker_config;
-       omap_board_config_size = ARRAY_SIZE(omap3_stalker_config);
 
        omap_mux_init_gpio(23, OMAP_PIN_INPUT);
        omap_hsmmc_init(mmc);
index 485d14d..944ffc4 100644 (file)
@@ -29,7 +29,7 @@
 #include <linux/mtd/nand.h>
 #include <linux/mmc/host.h>
 
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/spi/spi.h>
 
 #include <linux/spi/ads7846.h>
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 #include <asm/system_info.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 #include <plat/usb.h>
 
 #include "mux.h"
@@ -139,9 +137,6 @@ static int touchbook_twl_gpio_setup(struct device *dev,
 }
 
 static struct twl4030_gpio_platform_data touchbook_gpio_data = {
-       .gpio_base      = OMAP_MAX_GPIO_LINES,
-       .irq_base       = TWL4030_GPIO_IRQ_BASE,
-       .irq_end        = TWL4030_GPIO_IRQ_END,
        .use_leds       = true,
        .pullups        = BIT(1),
        .pulldowns      = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13)
index 70f6d1d..7b592d3 100644 (file)
 #include <linux/wl12xx.h>
 #include <linux/platform_data/omap-abe-twl6040.h>
 
-#include <mach/hardware.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <video/omapdss.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <plat/usb.h>
 #include <plat/mmc.h>
 #include <video/omap-panel-tfp410.h>
 
+#include "soc.h"
 #include "hsmmc.h"
 #include "control.h"
 #include "mux.h"
@@ -263,7 +262,14 @@ static struct twl6040_codec_data twl6040_codec = {
 static struct twl6040_platform_data twl6040_data = {
        .codec          = &twl6040_codec,
        .audpwron_gpio  = 127,
-       .irq_base       = TWL6040_CODEC_IRQ_BASE,
+};
+
+static struct i2c_board_info __initdata panda_i2c_1_boardinfo[] = {
+       {
+               I2C_BOARD_INFO("twl6040", 0x4b),
+               .irq = 119 + OMAP44XX_IRQ_GIC_START,
+               .platform_data = &twl6040_data,
+       },
 };
 
 /* Panda board uses the common PMIC configuration */
@@ -293,8 +299,8 @@ static int __init omap4_panda_i2c_init(void)
                        TWL_COMMON_REGULATOR_CLK32KG |
                        TWL_COMMON_REGULATOR_V1V8 |
                        TWL_COMMON_REGULATOR_V2V1);
-       omap4_pmic_init("twl6030", &omap4_panda_twldata,
-                       &twl6040_data, OMAP44XX_IRQ_SYS_2N);
+       omap4_pmic_init("twl6030", &omap4_panda_twldata, panda_i2c_1_boardinfo,
+                       ARRAY_SIZE(panda_i2c_1_boardinfo));
        omap_register_i2c_bus(2, 400, NULL, 0);
        /*
         * Bus 3 is attached to the DVI port where devices like the pico DLP
index 779734d..2e7f240 100644 (file)
 #include <linux/mtd/partitions.h>
 #include <linux/mmc/host.h>
 
+#include <linux/platform_data/mtd-nand-omap2.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
 #include "common.h"
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-tfp410.h>
 #include <plat/gpmc.h>
-#include <mach/hardware.h>
-#include <plat/nand.h>
-#include <plat/mcspi.h>
-#include <plat/mux.h>
 #include <plat/usb.h>
 
 #include "mux.h"
@@ -116,7 +114,7 @@ static inline void __init overo_ads7846_init(void) { return; }
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 
 #include <linux/smsc911x.h>
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 
 static struct omap_smsc911x_platform_data smsc911x_cfg = {
        .id             = 0,
@@ -399,9 +397,6 @@ static int overo_twl_gpio_setup(struct device *dev,
 }
 
 static struct twl4030_gpio_platform_data overo_gpio_data = {
-       .gpio_base      = OMAP_MAX_GPIO_LINES,
-       .irq_base       = TWL4030_GPIO_IRQ_BASE,
-       .irq_end        = TWL4030_GPIO_IRQ_END,
        .use_leds       = true,
        .setup          = overo_twl_gpio_setup,
 };
@@ -522,8 +517,7 @@ static void __init overo_init(void)
                udelay(10);
                gpio_set_value(OVERO_GPIO_W2W_NRESET, 1);
        } else {
-               printk(KERN_ERR "could not obtain gpio for "
-                                       "OVERO_GPIO_W2W_NRESET\n");
+               pr_err("could not obtain gpio for OVERO_GPIO_W2W_NRESET\n");
        }
 
        ret = gpio_request_array(overo_bt_gpios, ARRAY_SIZE(overo_bt_gpios));
@@ -542,8 +536,7 @@ static void __init overo_init(void)
        if (ret == 0)
                gpio_export(OVERO_GPIO_USBH_CPEN, 0);
        else
-               printk(KERN_ERR "could not obtain gpio for "
-                                       "OVERO_GPIO_USBH_CPEN\n");
+               pr_err("could not obtain gpio for OVERO_GPIO_USBH_CPEN\n");
 }
 
 MACHINE_START(OVERO, "Gumstix Overo")
index 0ad1bb3..45997bf 100644 (file)
@@ -17,6 +17,7 @@
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/consumer.h>
+#include <linux/platform_data/mtd-onenand-omap2.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
@@ -26,7 +27,7 @@
 #include <plat/usb.h>
 #include <plat/gpmc.h>
 #include "common.h"
-#include <plat/onenand.h>
+#include <plat/serial.h>
 
 #include "mux.h"
 #include "hsmmc.h"
@@ -72,9 +73,6 @@ static struct platform_device *rm680_peripherals_devices[] __initdata = {
 
 /* TWL */
 static struct twl4030_gpio_platform_data rm680_gpio_data = {
-       .gpio_base              = OMAP_MAX_GPIO_LINES,
-       .irq_base               = TWL4030_GPIO_IRQ_BASE,
-       .irq_end                = TWL4030_GPIO_IRQ_END,
        .pullups                = BIT(0),
        .pulldowns              = BIT(1) | BIT(2) | BIT(8) | BIT(15),
 };
@@ -87,7 +85,7 @@ static struct twl4030_platform_data rm680_twl_data = {
 static void __init rm680_i2c_init(void)
 {
        omap3_pmic_get_config(&rm680_twl_data, TWL_COMMON_PDATA_USB, 0);
-       omap_pmic_init(1, 2900, "twl5031", INT_34XX_SYS_NIRQ, &rm680_twl_data);
+       omap_pmic_init(1, 2900, "twl5031", 7 + OMAP_INTC_START, &rm680_twl_data);
        omap_register_i2c_bus(2, 400, NULL, 0);
        omap_register_i2c_bus(3, 400, NULL, 0);
 }
index df2534d..3945c50 100644 (file)
 #include <linux/gpio_keys.h>
 #include <linux/mmc/host.h>
 #include <linux/power/isp1704_charger.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/platform_data/mtd-onenand-omap2.h>
+
 #include <asm/system_info.h>
 
-#include <plat/mcspi.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/dma.h>
 #include <plat/gpmc.h>
-#include <plat/onenand.h>
-#include <plat/gpmc-smc91x.h>
+#include "gpmc-smc91x.h"
 
-#include <mach/board-rx51.h>
+#include "board-rx51.h"
 
 #include <sound/tlv320aic3x.h>
 #include <sound/tpa6130a2-plat.h>
@@ -774,9 +774,6 @@ static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n)
 }
 
 static struct twl4030_gpio_platform_data rx51_gpio_data = {
-       .gpio_base              = OMAP_MAX_GPIO_LINES,
-       .irq_base               = TWL4030_GPIO_IRQ_BASE,
-       .irq_end                = TWL4030_GPIO_IRQ_END,
        .pulldowns              = BIT(0) | BIT(1) | BIT(2) | BIT(3)
                                | BIT(4) | BIT(5)
                                | BIT(8) | BIT(9) | BIT(10) | BIT(11)
@@ -1051,7 +1048,7 @@ static int __init rx51_i2c_init(void)
        rx51_twldata.vdac->constraints.apply_uV = true;
        rx51_twldata.vdac->constraints.name = "VDAC";
 
-       omap_pmic_init(1, 2200, "twl5030", INT_34XX_SYS_NIRQ, &rx51_twldata);
+       omap_pmic_init(1, 2200, "twl5030", 7 + OMAP_INTC_START, &rx51_twldata);
        omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2,
                              ARRAY_SIZE(rx51_peripherals_i2c_board_info_2));
 #if defined(CONFIG_SENSORS_LIS3_I2C) || defined(CONFIG_SENSORS_LIS3_I2C_MODULE)
index 2c1289b..c22e111 100644 (file)
@@ -17,9 +17,9 @@
 #include <asm/mach-types.h>
 #include <video/omapdss.h>
 #include <plat/vram.h>
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
-#include <mach/board-rx51.h>
+#include "board-rx51.h"
 
 #include "mux.h"
 
index 345dd93..7bbb05d 100644 (file)
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/mcspi.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/dma.h>
 #include <plat/gpmc.h>
index d4c8392..c4f8833 100644 (file)
 #include <linux/kernel.h>
 #include <linux/init.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/irqs.h>
-#include <plat/board.h>
 #include "common.h"
 #include <plat/usb.h>
 
@@ -32,15 +29,10 @@ static struct omap_musb_board_data musb_board_data = {
        .power          = 500,
 };
 
-static struct omap_board_config_kernel ti81xx_evm_config[] __initdata = {
-};
-
 static void __init ti81xx_evm_init(void)
 {
        omap_serial_init();
        omap_sdrc_init(NULL, NULL);
-       omap_board_config = ti81xx_evm_config;
-       omap_board_config_size = ARRAY_SIZE(ti81xx_evm_config);
        usb_musb_init(&musb_board_data);
 }
 
index f64f441..afb2278 100644 (file)
 #include <linux/regulator/machine.h>
 
 #include <plat/gpmc.h>
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 
 #include <mach/board-zoom.h>
 
+#include "soc.h"
+#include "common.h"
+
 #define ZOOM_SMSC911X_CS       7
 #define ZOOM_SMSC911X_GPIO     158
 #define ZOOM_QUADUART_CS       3
@@ -81,8 +84,7 @@ static inline void __init zoom_init_quaduart(void)
        quart_cs = ZOOM_QUADUART_CS;
 
        if (gpmc_cs_request(quart_cs, SZ_1M, &cs_mem_base) < 0) {
-               printk(KERN_ERR "Failed to request GPMC mem"
-                               "for Quad UART(TL16CP754C)\n");
+               pr_err("Failed to request GPMC mem for Quad UART(TL16CP754C)\n");
                return;
        }
 
@@ -104,8 +106,8 @@ static inline int omap_zoom_debugboard_detect(void)
 
        if (gpio_request_one(debug_board_detect, GPIOF_IN,
                             "Zoom debug board detect") < 0) {
-               printk(KERN_ERR "Failed to request GPIO%d for Zoom debug"
-               "board detect\n", debug_board_detect);
+               pr_err("Failed to request GPIO%d for Zoom debug board detect\n",
+                      debug_board_detect);
                return 0;
        }
 
index 28187f1..b940ab2 100644 (file)
 #include <linux/gpio.h>
 #include <linux/i2c/twl.h>
 #include <linux/spi/spi.h>
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <video/omapdss.h>
 #include <mach/board-zoom.h>
 
+#include "common.h"
+
 #define LCD_PANEL_RESET_GPIO_PROD      96
 #define LCD_PANEL_RESET_GPIO_PILOT     55
 #define LCD_PANEL_QVGA_GPIO            56
index b797cb2..6bcc107 100644 (file)
@@ -19,6 +19,7 @@
 #include <linux/regulator/fixed.h>
 #include <linux/wl12xx.h>
 #include <linux/mmc/host.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -251,9 +252,6 @@ static void zoom2_set_hs_extmute(int mute)
 }
 
 static struct twl4030_gpio_platform_data zoom_gpio_data = {
-       .gpio_base      = OMAP_MAX_GPIO_LINES,
-       .irq_base       = TWL4030_GPIO_IRQ_BASE,
-       .irq_end        = TWL4030_GPIO_IRQ_END,
        .setup          = zoom_twl_gpio_setup,
 };
 
@@ -281,7 +279,7 @@ static int __init omap_i2c_init(void)
                codec_data->hs_extmute = 1;
                codec_data->set_hs_extmute = zoom2_set_hs_extmute;
        }
-       omap_pmic_init(1, 2400, "twl5030", INT_34XX_SYS_NIRQ, &zoom_twldata);
+       omap_pmic_init(1, 2400, "twl5030", 7 + OMAP_INTC_START, &zoom_twldata);
        omap_register_i2c_bus(2, 400, NULL, 0);
        omap_register_i2c_bus(3, 400, NULL, 0);
        return 0;
index 4e7e561..4994438 100644 (file)
@@ -22,7 +22,6 @@
 #include <asm/mach/arch.h>
 
 #include "common.h"
-#include <plat/board.h>
 #include <plat/usb.h>
 
 #include <mach/board-zoom.h>
index 3d9d746..cabcfdb 100644 (file)
 #include <linux/cpufreq.h>
 #include <linux/slab.h>
 
-#include <plat/cpu.h>
 #include <plat/clock.h>
 #include <plat/sram.h>
 #include <plat/sdrc.h>
 
+#include "soc.h"
 #include "clock.h"
 #include "clock2xxx.h"
 #include "opp2xxx.h"
index d6e34dd..298887b 100644 (file)
@@ -92,15 +92,13 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 
        pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
                 validrate);
-       pr_debug("clock: SDRC CS0 timing params used:"
-                " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
+       pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
                 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
                 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
        if (sdrc_cs1)
-               pr_debug("clock: SDRC CS1 timing params used: "
-                " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
-                sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
-                sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
+               pr_debug("clock: SDRC CS1 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
+                        sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
+                        sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
 
        if (sdrc_cs1)
                omap3_configure_core_dpll(
index 04d551b..19a9809 100644 (file)
@@ -71,8 +71,8 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk,
 
        if (!clks->parent) {
                /* This indicates a data problem */
-               WARN(1, "clock: Could not find parent clock %s in clksel array "
-                    "of clock %s\n", src_clk->name, clk->name);
+               WARN(1, "clock: %s: could not find parent clock %s in clksel array\n",
+                    clk->name, src_clk->name);
                return NULL;
        }
 
@@ -126,8 +126,8 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
 
        if (max_div == 0) {
                /* This indicates an error in the clksel data */
-               WARN(1, "clock: Could not find divisor for clock %s parent %s"
-                    "\n", clk->name, src_clk->parent->name);
+               WARN(1, "clock: %s: could not find divisor for parent %s\n",
+                    clk->name, src_clk->parent->name);
                return 0;
        }
 
@@ -191,8 +191,8 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
 
        if (!clkr->div) {
                /* This indicates a data error */
-               WARN(1, "clock: Could not find fieldval %d for clock %s parent "
-                    "%s\n", field_val, clk->name, clk->parent->name);
+               WARN(1, "clock: %s: could not find fieldval %d parent %s\n",
+                    clk->name, field_val, clk->parent->name);
                return 0;
        }
 
@@ -230,8 +230,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
        }
 
        if (!clkr->div) {
-               pr_err("clock: Could not find divisor %d for clock %s parent "
-                      "%s\n", div, clk->name, clk->parent->name);
+               pr_err("clock: %s: could not find divisor %d parent %s\n",
+                      clk->name, div, clk->parent->name);
                return ~0;
        }
 
@@ -300,8 +300,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
 
                /* Sanity check */
                if (clkr->div <= last_div)
-                       pr_err("clock: clksel_rate table not sorted "
-                              "for clock %s", clk->name);
+                       pr_err("clock: %s: clksel_rate table not sorted",
+                              clk->name);
 
                last_div = clkr->div;
 
@@ -312,9 +312,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
        }
 
        if (!clkr->div) {
-               pr_err("clock: Could not find divisor for target "
-                      "rate %ld for clock %s parent %s\n", target_rate,
-                      clk->name, clk->parent->name);
+               pr_err("clock: %s: could not find divisor for target rate %ld parent %s\n",
+                      clk->name, target_rate, clk->parent->name);
                return ~0;
        }
 
@@ -359,8 +358,7 @@ void omap2_init_clksel_parent(struct clk *clk)
 
                        if (clkr->val == r) {
                                if (clk->parent != clks->parent) {
-                                       pr_debug("clock: inited %s parent "
-                                                "to %s (was %s)\n",
+                                       pr_debug("clock: %s: inited parent to %s (was %s)\n",
                                                 clk->name, clks->parent->name,
                                                 ((clk->parent) ?
                                                  clk->parent->name : "NULL"));
index cd7fd0f..a3b60c7 100644 (file)
@@ -22,8 +22,8 @@
 #include <asm/div64.h>
 
 #include <plat/clock.h>
-#include <plat/cpu.h>
 
+#include "soc.h"
 #include "clock.h"
 #include "cm-regbits-24xx.h"
 #include "cm-regbits-34xx.h"
@@ -105,13 +105,13 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
        }
 
        if (fint < fint_min) {
-               pr_debug("rejecting n=%d due to Fint failure, "
-                        "lowering max_divider\n", n);
+               pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n",
+                        n);
                dd->max_divider = n;
                ret = DPLL_FINT_UNDERFLOW;
        } else if (fint > fint_max) {
-               pr_debug("rejecting n=%d due to Fint failure, "
-                        "boosting min_divider\n", n);
+               pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n",
+                        n);
                dd->min_divider = n;
                ret = DPLL_FINT_INVALID;
        } else if (cpu_is_omap3430() && fint > OMAP3430_DPLL_FINT_BAND1_MAX &&
index ea3f565..e97f98f 100644 (file)
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/bitops.h>
-#include <trace/events/power.h>
 
 #include <asm/cpu.h>
+
 #include <plat/clock.h>
-#include "clockdomain.h"
-#include <plat/cpu.h>
 #include <plat/prcm.h>
 
+#include <trace/events/power.h>
+
+#include "soc.h"
+#include "clockdomain.h"
 #include "clock.h"
 #include "cm2xxx_3xxx.h"
 #include "cm-regbits-24xx.h"
@@ -102,8 +104,8 @@ void omap2_init_clk_clkdm(struct clk *clk)
                         clk->name, clk->clkdm_name);
                clk->clkdm = clkdm;
        } else {
-               pr_debug("clock: could not associate clk %s to "
-                        "clkdm %s\n", clk->name, clk->clkdm_name);
+               pr_debug("clock: could not associate clk %s to clkdm %s\n",
+                        clk->name, clk->clkdm_name);
        }
 }
 
@@ -226,8 +228,7 @@ void omap2_dflt_clk_disable(struct clk *clk)
                 * 'Independent' here refers to a clock which is not
                 * controlled by its parent.
                 */
-               printk(KERN_ERR "clock: clk_disable called on independent "
-                      "clock %s which has no enable_reg\n", clk->name);
+               pr_err("clock: clk_disable called on independent clock %s which has no enable_reg\n", clk->name);
                return;
        }
 
@@ -270,8 +271,7 @@ const struct clkops clkops_omap2_dflt = {
 void omap2_clk_disable(struct clk *clk)
 {
        if (clk->usecount == 0) {
-               WARN(1, "clock: %s: omap2_clk_disable() called, but usecount "
-                    "already 0?", clk->name);
+               WARN(1, "clock: %s: omap2_clk_disable() called, but usecount already 0?", clk->name);
                return;
        }
 
@@ -332,8 +332,8 @@ int omap2_clk_enable(struct clk *clk)
        if (clkdm_control && clk->clkdm) {
                ret = clkdm_clk_enable(clk->clkdm, clk);
                if (ret) {
-                       WARN(1, "clock: %s: could not enable clockdomain %s: "
-                            "%d\n", clk->name, clk->clkdm->name, ret);
+                       WARN(1, "clock: %s: could not enable clockdomain %s: %d\n",
+                            clk->name, clk->clkdm->name, ret);
                        goto oce_err2;
                }
        }
@@ -501,10 +501,8 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
 
        hfclkin_rate = clk_get_rate(hfclkin_ck);
 
-       pr_info("Switched to new clocking rate (Crystal/Core/MPU): "
-               "%ld.%01ld/%ld/%ld MHz\n",
-               (hfclkin_rate / 1000000),
-               ((hfclkin_rate / 100000) % 10),
+       pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
+               (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10),
                (clk_get_rate(core_ck) / 1000000),
                (clk_get_rate(mpu_ck) / 1000000));
 }
index 0027451..12c178d 100644 (file)
@@ -18,9 +18,9 @@
 #include <linux/clk.h>
 #include <linux/list.h>
 
-#include <plat/hardware.h>
 #include <plat/clkdev_omap.h>
 
+#include "soc.h"
 #include "iomap.h"
 #include "clock.h"
 #include "clock2xxx.h"
index dfda9a3..a8e3261 100644 (file)
@@ -21,9 +21,9 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/hardware.h>
 #include <plat/clock.h>
 
+#include "soc.h"
 #include "iomap.h"
 #include "clock.h"
 #include "clock2xxx.h"
index cacabb0..7ea9139 100644 (file)
@@ -17,9 +17,9 @@
 #include <linux/clk.h>
 #include <linux/list.h>
 
-#include <plat/hardware.h>
 #include <plat/clkdev_omap.h>
 
+#include "soc.h"
 #include "iomap.h"
 #include "clock.h"
 #include "clock2xxx.h"
@@ -1856,6 +1856,7 @@ static struct omap_clk omap2430_clks[] = {
        CLK(NULL,       "func_32k_ck",  &func_32k_ck,   CK_243X),
        CLK(NULL,       "secure_32k_ck", &secure_32k_ck, CK_243X),
        CLK(NULL,       "osc_ck",       &osc_ck,        CK_243X),
+       CLK("twl",      "fck",          &osc_ck,        CK_243X),
        CLK(NULL,       "sys_ck",       &sys_ck,        CK_243X),
        CLK(NULL,       "alt_ck",       &alt_ck,        CK_243X),
        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_243X),
index 1250009..e92be1f 100644 (file)
@@ -22,9 +22,9 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/cpu.h>
 #include <plat/clock.h>
 
+#include "soc.h"
 #include "clock.h"
 #include "clock2xxx.h"
 #include "cm.h"
index ae27de8..8e06de6 100644 (file)
@@ -18,8 +18,8 @@
 #include <linux/list.h>
 #include <linux/clk.h>
 #include <plat/clkdev_omap.h>
-#include <plat/am33xx.h>
 
+#include "am33xx.h"
 #include "iomap.h"
 #include "control.h"
 #include "clock.h"
index 794d827..15cdc64 100644 (file)
@@ -21,9 +21,9 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/hardware.h>
 #include <plat/clock.h>
 
+#include "soc.h"
 #include "clock.h"
 #include "clock3xxx.h"
 #include "prm2xxx_3xxx.h"
@@ -49,8 +49,7 @@ int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
         * on DPLL4.
         */
        if (omap_rev() == OMAP3430_REV_ES1_0) {
-               pr_err("clock: DPLL4 cannot change rate due to "
-                      "silicon 'Limitation 2.5' on 3430ES1.\n");
+               pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
                return -EINVAL;
        }
 
index 83bed9a..700317a 100644 (file)
@@ -21,9 +21,9 @@
 #include <linux/list.h>
 #include <linux/io.h>
 
-#include <plat/hardware.h>
 #include <plat/clkdev_omap.h>
 
+#include "soc.h"
 #include "iomap.h"
 #include "clock.h"
 #include "clock3xxx.h"
@@ -3226,6 +3226,7 @@ static struct omap_clk omap3xxx_clks[] = {
        CLK(NULL,       "virt_26000000_ck",     &virt_26000000_ck,      CK_3XXX),
        CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
        CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_3XXX),
+       CLK("twl",      "fck",          &osc_sys_ck,    CK_3XXX),
        CLK(NULL,       "sys_ck",       &sys_ck,        CK_3XXX),
        CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_3XXX),
        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_3XXX),
index d7f55e4..500682c 100644 (file)
@@ -28,9 +28,9 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/hardware.h>
 #include <plat/clkdev_omap.h>
 
+#include "soc.h"
 #include "iomap.h"
 #include "clock.h"
 #include "clock44xx.h"
index 8664f5a..a155562 100644 (file)
@@ -174,9 +174,8 @@ void _clkdm_add_autodeps(struct clockdomain *clkdm)
                if (IS_ERR(autodep->clkdm.ptr))
                        continue;
 
-               pr_debug("clockdomain: adding %s sleepdep/wkdep for "
-                        "clkdm %s\n", autodep->clkdm.ptr->name,
-                        clkdm->name);
+               pr_debug("clockdomain: %s: adding %s sleepdep/wkdep\n",
+                        clkdm->name, autodep->clkdm.ptr->name);
 
                clkdm_add_sleepdep(clkdm, autodep->clkdm.ptr);
                clkdm_add_wkdep(clkdm, autodep->clkdm.ptr);
@@ -205,9 +204,8 @@ void _clkdm_del_autodeps(struct clockdomain *clkdm)
                if (IS_ERR(autodep->clkdm.ptr))
                        continue;
 
-               pr_debug("clockdomain: removing %s sleepdep/wkdep for "
-                        "clkdm %s\n", autodep->clkdm.ptr->name,
-                        clkdm->name);
+               pr_debug("clockdomain: %s: removing %s sleepdep/wkdep\n",
+                        clkdm->name, autodep->clkdm.ptr->name);
 
                clkdm_del_sleepdep(clkdm, autodep->clkdm.ptr);
                clkdm_del_wkdep(clkdm, autodep->clkdm.ptr);
@@ -469,14 +467,14 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
                ret = -EINVAL;
 
        if (ret) {
-               pr_debug("clockdomain: hardware cannot set/clear wake up of "
-                        "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+               pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
+                        clkdm1->name, clkdm2->name);
                return ret;
        }
 
        if (atomic_inc_return(&cd->wkdep_usecount) == 1) {
-               pr_debug("clockdomain: hardware will wake up %s when %s wakes "
-                        "up\n", clkdm1->name, clkdm2->name);
+               pr_debug("clockdomain: hardware will wake up %s when %s wakes up\n",
+                        clkdm1->name, clkdm2->name);
 
                ret = arch_clkdm->clkdm_add_wkdep(clkdm1, clkdm2);
        }
@@ -510,14 +508,14 @@ int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
                ret = -EINVAL;
 
        if (ret) {
-               pr_debug("clockdomain: hardware cannot set/clear wake up of "
-                        "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+               pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
+                        clkdm1->name, clkdm2->name);
                return ret;
        }
 
        if (atomic_dec_return(&cd->wkdep_usecount) == 0) {
-               pr_debug("clockdomain: hardware will no longer wake up %s "
-                        "after %s wakes up\n", clkdm1->name, clkdm2->name);
+               pr_debug("clockdomain: hardware will no longer wake up %s after %s wakes up\n",
+                        clkdm1->name, clkdm2->name);
 
                ret = arch_clkdm->clkdm_del_wkdep(clkdm1, clkdm2);
        }
@@ -555,8 +553,8 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
                ret = -EINVAL;
 
        if (ret) {
-               pr_debug("clockdomain: hardware cannot set/clear wake up of "
-                        "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+               pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
+                        clkdm1->name, clkdm2->name);
                return ret;
        }
 
@@ -613,15 +611,14 @@ int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
                ret = -EINVAL;
 
        if (ret) {
-               pr_debug("clockdomain: hardware cannot set/clear sleep "
-                        "dependency affecting %s from %s\n", clkdm1->name,
-                        clkdm2->name);
+               pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
+                        clkdm1->name, clkdm2->name);
                return ret;
        }
 
        if (atomic_inc_return(&cd->sleepdep_usecount) == 1) {
-               pr_debug("clockdomain: will prevent %s from sleeping if %s "
-                        "is active\n", clkdm1->name, clkdm2->name);
+               pr_debug("clockdomain: will prevent %s from sleeping if %s is active\n",
+                        clkdm1->name, clkdm2->name);
 
                ret = arch_clkdm->clkdm_add_sleepdep(clkdm1, clkdm2);
        }
@@ -657,16 +654,14 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
                ret = -EINVAL;
 
        if (ret) {
-               pr_debug("clockdomain: hardware cannot set/clear sleep "
-                        "dependency affecting %s from %s\n", clkdm1->name,
-                        clkdm2->name);
+               pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
+                        clkdm1->name, clkdm2->name);
                return ret;
        }
 
        if (atomic_dec_return(&cd->sleepdep_usecount) == 0) {
-               pr_debug("clockdomain: will no longer prevent %s from "
-                        "sleeping if %s is active\n", clkdm1->name,
-                        clkdm2->name);
+               pr_debug("clockdomain: will no longer prevent %s from sleeping if %s is active\n",
+                        clkdm1->name, clkdm2->name);
 
                ret = arch_clkdm->clkdm_del_sleepdep(clkdm1, clkdm2);
        }
@@ -706,9 +701,8 @@ int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
                ret = -EINVAL;
 
        if (ret) {
-               pr_debug("clockdomain: hardware cannot set/clear sleep "
-                        "dependency affecting %s from %s\n", clkdm1->name,
-                        clkdm2->name);
+               pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
+                        clkdm1->name, clkdm2->name);
                return ret;
        }
 
@@ -755,8 +749,8 @@ int clkdm_sleep(struct clockdomain *clkdm)
                return -EINVAL;
 
        if (!(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
-               pr_debug("clockdomain: %s does not support forcing "
-                        "sleep via software\n", clkdm->name);
+               pr_debug("clockdomain: %s does not support forcing sleep via software\n",
+                        clkdm->name);
                return -EINVAL;
        }
 
@@ -790,8 +784,8 @@ int clkdm_wakeup(struct clockdomain *clkdm)
                return -EINVAL;
 
        if (!(clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
-               pr_debug("clockdomain: %s does not support forcing "
-                        "wakeup via software\n", clkdm->name);
+               pr_debug("clockdomain: %s does not support forcing wakeup via software\n",
+                        clkdm->name);
                return -EINVAL;
        }
 
@@ -826,8 +820,8 @@ void clkdm_allow_idle(struct clockdomain *clkdm)
                return;
 
        if (!(clkdm->flags & CLKDM_CAN_ENABLE_AUTO)) {
-               pr_debug("clock: automatic idle transitions cannot be enabled "
-                        "on clockdomain %s\n", clkdm->name);
+               pr_debug("clock: %s: automatic idle transitions cannot be enabled\n",
+                        clkdm->name);
                return;
        }
 
@@ -861,8 +855,8 @@ void clkdm_deny_idle(struct clockdomain *clkdm)
                return;
 
        if (!(clkdm->flags & CLKDM_CAN_DISABLE_AUTO)) {
-               pr_debug("clockdomain: automatic idle transitions cannot be "
-                        "disabled on %s\n", clkdm->name);
+               pr_debug("clockdomain: %s: automatic idle transitions cannot be disabled\n",
+                        clkdm->name);
                return;
        }
 
@@ -927,7 +921,7 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
        pwrdm_state_switch(clkdm->pwrdm.ptr);
        spin_unlock_irqrestore(&clkdm->lock, flags);
 
-       pr_debug("clockdomain: clkdm %s: enabled\n", clkdm->name);
+       pr_debug("clockdomain: %s: enabled\n", clkdm->name);
 
        return 0;
 }
@@ -952,7 +946,7 @@ static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
        pwrdm_state_switch(clkdm->pwrdm.ptr);
        spin_unlock_irqrestore(&clkdm->lock, flags);
 
-       pr_debug("clockdomain: clkdm %s: disabled\n", clkdm->name);
+       pr_debug("clockdomain: %s: disabled\n", clkdm->name);
 
        return 0;
 }
index 389f9f8..a911e76 100644 (file)
@@ -18,8 +18,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include <plat/hardware.h>
-
+#include "soc.h"
 #include "iomap.h"
 #include "common.h"
 #include "cm.h"
index c187586..48daac2 100644 (file)
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 
-#include <plat/mcspi.h>
-#include <plat/nand.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 
+#include "common.h"
 #include "common-board-devices.h"
 
 #if defined(CONFIG_TOUCHSCREEN_ADS7846) || \
@@ -119,8 +120,7 @@ void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
        }
 
        if (nandcs > GPMC_CS_NUM) {
-               printk(KERN_INFO "NAND: Unable to find configuration "
-                                "in GPMC\n ");
+               pr_info("NAND: Unable to find configuration in GPMC\n");
                return;
        }
 
index 069f972..17950c6 100644 (file)
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/hardware.h>
-#include <plat/board.h>
-#include <plat/mux.h>
 #include <plat/clock.h>
 
+#include "soc.h"
 #include "iomap.h"
 #include "common.h"
 #include "sdrc.h"
index 1f65b18..da0f5c1 100644 (file)
 #define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
 #ifndef __ASSEMBLER__
 
+#include <linux/irq.h>
 #include <linux/delay.h>
 #include <linux/i2c/twl.h>
-#include <plat/common.h>
+
 #include <asm/proc-fns.h>
 
+#include <plat/cpu.h>
+#include <plat/serial.h>
+#include <plat/common.h>
+
+#define OMAP_INTC_START                NR_IRQS
+
 #ifdef CONFIG_SOC_OMAP2420
 extern void omap242x_map_common_io(void);
 #else
index 3223b81..d1ff839 100644 (file)
@@ -15,9 +15,9 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 
-#include <plat/hardware.h>
 #include <plat/sdrc.h>
 
+#include "soc.h"
 #include "iomap.h"
 #include "common.h"
 #include "cm-regbits-34xx.h"
index b8cdc85..123186a 100644 (file)
 #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H
 #define __ARCH_ARM_MACH_OMAP2_CONTROL_H
 
-#include <mach/ctrl_module_core_44xx.h>
-#include <mach/ctrl_module_wkup_44xx.h>
-#include <mach/ctrl_module_pad_core_44xx.h>
-#include <mach/ctrl_module_pad_wkup_44xx.h>
+#include "ctrl_module_core_44xx.h"
+#include "ctrl_module_wkup_44xx.h"
+#include "ctrl_module_pad_core_44xx.h"
+#include "ctrl_module_pad_wkup_44xx.h"
 
-#include <plat/am33xx.h>
+#include "am33xx.h"
 
 #ifndef __ASSEMBLY__
 #define OMAP242X_CTRL_REGADDR(reg)                                     \
index f2a49a4..bc27569 100644 (file)
@@ -28,7 +28,6 @@
 #include <linux/cpu_pm.h>
 
 #include <plat/prcm.h>
-#include <plat/irqs.h>
 #include "powerdomain.h"
 #include "clockdomain.h"
 
diff --git a/arch/arm/mach-omap2/debug-devices.h b/arch/arm/mach-omap2/debug-devices.h
new file mode 100644 (file)
index 0000000..a4edbd2
--- /dev/null
@@ -0,0 +1,9 @@
+#ifndef _OMAP_DEBUG_DEVICES_H
+#define _OMAP_DEBUG_DEVICES_H
+
+#include <linux/types.h>
+
+/* for TI reference platforms sharing the same debug card */
+extern int debug_card_init(u32 addr, unsigned gpio);
+
+#endif
index c00c689..d092d2a 100644 (file)
 #include <linux/err.h>
 #include <linux/slab.h>
 #include <linux/of.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/platform_data/omap4-keypad.h>
 
-#include <mach/hardware.h>
-#include <mach/irqs.h>
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
-#include <asm/pmu.h>
 
 #include "iomap.h"
-#include <plat/board.h>
 #include <plat/dma.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
-#include <plat/omap4-keypad.h>
+#include "omap4-keypad.h"
 
+#include "soc.h"
+#include "common.h"
 #include "mux.h"
 #include "control.h"
 #include "devices.h"
@@ -112,7 +111,7 @@ static struct resource omap2cam_resources[] = {
                .flags          = IORESOURCE_MEM,
        },
        {
-               .start          = INT_24XX_CAM_IRQ,
+               .start          = 24 + OMAP_INTC_START,
                .flags          = IORESOURCE_IRQ,
        }
 };
@@ -201,7 +200,7 @@ static struct resource omap3isp_resources[] = {
                .flags          = IORESOURCE_MEM,
        },
        {
-               .start          = INT_34XX_CAM_IRQ,
+               .start          = 24 + OMAP_INTC_START,
                .flags          = IORESOURCE_IRQ,
        }
 };
@@ -385,7 +384,7 @@ static inline void omap_init_hdmi_audio(void) {}
 
 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
 
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
 static int __init omap_mcspi_init(struct omap_hwmod *oh, void *unused)
 {
@@ -435,20 +434,18 @@ static inline void omap_init_mcspi(void) {}
 #endif
 
 static struct resource omap2_pmu_resource = {
-       .start  = 3,
-       .end    = 3,
+       .start  = 3 + OMAP_INTC_START,
        .flags  = IORESOURCE_IRQ,
 };
 
 static struct resource omap3_pmu_resource = {
-       .start  = INT_34XX_BENCH_MPU_EMUL,
-       .end    = INT_34XX_BENCH_MPU_EMUL,
+       .start  = 3 + OMAP_INTC_START,
        .flags  = IORESOURCE_IRQ,
 };
 
 static struct platform_device omap_pmu_device = {
        .name           = "arm-pmu",
-       .id             = ARM_PMU_DEVICE_CPU,
+       .id             = -1,
        .num_resources  = 1,
 };
 
@@ -475,7 +472,7 @@ static struct resource omap2_sham_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        {
-               .start  = INT_24XX_SHA1MD5,
+               .start  = 51 + OMAP_INTC_START,
                .flags  = IORESOURCE_IRQ,
        }
 };
@@ -493,7 +490,7 @@ static struct resource omap3_sham_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        {
-               .start  = INT_34XX_SHA1MD52_IRQ,
+               .start  = 49 + OMAP_INTC_START,
                .flags  = IORESOURCE_IRQ,
        },
        {
@@ -631,6 +628,10 @@ static inline void omap_init_vout(void) {}
 
 static int __init omap2_init_devices(void)
 {
+       /* Enable dummy states for those platforms without pinctrl support */
+       if (!of_have_populated_dt())
+               pinctrl_provide_dummies();
+
        /*
         * please keep these calls, and their implementations above,
         * in alphabetical order so they're easier to sort through.
index b9c8d2f..ef66645 100644 (file)
@@ -28,9 +28,9 @@
 #include <linux/bitops.h>
 #include <linux/clkdev.h>
 
-#include <plat/cpu.h>
 #include <plat/clock.h>
 
+#include "soc.h"
 #include "clock.h"
 #include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
@@ -623,8 +623,11 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
        while (pclk && !pclk->dpll_data)
                pclk = pclk->parent;
 
-       /* clk does not have a DPLL as a parent? */
-       WARN_ON(!pclk);
+       /* clk does not have a DPLL as a parent?  error in the clock data */
+       if (!pclk) {
+               WARN_ON(1);
+               return 0;
+       }
 
        dd = pclk->dpll_data;
 
index 9c6a296..09d0ccc 100644 (file)
@@ -15,9 +15,9 @@
 #include <linux/io.h>
 #include <linux/bitops.h>
 
-#include <plat/cpu.h>
 #include <plat/clock.h>
 
+#include "soc.h"
 #include "clock.h"
 #include "clock44xx.h"
 #include "cm-regbits-44xx.h"
index a636ebc..9838810 100644 (file)
@@ -30,7 +30,7 @@
 #include <plat/omap-pm.h>
 #endif
 
-#include <plat/dsp.h>
+#include <linux/platform_data/dsp-omap.h>
 
 static struct platform_device *omap_dsp_pdev;
 
index e28e761..b3566f6 100644 (file)
@@ -21,8 +21,7 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 
-#include <mach/hardware.h>
-
+#include "soc.h"
 #include "iomap.h"
 
 MODULE_LICENSE("GPL");
index fe626e9..d1058f1 100644 (file)
@@ -21,6 +21,7 @@
 #include <linux/slab.h>
 #include <linux/interrupt.h>
 #include <linux/of.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
index 386dec8..4acf497 100644 (file)
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/mtd/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 
 #include <asm/mach/flash.h>
 
-#include <plat/cpu.h>
-#include <plat/nand.h>
-#include <plat/board.h>
 #include <plat/gpmc.h>
 
-static struct resource gpmc_nand_resource = {
-       .flags          = IORESOURCE_MEM,
+#include "soc.h"
+
+static struct resource gpmc_nand_resource[] = {
+       {
+               .flags          = IORESOURCE_MEM,
+       },
+       {
+               .flags          = IORESOURCE_IRQ,
+       },
+       {
+               .flags          = IORESOURCE_IRQ,
+       },
 };
 
 static struct platform_device gpmc_nand_device = {
        .name           = "omap2-nand",
        .id             = 0,
-       .num_resources  = 1,
-       .resource       = &gpmc_nand_resource,
+       .num_resources  = ARRAY_SIZE(gpmc_nand_resource),
+       .resource       = gpmc_nand_resource,
 };
 
 static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data)
@@ -75,6 +83,7 @@ static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data
                gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0);
        gpmc_cs_configure(gpmc_nand_data->cs,
                        GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND);
+       gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_WP, 0);
        err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
        if (err)
                return err;
@@ -90,12 +99,19 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
        gpmc_nand_device.dev.platform_data = gpmc_nand_data;
 
        err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
-                               &gpmc_nand_data->phys_base);
+                               (unsigned long *)&gpmc_nand_resource[0].start);
        if (err < 0) {
                dev_err(dev, "Cannot request GPMC CS\n");
                return err;
        }
 
+       gpmc_nand_resource[0].end = gpmc_nand_resource[0].start +
+                                                       NAND_IO_SIZE - 1;
+
+       gpmc_nand_resource[1].start =
+                               gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
+       gpmc_nand_resource[2].start =
+                               gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
         /* Set timings in GPMC */
        err = omap2_nand_gpmc_retime(gpmc_nand_data);
        if (err < 0) {
@@ -108,6 +124,8 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
                gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1);
        }
 
+       gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
+
        err = platform_device_register(&gpmc_nand_device);
        if (err < 0) {
                dev_err(dev, "Unable to register NAND device\n");
index a0fa9bb..916716e 100644 (file)
 #include <linux/platform_device.h>
 #include <linux/mtd/onenand_regs.h>
 #include <linux/io.h>
+#include <linux/platform_data/mtd-onenand-omap2.h>
 
 #include <asm/mach/flash.h>
 
-#include <plat/cpu.h>
-#include <plat/onenand.h>
-#include <plat/board.h>
 #include <plat/gpmc.h>
 
+#include "soc.h"
+
+#define        ONENAND_IO_SIZE SZ_128K
+
 static struct omap_onenand_platform_data *gpmc_onenand_data;
 
+static struct resource gpmc_onenand_resource = {
+       .flags          = IORESOURCE_MEM,
+};
+
 static struct platform_device gpmc_onenand_device = {
        .name           = "omap2-onenand",
        .id             = -1,
+       .num_resources  = 1,
+       .resource       = &gpmc_onenand_resource,
 };
 
 static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
@@ -390,6 +398,8 @@ static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
 
 void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
 {
+       int err;
+
        gpmc_onenand_data = _onenand_data;
        gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
        gpmc_onenand_device.dev.platform_data = gpmc_onenand_data;
@@ -401,8 +411,19 @@ void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
                gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
        }
 
+       err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE,
+                               (unsigned long *)&gpmc_onenand_resource.start);
+       if (err < 0) {
+               pr_err("%s: Cannot request GPMC CS\n", __func__);
+               return;
+       }
+
+       gpmc_onenand_resource.end = gpmc_onenand_resource.start +
+                                                       ONENAND_IO_SIZE - 1;
+
        if (platform_device_register(&gpmc_onenand_device) < 0) {
-               printk(KERN_ERR "Unable to register OneNAND device\n");
+               pr_err("%s: Unable to register OneNAND device\n", __func__);
+               gpmc_cs_free(gpmc_onenand_data->cs);
                return;
        }
 }
index ba10c24..5654753 100644 (file)
 #include <linux/io.h>
 #include <linux/smc91x.h>
 
-#include <plat/board.h>
 #include <plat/gpmc.h>
-#include <plat/gpmc-smc91x.h>
+#include "gpmc-smc91x.h"
+
+#include "soc.h"
 
 static struct omap_smc91x_platform_data *gpmc_cfg;
 
index b6c77be..249a0b4 100644 (file)
@@ -20,9 +20,8 @@
 #include <linux/io.h>
 #include <linux/smsc911x.h>
 
-#include <plat/board.h>
 #include <plat/gpmc.h>
-#include <plat/gpmc-smsc911x.h>
+#include "gpmc-smsc911x.h"
 
 static struct resource gpmc_smsc911x_resources[] = {
        [0] = {
index b2b5759..72428bd 100644 (file)
 #include <asm/mach-types.h>
 #include <plat/gpmc.h>
 
+#include <plat/cpu.h>
+#include <plat/gpmc.h>
 #include <plat/sdrc.h>
 
+#include "soc.h"
+#include "common.h"
+
 /* GPMC register offsets */
 #define GPMC_REVISION          0x00
 #define GPMC_SYSCONFIG         0x10
 #define ENABLE_PREFETCH                (0x1 << 7)
 #define DMA_MPU_MODE           2
 
+/* XXX: Only NAND irq has been considered,currently these are the only ones used
+ */
+#define        GPMC_NR_IRQ             2
+
+struct gpmc_client_irq {
+       unsigned                irq;
+       u32                     bitmask;
+};
+
 /* Structure to save gpmc cs context */
 struct gpmc_cs_config {
        u32 config1;
@@ -105,6 +119,10 @@ struct omap3_gpmc_regs {
        struct gpmc_cs_config cs_context[GPMC_CS_NUM];
 };
 
+static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
+static struct irq_chip gpmc_irq_chip;
+static unsigned gpmc_irq_start;
+
 static struct resource gpmc_mem_root;
 static struct resource gpmc_cs_mem[GPMC_CS_NUM];
 static DEFINE_SPINLOCK(gpmc_mem_lock);
@@ -279,7 +297,7 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
 
        div = gpmc_cs_calc_divider(cs, t->sync_clk);
        if (div < 0)
-               return -1;
+               return div;
 
        GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
        GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
@@ -682,6 +700,117 @@ int gpmc_prefetch_reset(int cs)
 }
 EXPORT_SYMBOL(gpmc_prefetch_reset);
 
+void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
+{
+       reg->gpmc_status = gpmc_base + GPMC_STATUS;
+       reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
+                               GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
+       reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
+                               GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
+       reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
+                               GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
+       reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
+       reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
+       reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
+       reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
+       reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
+       reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
+       reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
+       reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
+       reg->gpmc_bch_result0 = gpmc_base + GPMC_ECC_BCH_RESULT_0;
+}
+
+int gpmc_get_client_irq(unsigned irq_config)
+{
+       int i;
+
+       if (hweight32(irq_config) > 1)
+               return 0;
+
+       for (i = 0; i < GPMC_NR_IRQ; i++)
+               if (gpmc_client_irq[i].bitmask & irq_config)
+                       return gpmc_client_irq[i].irq;
+
+       return 0;
+}
+
+static int gpmc_irq_endis(unsigned irq, bool endis)
+{
+       int i;
+       u32 regval;
+
+       for (i = 0; i < GPMC_NR_IRQ; i++)
+               if (irq == gpmc_client_irq[i].irq) {
+                       regval = gpmc_read_reg(GPMC_IRQENABLE);
+                       if (endis)
+                               regval |= gpmc_client_irq[i].bitmask;
+                       else
+                               regval &= ~gpmc_client_irq[i].bitmask;
+                       gpmc_write_reg(GPMC_IRQENABLE, regval);
+                       break;
+               }
+
+       return 0;
+}
+
+static void gpmc_irq_disable(struct irq_data *p)
+{
+       gpmc_irq_endis(p->irq, false);
+}
+
+static void gpmc_irq_enable(struct irq_data *p)
+{
+       gpmc_irq_endis(p->irq, true);
+}
+
+static void gpmc_irq_noop(struct irq_data *data) { }
+
+static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
+
+static int gpmc_setup_irq(int gpmc_irq)
+{
+       int i;
+       u32 regval;
+
+       if (!gpmc_irq)
+               return -EINVAL;
+
+       gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
+       if (IS_ERR_VALUE(gpmc_irq_start)) {
+               pr_err("irq_alloc_descs failed\n");
+               return gpmc_irq_start;
+       }
+
+       gpmc_irq_chip.name = "gpmc";
+       gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
+       gpmc_irq_chip.irq_enable = gpmc_irq_enable;
+       gpmc_irq_chip.irq_disable = gpmc_irq_disable;
+       gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
+       gpmc_irq_chip.irq_ack = gpmc_irq_noop;
+       gpmc_irq_chip.irq_mask = gpmc_irq_noop;
+       gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
+
+       gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
+       gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
+
+       for (i = 0; i < GPMC_NR_IRQ; i++) {
+               gpmc_client_irq[i].irq = gpmc_irq_start + i;
+               irq_set_chip_and_handler(gpmc_client_irq[i].irq,
+                                       &gpmc_irq_chip, handle_simple_irq);
+               set_irq_flags(gpmc_client_irq[i].irq,
+                               IRQF_VALID | IRQF_NOAUTOEN);
+       }
+
+       /* Disable interrupts */
+       gpmc_write_reg(GPMC_IRQENABLE, 0);
+
+       /* clear interrupts */
+       regval = gpmc_read_reg(GPMC_IRQSTATUS);
+       gpmc_write_reg(GPMC_IRQSTATUS, regval);
+
+       return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
+}
+
 static void __init gpmc_mem_init(void)
 {
        int cs;
@@ -711,8 +840,8 @@ static void __init gpmc_mem_init(void)
 
 static int __init gpmc_init(void)
 {
-       u32 l, irq;
-       int cs, ret = -EINVAL;
+       u32 l;
+       int ret = -EINVAL;
        int gpmc_irq;
        char *ck = NULL;
 
@@ -722,16 +851,16 @@ static int __init gpmc_init(void)
                        l = OMAP2420_GPMC_BASE;
                else
                        l = OMAP34XX_GPMC_BASE;
-               gpmc_irq = INT_34XX_GPMC_IRQ;
+               gpmc_irq = 20 + OMAP_INTC_START;
        } else if (cpu_is_omap34xx()) {
                ck = "gpmc_fck";
                l = OMAP34XX_GPMC_BASE;
-               gpmc_irq = INT_34XX_GPMC_IRQ;
+               gpmc_irq = 20 + OMAP_INTC_START;
        } else if (cpu_is_omap44xx() || soc_is_omap54xx()) {
                /* Base address and irq number are same for OMAP4/5 */
                ck = "gpmc_ck";
                l = OMAP44XX_GPMC_BASE;
-               gpmc_irq = OMAP44XX_IRQ_GPMC;
+               gpmc_irq = 20 + OMAP44XX_IRQ_GIC_START;
        }
 
        if (WARN_ON(!ck))
@@ -761,16 +890,7 @@ static int __init gpmc_init(void)
        gpmc_write_reg(GPMC_SYSCONFIG, l);
        gpmc_mem_init();
 
-       /* initalize the irq_chained */
-       irq = OMAP_GPMC_IRQ_BASE;
-       for (cs = 0; cs < GPMC_CS_NUM; cs++) {
-               irq_set_chip_and_handler(irq, &dummy_irq_chip,
-                                               handle_simple_irq);
-               set_irq_flags(irq, IRQF_VALID);
-               irq++;
-       }
-
-       ret = request_irq(gpmc_irq, gpmc_handle_irq, IRQF_SHARED, "gpmc", NULL);
+       ret = gpmc_setup_irq(gpmc_irq);
        if (ret)
                pr_err("gpmc: irq-%d could not claim: err %d\n",
                                                gpmc_irq, ret);
@@ -780,12 +900,19 @@ postcore_initcall(gpmc_init);
 
 static irqreturn_t gpmc_handle_irq(int irq, void *dev)
 {
-       u8 cs;
+       int i;
+       u32 regval;
+
+       regval = gpmc_read_reg(GPMC_IRQSTATUS);
+
+       if (!regval)
+               return IRQ_NONE;
+
+       for (i = 0; i < GPMC_NR_IRQ; i++)
+               if (regval & gpmc_client_irq[i].bitmask)
+                       generic_handle_irq(gpmc_client_irq[i].irq);
 
-       /* check cs to invoke the irq */
-       cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7;
-       if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END)
-               generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs);
+       gpmc_write_reg(GPMC_IRQSTATUS, regval);
 
        return IRQ_HANDLED;
 }
index cdd6dda..e003f2b 100644 (file)
@@ -29,7 +29,7 @@
 
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
-#include <plat/hdq1w.h>
+#include "hdq1w.h"
 
 #include "common.h"
 
index a9675d8..03ebf47 100644 (file)
 #include <linux/delay.h>
 #include <linux/gpio.h>
 #include <mach/hardware.h>
+#include <linux/platform_data/gpio-omap.h>
+
 #include <plat/mmc.h>
 #include <plat/omap-pm.h>
-#include <plat/mux.h>
 #include <plat/omap_device.h>
 
 #include "mux.h"
index a12e224..fc57e67 100644 (file)
@@ -19,7 +19,6 @@
  *
  */
 
-#include <plat/cpu.h>
 #include <plat/i2c.h>
 #include "common.h"
 #include <plat/omap_hwmod.h>
index 40373db..cf2362c 100644 (file)
 #include <asm/cputype.h>
 
 #include "common.h"
-#include <plat/cpu.h>
 
-#include <mach/id.h>
+#include "id.h"
 
+#include "soc.h"
 #include "control.h"
 
 static unsigned int omap_revision;
@@ -161,9 +161,8 @@ void __init omap2xxx_check_revision(void)
        }
 
        if (j == ARRAY_SIZE(omap_ids)) {
-               printk(KERN_ERR "Unknown OMAP device type. "
-                               "Handling it as OMAP%04x\n",
-                               omap_ids[i].type >> 16);
+               pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n",
+                      omap_ids[i].type >> 16);
                j = i;
        }
 
index be4d290..5621cc5 100644 (file)
@@ -1,5 +1,3 @@
 /*
  * arch/arm/mach-omap2/include/mach/gpio.h
  */
-
-#include <plat/gpio.h>
index 78edf9d..54492db 100644 (file)
@@ -1,5 +1,3 @@
 /*
  * arch/arm/mach-omap2/include/mach/hardware.h
  */
-
-#include <plat/hardware.h>
index 44dab77..ba5282c 100644 (file)
@@ -1,5 +1,3 @@
 /*
  * arch/arm/mach-omap2/include/mach/irqs.h
  */
-
-#include <plat/irqs.h>
diff --git a/arch/arm/mach-omap2/include/mach/smp.h b/arch/arm/mach-omap2/include/mach/smp.h
deleted file mode 100644 (file)
index 323675f..0000000
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-omap2/include/mach/smp.h
- */
-
-#include <plat/smp.h>
index 4d2d981..0d79c23 100644 (file)
@@ -33,6 +33,7 @@
 #include <plat/multi.h>
 #include <plat/dma.h>
 
+#include "soc.h"
 #include "iomap.h"
 #include "voltage.h"
 #include "powerdomain.h"
index bcd83db..3926f37 100644 (file)
@@ -23,8 +23,7 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 
-#include <mach/hardware.h>
-
+#include "soc.h"
 #include "iomap.h"
 #include "common.h"
 
@@ -49,6 +48,8 @@
 #define OMAP3_IRQ_BASE         OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
 #define INTCPS_SIR_IRQ_OFFSET  0x0040  /* omap2/3 active interrupt offset */
 #define ACTIVEIRQ_MASK         0x7f    /* omap2/3 active interrupt bits */
+#define INTCPS_NR_MIR_REGS     3
+#define INTCPS_NR_IRQS         96
 
 /*
  * OMAP2 has a number of different interrupt controllers, each interrupt
@@ -107,9 +108,8 @@ static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
        unsigned long tmp;
 
        tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
-       printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
-                        "(revision %ld.%ld) with %d interrupts\n",
-                        bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
+       pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
+               bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
 
        tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
        tmp |= 1 << 1;  /* soft reset */
index 6875be8..0d97456 100644 (file)
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/pm_runtime.h>
+
 #include <plat/mailbox.h>
-#include <mach/irqs.h>
+
+#include "soc.h"
 
 #define MAILBOX_REVISION               0x000
 #define MAILBOX_MESSAGE(m)             (0x040 + 4 * (m))
index 577cb77..7d47407 100644 (file)
 #include <linux/io.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
-#include <mach/irqs.h>
 #include <plat/dma.h>
-#include <plat/cpu.h>
-#include <plat/mcbsp.h>
 #include <plat/omap_device.h>
 #include <linux/pm_runtime.h>
 
index fb5bc6c..9e57b4a 100644 (file)
@@ -23,6 +23,7 @@
 
 #include <linux/kernel.h>
 #include <linux/err.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
index 414083b..765a2ac 100644 (file)
@@ -20,7 +20,7 @@
 #include <linux/io.h>
 
 #include <asm/cacheflush.h>
-#include <mach/omap-wakeupgen.h>
+#include "omap-wakeupgen.h"
 
 #include "common.h"
 
index 1be8bcb..df298d4 100644 (file)
@@ -14,7 +14,9 @@
 #include <linux/platform_device.h>
 
 #include <plat/iommu.h>
-#include <plat/irqs.h>
+
+#include "soc.h"
+#include "common.h"
 
 struct iommu_device {
        resource_size_t base;
@@ -29,7 +31,7 @@ static int num_iommu_devices;
 static struct iommu_device omap3_devices[] = {
        {
                .base = 0x480bd400,
-               .irq = 24,
+               .irq = 24 + OMAP_INTC_START,
                .pdata = {
                        .name = "isp",
                        .nr_tlb_entries = 8,
@@ -41,7 +43,7 @@ static struct iommu_device omap3_devices[] = {
 #if defined(CONFIG_OMAP_IOMMU_IVA2)
        {
                .base = 0x5d000000,
-               .irq = 28,
+               .irq = 28 + OMAP_INTC_START,
                .pdata = {
                        .name = "iva2",
                        .nr_tlb_entries = 32,
@@ -64,7 +66,7 @@ static struct platform_device *omap3_iommu_pdev[NR_OMAP3_IOMMU_DEVICES];
 static struct iommu_device omap4_devices[] = {
        {
                .base = OMAP4_MMU1_BASE,
-               .irq = OMAP44XX_IRQ_DUCATI_MMU,
+               .irq = 100 + OMAP44XX_IRQ_GIC_START,
                .pdata = {
                        .name = "ducati",
                        .nr_tlb_entries = 32,
@@ -75,7 +77,7 @@ static struct iommu_device omap4_devices[] = {
        },
        {
                .base = OMAP4_MMU2_BASE,
-               .irq = OMAP44XX_IRQ_TESLA_MMU,
+               .irq = 28 + OMAP44XX_IRQ_GIC_START,
                .pdata = {
                        .name = "tesla",
                        .nr_tlb_entries = 32,
index 637a1bd..ff4e6a0 100644 (file)
@@ -50,9 +50,8 @@
 #include <asm/suspend.h>
 #include <asm/hardware/cache-l2x0.h>
 
-#include <plat/omap44xx.h>
-
 #include "common.h"
+#include "omap44xx.h"
 #include "omap4-sar-layout.h"
 #include "pm.h"
 #include "prcm_mpu44xx.h"
index d9ae4a5..a004cb9 100644 (file)
@@ -19,7 +19,7 @@
 #include <asm/memblock.h>
 
 #include <plat/omap-secure.h>
-#include <mach/omap-secure.h>
+#include "omap-secure.h"
 
 static phys_addr_t omap_secure_memblock_base;
 
index 9a35adf..06d8bc3 100644 (file)
 #include <asm/hardware/gic.h>
 #include <asm/smp_scu.h>
 
-#include <mach/hardware.h>
-#include <mach/omap-secure.h>
-#include <mach/omap-wakeupgen.h>
+#include "omap-secure.h"
+#include "omap-wakeupgen.h"
 #include <asm/cputype.h>
 
+#include "soc.h"
 #include "iomap.h"
 #include "common.h"
 #include "clockdomain.h"
index c4bee21..5d3b4f4 100644 (file)
 
 #include <asm/hardware/gic.h>
 
-#include <mach/omap-wakeupgen.h>
-#include <mach/omap-secure.h>
+#include "omap-wakeupgen.h"
+#include "omap-secure.h"
 
+#include "soc.h"
 #include "omap4-sar-layout.h"
 #include "common.h"
 
similarity index 98%
rename from arch/arm/plat-omap/include/plat/omap24xx.h
rename to arch/arm/mach-omap2/omap24xx.h
index 92df9e2..641a2c8 100644 (file)
@@ -1,6 +1,4 @@
 /*
- * arch/arm/plat-omap/include/mach/omap24xx.h
- *
  * This file contains the processor specific definitions
  * of the TI OMAP24XX.
  *
similarity index 98%
rename from arch/arm/plat-omap/include/plat/omap34xx.h
rename to arch/arm/mach-omap2/omap34xx.h
index 0d818ac..c0d1b4b 100644 (file)
@@ -1,6 +1,4 @@
 /*
- * arch/arm/plat-omap/include/mach/omap34xx.h
- *
  * This file contains the processor specific definitions of the TI OMAP34XX.
  *
  * Copyright (C) 2007 Texas Instruments.
index c29dee9..9fc8655 100644 (file)
 #include <linux/io.h>
 #include <linux/platform_device.h>
 #include <linux/memblock.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/export.h>
 
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
 #include <asm/memblock.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
 
-#include <plat/irqs.h>
 #include <plat/sram.h>
 #include <plat/omap-secure.h>
 #include <plat/mmc.h>
 
-#include <mach/hardware.h>
-#include <mach/omap-wakeupgen.h>
+#include "omap-wakeupgen.h"
 
+#include "soc.h"
 #include "common.h"
 #include "hsmmc.h"
 #include "omap4-sar-layout.h"
-#include <linux/export.h>
 
 #ifdef CONFIG_CACHE_L2X0
 static void __iomem *l2cache_base;
similarity index 87%
rename from arch/arm/plat-omap/include/plat/omap4-keypad.h
rename to arch/arm/mach-omap2/omap4-keypad.h
index 8ad0a37..20de0d5 100644 (file)
@@ -1,6 +1,8 @@
 #ifndef ARCH_ARM_PLAT_OMAP4_KEYPAD_H
 #define ARCH_ARM_PLAT_OMAP4_KEYPAD_H
 
+struct omap_board_data;
+
 extern int omap4_keyboard_init(struct omap4_keypad_platform_data *,
                                struct omap_board_data *);
 #endif
similarity index 97%
rename from arch/arm/plat-omap/include/plat/omap44xx.h
rename to arch/arm/mach-omap2/omap44xx.h
index c0d478e..43b927b 100644 (file)
 #define IRQ_SIR_IRQ                    0x0040
 #define OMAP44XX_GIC_DIST_BASE         0x48241000
 #define OMAP44XX_GIC_CPU_BASE          0x48240100
+#define OMAP44XX_IRQ_GIC_START         32
 #define OMAP44XX_SCU_BASE              0x48240000
 #define OMAP44XX_LOCAL_TWD_BASE                0x48240600
 #define OMAP44XX_L2CACHE_BASE          0x48242000
 #define OMAP44XX_WKUPGEN_BASE          0x48281000
 #define OMAP44XX_MCPDM_BASE            0x40132000
-#define OMAP44XX_MCPDM_L3_BASE         0x49032000
 #define OMAP44XX_SAR_RAM_BASE          0x4a326000
 
 #define OMAP44XX_MAILBOX_BASE          (L4_44XX_BASE + 0xF4000)
index 37afbd1..3615e0d 100644 (file)
 #include <linux/slab.h>
 #include <linux/bootmem.h>
 
-#include "common.h"
-#include <plat/cpu.h>
-#include "clockdomain.h"
-#include "powerdomain.h"
 #include <plat/clock.h>
 #include <plat/omap_hwmod.h>
 #include <plat/prcm.h>
 
+#include "soc.h"
+#include "common.h"
+#include "clockdomain.h"
+#include "powerdomain.h"
 #include "cm2xxx_3xxx.h"
 #include "cminst44xx.h"
 #include "prm2xxx_3xxx.h"
@@ -1438,8 +1438,8 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
  * Return the bit position of the reset line that match the
  * input name. Return -ENOENT if not found.
  */
-static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name,
-                           struct omap_hwmod_rst_info *ohri)
+static int _lookup_hardreset(struct omap_hwmod *oh, const char *name,
+                            struct omap_hwmod_rst_info *ohri)
 {
        int i;
 
@@ -1475,7 +1475,7 @@ static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name,
 static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
 {
        struct omap_hwmod_rst_info ohri;
-       u8 ret = -EINVAL;
+       int ret = -EINVAL;
 
        if (!oh)
                return -EINVAL;
@@ -1484,7 +1484,7 @@ static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
                return -ENOSYS;
 
        ret = _lookup_hardreset(oh, name, &ohri);
-       if (IS_ERR_VALUE(ret))
+       if (ret < 0)
                return ret;
 
        ret = soc_ops.assert_hardreset(oh, &ohri);
@@ -1542,7 +1542,7 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
 static int _read_hardreset(struct omap_hwmod *oh, const char *name)
 {
        struct omap_hwmod_rst_info ohri;
-       u8 ret = -EINVAL;
+       int ret = -EINVAL;
 
        if (!oh)
                return -EINVAL;
@@ -1551,7 +1551,7 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name)
                return -ENOSYS;
 
        ret = _lookup_hardreset(oh, name, &ohri);
-       if (IS_ERR_VALUE(ret))
+       if (ret < 0)
                return ret;
 
        return soc_ops.is_hardreset_asserted(oh, &ohri);
@@ -1641,8 +1641,8 @@ static int _ocp_softreset(struct omap_hwmod *oh)
 
        /* clocks must be on for this operation */
        if (oh->_state != _HWMOD_STATE_ENABLED) {
-               pr_warning("omap_hwmod: %s: reset can only be entered from "
-                          "enabled state\n", oh->name);
+               pr_warn("omap_hwmod: %s: reset can only be entered from enabled state\n",
+                       oh->name);
                return -EINVAL;
        }
 
index 50cfab6..10575a1 100644 (file)
  * XXX handle crossbar/shared link difference for L3?
  * XXX these should be marked initdata for multi-OMAP kernels
  */
+#include <linux/platform_data/spi-omap2-mcspi.h>
+
 #include <plat/omap_hwmod.h>
-#include <mach/irqs.h>
-#include <plat/cpu.h>
 #include <plat/dma.h>
 #include <plat/serial.h>
 #include <plat/i2c.h>
-#include <plat/gpio.h>
-#include <plat/mcspi.h>
 #include <plat/dmtimer.h>
-#include <plat/l3_2xxx.h>
-#include <plat/l4_2xxx.h>
+#include "l3_2xxx.h"
+#include "l4_2xxx.h"
 #include <plat/mmc.h>
 
 #include "omap_hwmod_common_data.h"
@@ -162,9 +160,9 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
 
 /* mailbox */
 static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
-       { .name = "dsp", .irq = 26 },
-       { .name = "iva", .irq = 34 },
-       { .irq = -1 }
+       { .name = "dsp", .irq = 26 + OMAP_INTC_START, },
+       { .name = "iva", .irq = 34 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod omap2420_mailbox_hwmod = {
@@ -199,9 +197,9 @@ static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
 
 /* mcbsp1 */
 static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
-       { .name = "tx", .irq = 59 },
-       { .name = "rx", .irq = 60 },
-       { .irq = -1 }
+       { .name = "tx", .irq = 59 + OMAP_INTC_START, },
+       { .name = "rx", .irq = 60 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
@@ -225,9 +223,9 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
 
 /* mcbsp2 */
 static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
-       { .name = "tx", .irq = 62 },
-       { .name = "rx", .irq = 63 },
-       { .irq = -1 }
+       { .name = "tx", .irq = 62 + OMAP_INTC_START, },
+       { .name = "rx", .irq = 63 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
@@ -265,8 +263,8 @@ static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
 
 /* msdi1 */
 static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = {
-       { .irq = 83 },
-       { .irq = -1 }
+       { .irq = 83 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = {
index 58b5bc1..60de70f 100644 (file)
  * XXX handle crossbar/shared link difference for L3?
  * XXX these should be marked initdata for multi-OMAP kernels
  */
+#include <linux/platform_data/asoc-ti-mcbsp.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+
 #include <plat/omap_hwmod.h>
-#include <mach/irqs.h>
-#include <plat/cpu.h>
 #include <plat/dma.h>
 #include <plat/serial.h>
 #include <plat/i2c.h>
-#include <plat/gpio.h>
-#include <plat/mcbsp.h>
-#include <plat/mcspi.h>
 #include <plat/dmtimer.h>
 #include <plat/mmc.h>
-#include <plat/l3_2xxx.h>
+#include "l3_2xxx.h"
 
+#include "soc.h"
 #include "omap_hwmod_common_data.h"
-
 #include "prm-regbits-24xx.h"
 #include "cm-regbits-24xx.h"
 #include "wd_timer.h"
@@ -133,8 +131,8 @@ static struct omap_hwmod omap2430_i2c2_hwmod = {
 
 /* gpio5 */
 static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
-       { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
-       { .irq = -1 }
+       { .irq = 33 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK5 */
+       { .irq = -1 },
 };
 
 static struct omap_hwmod omap2430_gpio5_hwmod = {
@@ -173,8 +171,8 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
 
 /* mailbox */
 static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
-       { .irq = 26 },
-       { .irq = -1 }
+       { .irq = 26 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod omap2430_mailbox_hwmod = {
@@ -195,8 +193,8 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
 
 /* mcspi3 */
 static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
-       { .irq = 91 },
-       { .irq = -1 }
+       { .irq = 91 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
@@ -250,9 +248,9 @@ static struct omap_hwmod_class usbotg_class = {
 /* usb_otg_hs */
 static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
 
-       { .name = "mc", .irq = 92 },
-       { .name = "dma", .irq = 93 },
-       { .irq = -1 }
+       { .name = "mc", .irq = 92 + OMAP_INTC_START, },
+       { .name = "dma", .irq = 93 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod omap2430_usbhsotg_hwmod = {
@@ -303,11 +301,11 @@ static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
 
 /* mcbsp1 */
 static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
-       { .name = "tx",         .irq = 59 },
-       { .name = "rx",         .irq = 60 },
-       { .name = "ovr",        .irq = 61 },
-       { .name = "common",     .irq = 64 },
-       { .irq = -1 }
+       { .name = "tx",         .irq = 59 + OMAP_INTC_START, },
+       { .name = "rx",         .irq = 60 + OMAP_INTC_START, },
+       { .name = "ovr",        .irq = 61 + OMAP_INTC_START, },
+       { .name = "common",     .irq = 64 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod omap2430_mcbsp1_hwmod = {
@@ -331,10 +329,10 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
 
 /* mcbsp2 */
 static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
-       { .name = "tx",         .irq = 62 },
-       { .name = "rx",         .irq = 63 },
-       { .name = "common",     .irq = 16 },
-       { .irq = -1 }
+       { .name = "tx",         .irq = 62 + OMAP_INTC_START, },
+       { .name = "rx",         .irq = 63 + OMAP_INTC_START, },
+       { .name = "common",     .irq = 16 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod omap2430_mcbsp2_hwmod = {
@@ -358,10 +356,10 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
 
 /* mcbsp3 */
 static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
-       { .name = "tx",         .irq = 89 },
-       { .name = "rx",         .irq = 90 },
-       { .name = "common",     .irq = 17 },
-       { .irq = -1 }
+       { .name = "tx",         .irq = 89 + OMAP_INTC_START, },
+       { .name = "rx",         .irq = 90 + OMAP_INTC_START, },
+       { .name = "common",     .irq = 17 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod omap2430_mcbsp3_hwmod = {
@@ -385,10 +383,10 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
 
 /* mcbsp4 */
 static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
-       { .name = "tx",         .irq = 54 },
-       { .name = "rx",         .irq = 55 },
-       { .name = "common",     .irq = 18 },
-       { .irq = -1 }
+       { .name = "tx",         .irq = 54 + OMAP_INTC_START, },
+       { .name = "rx",         .irq = 55 + OMAP_INTC_START, },
+       { .name = "common",     .irq = 18 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
@@ -418,10 +416,10 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = {
 
 /* mcbsp5 */
 static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
-       { .name = "tx",         .irq = 81 },
-       { .name = "rx",         .irq = 82 },
-       { .name = "common",     .irq = 19 },
-       { .irq = -1 }
+       { .name = "tx",         .irq = 81 + OMAP_INTC_START, },
+       { .name = "rx",         .irq = 82 + OMAP_INTC_START, },
+       { .name = "common",     .irq = 19 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
@@ -468,8 +466,8 @@ static struct omap_hwmod_class omap2430_mmc_class = {
 
 /* MMC/SD/SDIO1 */
 static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
-       { .irq = 83 },
-       { .irq = -1 }
+       { .irq = 83 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
@@ -509,8 +507,8 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
 
 /* MMC/SD/SDIO2 */
 static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
-       { .irq = 86 },
-       { .irq = -1 }
+       { .irq = 86 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
index 102d76e..8851bbb 100644 (file)
@@ -13,9 +13,7 @@
 #include <plat/serial.h>
 #include <plat/dma.h>
 #include <plat/common.h>
-#include <plat/hdq1w.h>
-
-#include <mach/irqs.h>
+#include "hdq1w.h"
 
 #include "omap_hwmod_common_data.h"
 
@@ -182,126 +180,126 @@ struct omap_hwmod_class iva_hwmod_class = {
 /* Common MPU IRQ line data */
 
 struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
-       { .irq = 37, },
-       { .irq = -1 }
+       { .irq = 37 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
-       { .irq = 38, },
-       { .irq = -1 }
+       { .irq = 38 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
-       { .irq = 39, },
-       { .irq = -1 }
+       { .irq = 39 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
-       { .irq = 40, },
-       { .irq = -1 }
+       { .irq = 40 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
-       { .irq = 41, },
-       { .irq = -1 }
+       { .irq = 41 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
-       { .irq = 42, },
-       { .irq = -1 }
+       { .irq = 42 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
-       { .irq = 43, },
-       { .irq = -1 }
+       { .irq = 43 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
-       { .irq = 44, },
-       { .irq = -1 }
+       { .irq = 44 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
-       { .irq = 45, },
-       { .irq = -1 }
+       { .irq = 45 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
-       { .irq = 46, },
-       { .irq = -1 }
+       { .irq = 46 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
-       { .irq = 47, },
-       { .irq = -1 }
+       { .irq = 47 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
-       { .irq = INT_24XX_UART1_IRQ, },
-       { .irq = -1 }
+       { .irq = 72 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
-       { .irq = INT_24XX_UART2_IRQ, },
-       { .irq = -1 }
+       { .irq = 73 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
-       { .irq = INT_24XX_UART3_IRQ, },
-       { .irq = -1 }
+       { .irq = 74 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
-       { .irq = 25 },
-       { .irq = -1 }
+       { .irq = 25 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
-       { .irq = INT_24XX_I2C1_IRQ, },
-       { .irq = -1 }
+       { .irq = 56 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
-       { .irq = INT_24XX_I2C2_IRQ, },
-       { .irq = -1 }
+       { .irq = 57 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
-       { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
-       { .irq = -1 }
+       { .irq = 29 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK1 */
+       { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
-       { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
-       { .irq = -1 }
+       { .irq = 30 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK2 */
+       { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
-       { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
-       { .irq = -1 }
+       { .irq = 31 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK3 */
+       { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
-       { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
-       { .irq = -1 }
+       { .irq = 32 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK4 */
+       { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
-       { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
-       { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
-       { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
-       { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
-       { .irq = -1 }
+       { .name = "0", .irq = 12 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ0 */
+       { .name = "1", .irq = 13 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ1 */
+       { .name = "2", .irq = 14 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ2 */
+       { .name = "3", .irq = 15 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ3 */
+       { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
-       { .irq = 65 },
-       { .irq = -1 }
+       { .irq = 65 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
-       { .irq = 66 },
-       { .irq = -1 }
+       { .irq = 66 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = {
@@ -320,7 +318,7 @@ struct omap_hwmod_class omap2_hdq1w_class = {
 };
 
 struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = {
-       { .irq = 58, },
-       { .irq = -1 }
+       { .irq = 58 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
index 5178e40..f853a0b 100644 (file)
@@ -15,8 +15,8 @@
 
 #include <plat/omap_hwmod.h>
 #include <plat/serial.h>
-#include <plat/l3_2xxx.h>
-#include <plat/l4_2xxx.h>
+#include "l3_2xxx.h"
+#include "l4_2xxx.h"
 
 #include "omap_hwmod_common_data.h"
 
index afad69c..feeb401 100644 (file)
  */
 #include <plat/omap_hwmod.h>
 #include <plat/serial.h>
-#include <plat/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
 #include <plat/dma.h>
 #include <plat/dmtimer.h>
-#include <plat/mcspi.h>
-
-#include <mach/irqs.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
 #include "omap_hwmod_common_data.h"
 #include "cm-regbits-24xx.h"
@@ -23,8 +21,8 @@
 #include "wd_timer.h"
 
 struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
-       { .irq = 48, },
-       { .irq = -1 }
+       { .irq = 48 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
index ce7e606..94b38af 100644 (file)
  * XXX these should be marked initdata for multi-OMAP kernels
  */
 #include <linux/power/smartreflex.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <plat/omap_hwmod.h>
-#include <mach/irqs.h>
-#include <plat/cpu.h>
 #include <plat/dma.h>
 #include <plat/serial.h>
-#include <plat/l3_3xxx.h>
-#include <plat/l4_3xxx.h>
+#include "l3_3xxx.h"
+#include "l4_3xxx.h"
 #include <plat/i2c.h>
-#include <plat/gpio.h>
 #include <plat/mmc.h>
-#include <plat/mcbsp.h>
-#include <plat/mcspi.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 #include <plat/dmtimer.h>
 
+#include "am35xx.h"
+
+#include "soc.h"
 #include "omap_hwmod_common_data.h"
 #include "prm-regbits-34xx.h"
 #include "cm-regbits-34xx.h"
 #include "wd_timer.h"
-#include <mach/am35xx.h>
 
 /*
  * OMAP3xxx hardware module integration data
@@ -51,9 +51,9 @@
 
 /* L3 */
 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
-       { .irq = INT_34XX_L3_DBG_IRQ },
-       { .irq = INT_34XX_L3_APP_IRQ },
-       { .irq = -1 }
+       { .irq = 9 + OMAP_INTC_START, },
+       { .irq = 10 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
@@ -364,8 +364,8 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
 
 /* timer12 */
 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
-       { .irq = 95, },
-       { .irq = -1 }
+       { .irq = 95 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod omap3xxx_timer12_hwmod = {
@@ -499,8 +499,8 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
 
 /* UART4 */
 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
-       { .irq = INT_36XX_UART4_IRQ, },
-       { .irq = -1 }
+       { .irq = 80 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
@@ -527,8 +527,8 @@ static struct omap_hwmod omap36xx_uart4_hwmod = {
 };
 
 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
-       { .irq = INT_35XX_UART4_IRQ, },
-       { .irq = -1 }
+       { .irq = 84 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
@@ -683,8 +683,8 @@ static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
 };
 
 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
-       { .irq = 25 },
-       { .irq = -1 }
+       { .irq = 25 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 /* dss_dsi1 */
@@ -813,8 +813,8 @@ static struct omap_i2c_dev_attr i2c3_dev_attr = {
 };
 
 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
-       { .irq = INT_34XX_I2C3_IRQ, },
-       { .irq = -1 }
+       { .irq = 61 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
@@ -972,8 +972,8 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = {
 
 /* gpio5 */
 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
-       { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
-       { .irq = -1 }
+       { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */
+       { .irq = -1 },
 };
 
 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
@@ -1002,8 +1002,8 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
 
 /* gpio6 */
 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
-       { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
-       { .irq = -1 }
+       { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */
+       { .irq = -1 },
 };
 
 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
@@ -1107,10 +1107,10 @@ static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
 
 /* mcbsp1 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
-       { .name = "common", .irq = 16 },
-       { .name = "tx", .irq = 59 },
-       { .name = "rx", .irq = 60 },
-       { .irq = -1 }
+       { .name = "common", .irq = 16 + OMAP_INTC_START, },
+       { .name = "tx", .irq = 59 + OMAP_INTC_START, },
+       { .name = "rx", .irq = 60 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
@@ -1134,10 +1134,10 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
 
 /* mcbsp2 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
-       { .name = "common", .irq = 17 },
-       { .name = "tx", .irq = 62 },
-       { .name = "rx", .irq = 63 },
-       { .irq = -1 }
+       { .name = "common", .irq = 17 + OMAP_INTC_START, },
+       { .name = "tx", .irq = 62 + OMAP_INTC_START, },
+       { .name = "rx", .irq = 63 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
@@ -1166,10 +1166,10 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
 
 /* mcbsp3 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
-       { .name = "common", .irq = 22 },
-       { .name = "tx", .irq = 89 },
-       { .name = "rx", .irq = 90 },
-       { .irq = -1 }
+       { .name = "common", .irq = 22 + OMAP_INTC_START, },
+       { .name = "tx", .irq = 89 + OMAP_INTC_START, },
+       { .name = "rx", .irq = 90 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
@@ -1198,10 +1198,10 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
 
 /* mcbsp4 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
-       { .name = "common", .irq = 23 },
-       { .name = "tx", .irq = 54 },
-       { .name = "rx", .irq = 55 },
-       { .irq = -1 }
+       { .name = "common", .irq = 23 + OMAP_INTC_START, },
+       { .name = "tx", .irq = 54 + OMAP_INTC_START, },
+       { .name = "rx", .irq = 55 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
@@ -1231,10 +1231,10 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
 
 /* mcbsp5 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
-       { .name = "common", .irq = 27 },
-       { .name = "tx", .irq = 81 },
-       { .name = "rx", .irq = 82 },
-       { .irq = -1 }
+       { .name = "common", .irq = 27 + OMAP_INTC_START, },
+       { .name = "tx", .irq = 81 + OMAP_INTC_START, },
+       { .name = "rx", .irq = 82 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
@@ -1276,8 +1276,8 @@ static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
 
 /* mcbsp2_sidetone */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
-       { .name = "irq", .irq = 4 },
-       { .irq = -1 }
+       { .name = "irq", .irq = 4 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
@@ -1298,8 +1298,8 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
 
 /* mcbsp3_sidetone */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
-       { .name = "irq", .irq = 5 },
-       { .irq = -1 }
+       { .name = "irq", .irq = 5 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
@@ -1361,8 +1361,8 @@ static struct omap_smartreflex_dev_attr sr1_dev_attr = {
 };
 
 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
-       { .irq = 18 },
-       { .irq = -1 }
+       { .irq = 18 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod omap34xx_sr1_hwmod = {
@@ -1406,8 +1406,8 @@ static struct omap_smartreflex_dev_attr sr2_dev_attr = {
 };
 
 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
-       { .irq = 19 },
-       { .irq = -1 }
+       { .irq = 19 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod omap34xx_sr2_hwmod = {
@@ -1467,8 +1467,8 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
 };
 
 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
-       { .irq = 26 },
-       { .irq = -1 }
+       { .irq = 26 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
@@ -1558,8 +1558,8 @@ static struct omap_hwmod omap34xx_mcspi2 = {
 
 /* mcspi3 */
 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
-       { .name = "irq", .irq = 91 }, /* 91 */
-       { .irq = -1 }
+       { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */
+       { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
@@ -1594,8 +1594,8 @@ static struct omap_hwmod omap34xx_mcspi3 = {
 
 /* mcspi4 */
 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
-       { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
-       { .irq = -1 }
+       { .name = "irq", .irq = 48 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
@@ -1647,9 +1647,9 @@ static struct omap_hwmod_class usbotg_class = {
 /* usb_otg_hs */
 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
 
-       { .name = "mc", .irq = 92 },
-       { .name = "dma", .irq = 93 },
-       { .irq = -1 }
+       { .name = "mc", .irq = 92 + OMAP_INTC_START, },
+       { .name = "dma", .irq = 93 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
@@ -1679,8 +1679,8 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
 
 /* usb_otg_hs */
 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
-       { .name = "mc", .irq = 71 },
-       { .irq = -1 }
+       { .name = "mc", .irq = 71 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod_class am35xx_usbotg_class = {
@@ -1715,8 +1715,8 @@ static struct omap_hwmod_class omap34xx_mmc_class = {
 /* MMC/SD/SDIO1 */
 
 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
-       { .irq = 83, },
-       { .irq = -1 }
+       { .irq = 83 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
@@ -1782,8 +1782,8 @@ static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
 /* MMC/SD/SDIO2 */
 
 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
-       { .irq = INT_24XX_MMC2_IRQ, },
-       { .irq = -1 }
+       { .irq = 86 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
@@ -1843,8 +1843,8 @@ static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
 /* MMC/SD/SDIO3 */
 
 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
-       { .irq = 94, },
-       { .irq = -1 }
+       { .irq = 94 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
@@ -1902,9 +1902,9 @@ static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
 };
 
 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
-       { .name = "ohci-irq", .irq = 76 },
-       { .name = "ehci-irq", .irq = 77 },
-       { .irq = -1 }
+       { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
+       { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
@@ -1996,8 +1996,8 @@ static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
 };
 
 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
-       { .name = "tll-irq", .irq = 78 },
-       { .irq = -1 }
+       { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
@@ -3223,11 +3223,11 @@ static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
 };
 
 static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
-       { .name = "rxthresh",   .irq = INT_35XX_EMAC_C0_RXTHRESH_IRQ },
-       { .name = "rx_pulse",   .irq = INT_35XX_EMAC_C0_RX_PULSE_IRQ },
-       { .name = "tx_pulse",   .irq = INT_35XX_EMAC_C0_TX_PULSE_IRQ },
-       { .name = "misc_pulse", .irq = INT_35XX_EMAC_C0_MISC_PULSE_IRQ },
-       { .irq = -1 }
+       { .name = "rxthresh",   .irq = 67 + OMAP_INTC_START, },
+       { .name = "rx_pulse",   .irq = 68 + OMAP_INTC_START, },
+       { .name = "tx_pulse",   .irq = 69 + OMAP_INTC_START },
+       { .name = "misc_pulse", .irq = 70 + OMAP_INTC_START },
+       { .irq = -1 },
 };
 
 static struct omap_hwmod_class am35xx_emac_class = {
index 64b564f..c7dcb60 100644 (file)
  */
 
 #include <linux/io.h>
+#include <linux/platform_data/gpio-omap.h>
 #include <linux/power/smartreflex.h>
 
 #include <plat/omap_hwmod.h>
-#include <plat/cpu.h>
 #include <plat/i2c.h>
-#include <plat/gpio.h>
 #include <plat/dma.h>
-#include <plat/mcspi.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 #include <plat/mmc.h>
 #include <plat/dmtimer.h>
 #include <plat/common.h>
index e7e8eea..dddb677 100644 (file)
@@ -16,6 +16,7 @@
 
 #include <plat/omap_hwmod.h>
 
+#include "common.h"
 #include "display.h"
 
 /* Common address space across OMAP2xxx */
index d15225f..f447e02 100644 (file)
@@ -28,6 +28,7 @@
 #include <linux/kernel.h>
 #include <linux/slab.h>
 
+#include "soc.h"
 #include "omap_l3_noc.h"
 
 /*
@@ -190,7 +191,7 @@ static int __devinit omap4_l3_probe(struct platform_device *pdev)
                        IRQF_DISABLED, "l3-dbg-irq", l3);
        if (ret) {
                pr_crit("L3: request_irq failed to register for 0x%x\n",
-                                               OMAP44XX_IRQ_L3_DBG);
+                                               9 + OMAP44XX_IRQ_GIC_START);
                goto err3;
        }
 
@@ -200,7 +201,7 @@ static int __devinit omap4_l3_probe(struct platform_device *pdev)
                        IRQF_DISABLED, "l3-app-irq", l3);
        if (ret) {
                pr_crit("L3: request_irq failed to register for 0x%x\n",
-                                               OMAP44XX_IRQ_L3_APP);
+                                               10 + OMAP44XX_IRQ_GIC_START);
                goto err4;
        }
 
index 874aecc..d992db8 100644 (file)
@@ -29,6 +29,8 @@
 #include <linux/usb.h>
 
 #include <plat/usb.h>
+
+#include "soc.h"
 #include "control.h"
 
 void am35x_musb_reset(void)
index d8f6dbf..45ad7f7 100644 (file)
@@ -64,25 +64,22 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def,
                }
                oh = omap_hwmod_lookup(opp_def->hwmod_name);
                if (!oh || !oh->od) {
-                       pr_debug("%s: no hwmod or odev for %s, [%d] "
-                               "cannot add OPPs.\n", __func__,
-                               opp_def->hwmod_name, i);
+                       pr_debug("%s: no hwmod or odev for %s, [%d] cannot add OPPs.\n",
+                                __func__, opp_def->hwmod_name, i);
                        continue;
                }
                dev = &oh->od->pdev->dev;
 
                r = opp_add(dev, opp_def->freq, opp_def->u_volt);
                if (r) {
-                       dev_err(dev, "%s: add OPP %ld failed for %s [%d] "
-                               "result=%d\n",
-                              __func__, opp_def->freq,
-                              opp_def->hwmod_name, i, r);
+                       dev_err(dev, "%s: add OPP %ld failed for %s [%d] result=%d\n",
+                               __func__, opp_def->freq,
+                               opp_def->hwmod_name, i, r);
                } else {
                        if (!opp_def->default_available)
                                r = opp_disable(dev, opp_def->freq);
                        if (r)
-                               dev_err(dev, "%s: disable %ld failed for %s "
-                                       "[%d] result=%d\n",
+                               dev_err(dev, "%s: disable %ld failed for %s [%d] result=%d\n",
                                        __func__, opp_def->freq,
                                        opp_def->hwmod_name, i, r);
                }
index 5037e76..a9e8cf2 100644 (file)
@@ -28,7 +28,7 @@
  *     http://repository.maemo.org/pool/diablo/free/k/kernel-source-diablo/
  */
 
-#include <plat/hardware.h>
+#include <linux/kernel.h>
 
 #include "opp2xxx.h"
 #include "sdrc.h"
index 750805c..0e75ec3 100644 (file)
@@ -26,7 +26,7 @@
  * This is technically part of the OMAP2xxx clock code.
  */
 
-#include <plat/hardware.h>
+#include <linux/kernel.h>
 
 #include "opp2xxx.h"
 #include "sdrc.h"
index d95f3f9..75cef5f 100644 (file)
@@ -19,8 +19,6 @@
  */
 #include <linux/module.h>
 
-#include <plat/cpu.h>
-
 #include "control.h"
 #include "omap_opp_data.h"
 #include "pm.h"
index c95415d..a9fd6d5 100644 (file)
@@ -20,8 +20,7 @@
  */
 #include <linux/module.h>
 
-#include <plat/cpu.h>
-
+#include "soc.h"
 #include "control.h"
 #include "omap_opp_data.h"
 #include "pm.h"
index 814bcd9..3e1345f 100644 (file)
@@ -28,7 +28,6 @@
 #include <linux/slab.h>
 
 #include <plat/clock.h>
-#include <plat/board.h>
 #include "powerdomain.h"
 #include "clockdomain.h"
 #include <plat/dmtimer.h>
index 9cb5ced..939bd6f 100644 (file)
@@ -203,8 +203,8 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
        bootup_volt = opp_get_voltage(opp);
        rcu_read_unlock();
        if (!bootup_volt) {
-               pr_err("%s: unable to find voltage corresponding "
-                       "to the bootup OPP for vdd_%s\n", __func__, vdd_name);
+               pr_err("%s: unable to find voltage corresponding to the bootup OPP for vdd_%s\n",
+                      __func__, vdd_name);
                goto exit;
        }
 
index 2edeffc..8af6cd6 100644 (file)
@@ -29,6 +29,7 @@
 #include <linux/irq.h>
 #include <linux/time.h>
 #include <linux/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
@@ -38,9 +39,6 @@
 #include <plat/clock.h>
 #include <plat/sram.h>
 #include <plat/dma.h>
-#include <plat/board.h>
-
-#include <mach/irqs.h>
 
 #include "common.h"
 #include "prm2xxx_3xxx.h"
@@ -352,16 +350,6 @@ int __init omap2_pm_init(void)
 
        prcm_setup_regs();
 
-       /* Hack to prevent MPU retention when STI console is enabled. */
-       {
-               const struct omap_sti_console_config *sti;
-
-               sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
-                                     struct omap_sti_console_config);
-               if (sti != NULL && sti->enable)
-                       sti_console_enabled = 1;
-       }
-
        /*
         * We copy the assembler sleep/wakeup routines to SRAM.
         * These routines need to be in SRAM as that's the only
index 05bd8f0..ba670db 100644 (file)
@@ -28,6 +28,8 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
+#include <linux/platform_data/gpio-omap.h>
+
 #include <trace/events/power.h>
 
 #include <asm/suspend.h>
@@ -389,9 +391,8 @@ restore:
        list_for_each_entry(pwrst, &pwrst_list, node) {
                state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
                if (state > pwrst->next_state) {
-                       pr_info("Powerdomain (%s) didn't enter "
-                               "target state %d\n",
-                              pwrst->pwrdm->name, pwrst->next_state);
+                       pr_info("Powerdomain (%s) didn't enter target state %d\n",
+                               pwrst->pwrdm->name, pwrst->next_state);
                        ret = -1;
                }
                omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
@@ -731,8 +732,7 @@ int __init omap3_pm_init(void)
                omap3_secure_ram_storage =
                        kmalloc(0x803F, GFP_KERNEL);
                if (!omap3_secure_ram_storage)
-                       pr_err("Memory allocation failed when "
-                              "allocating for secure sram context\n");
+                       pr_err("Memory allocation failed when allocating for secure sram context\n");
 
                local_irq_disable();
                local_fiq_disable();
index ea24174..04922d1 100644 (file)
@@ -69,9 +69,8 @@ static int omap4_pm_suspend(void)
        list_for_each_entry(pwrst, &pwrst_list, node) {
                state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
                if (state > pwrst->next_state) {
-                       pr_info("Powerdomain (%s) didn't enter "
-                              "target state %d\n",
-                              pwrst->pwrdm->name, pwrst->next_state);
+                       pr_info("Powerdomain (%s) didn't enter target state %d\n",
+                               pwrst->pwrdm->name, pwrst->next_state);
                        ret = -1;
                }
                omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
@@ -189,8 +188,7 @@ int __init omap4_pm_init(void)
        ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
        ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
        if (ret) {
-               pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 "
-                               "wakeup dependency\n");
+               pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n");
                goto err2;
        }
 
index 69b36e1..1678a32 100644 (file)
 #include "prm44xx.h"
 
 #include <asm/cpu.h>
-#include <plat/cpu.h>
+
+#include <plat/prcm.h>
+
 #include "powerdomain.h"
 #include "clockdomain.h"
-#include <plat/prcm.h>
 
+#include "soc.h"
 #include "pm.h"
 
 #define PWRDM_TRACE_STATES_FLAG        (1<<31)
@@ -339,8 +341,8 @@ int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
        if (!pwrdm || !clkdm)
                return -EINVAL;
 
-       pr_debug("powerdomain: associating clockdomain %s with powerdomain "
-                "%s\n", clkdm->name, pwrdm->name);
+       pr_debug("powerdomain: %s: associating clockdomain %s\n",
+                pwrdm->name, clkdm->name);
 
        for (i = 0; i < PWRDM_MAX_CLKDMS; i++) {
                if (!pwrdm->pwrdm_clkdms[i])
@@ -354,8 +356,8 @@ int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
        }
 
        if (i == PWRDM_MAX_CLKDMS) {
-               pr_debug("powerdomain: increase PWRDM_MAX_CLKDMS for "
-                        "pwrdm %s clkdm %s\n", pwrdm->name, clkdm->name);
+               pr_debug("powerdomain: %s: increase PWRDM_MAX_CLKDMS for clkdm %s\n",
+                        pwrdm->name, clkdm->name);
                WARN_ON(1);
                ret = -ENOMEM;
                goto pac_exit;
@@ -387,16 +389,16 @@ int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
        if (!pwrdm || !clkdm)
                return -EINVAL;
 
-       pr_debug("powerdomain: dissociating clockdomain %s from powerdomain "
-                "%s\n", clkdm->name, pwrdm->name);
+       pr_debug("powerdomain: %s: dissociating clockdomain %s\n",
+                pwrdm->name, clkdm->name);
 
        for (i = 0; i < PWRDM_MAX_CLKDMS; i++)
                if (pwrdm->pwrdm_clkdms[i] == clkdm)
                        break;
 
        if (i == PWRDM_MAX_CLKDMS) {
-               pr_debug("powerdomain: clkdm %s not associated with pwrdm "
-                        "%s ?!\n", clkdm->name, pwrdm->name);
+               pr_debug("powerdomain: %s: clkdm %s not associated?!\n",
+                        pwrdm->name, clkdm->name);
                ret = -ENOENT;
                goto pdc_exit;
        }
@@ -485,7 +487,7 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
        if (!(pwrdm->pwrsts & (1 << pwrst)))
                return -EINVAL;
 
-       pr_debug("powerdomain: setting next powerstate for %s to %0x\n",
+       pr_debug("powerdomain: %s: setting next powerstate to %0x\n",
                 pwrdm->name, pwrst);
 
        if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) {
@@ -587,7 +589,7 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
        if (!(pwrdm->pwrsts_logic_ret & (1 << pwrst)))
                return -EINVAL;
 
-       pr_debug("powerdomain: setting next logic powerstate for %s to %0x\n",
+       pr_debug("powerdomain: %s: setting next logic powerstate to %0x\n",
                 pwrdm->name, pwrst);
 
        if (arch_pwrdm && arch_pwrdm->pwrdm_set_logic_retst)
@@ -624,8 +626,8 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
        if (!(pwrdm->pwrsts_mem_on[bank] & (1 << pwrst)))
                return -EINVAL;
 
-       pr_debug("powerdomain: setting next memory powerstate for domain %s "
-                "bank %0x while pwrdm-ON to %0x\n", pwrdm->name, bank, pwrst);
+       pr_debug("powerdomain: %s: setting next memory powerstate for bank %0x while pwrdm-ON to %0x\n",
+                pwrdm->name, bank, pwrst);
 
        if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_onst)
                ret = arch_pwrdm->pwrdm_set_mem_onst(pwrdm, bank, pwrst);
@@ -662,8 +664,8 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
        if (!(pwrdm->pwrsts_mem_ret[bank] & (1 << pwrst)))
                return -EINVAL;
 
-       pr_debug("powerdomain: setting next memory powerstate for domain %s "
-                "bank %0x while pwrdm-RET to %0x\n", pwrdm->name, bank, pwrst);
+       pr_debug("powerdomain: %s: setting next memory powerstate for bank %0x while pwrdm-RET to %0x\n",
+                pwrdm->name, bank, pwrst);
 
        if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_retst)
                ret = arch_pwrdm->pwrdm_set_mem_retst(pwrdm, bank, pwrst);
@@ -841,7 +843,7 @@ int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
         * warn & fail if it is not ON.
         */
 
-       pr_debug("powerdomain: clearing previous power state reg for %s\n",
+       pr_debug("powerdomain: %s: clearing previous power state reg\n",
                 pwrdm->name);
 
        if (arch_pwrdm && arch_pwrdm->pwrdm_clear_all_prev_pwrst)
@@ -871,8 +873,7 @@ int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
        if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
                return ret;
 
-       pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n",
-                pwrdm->name);
+       pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n", pwrdm->name);
 
        if (arch_pwrdm && arch_pwrdm->pwrdm_enable_hdwr_sar)
                ret = arch_pwrdm->pwrdm_enable_hdwr_sar(pwrdm);
@@ -901,8 +902,7 @@ int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
        if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
                return ret;
 
-       pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n",
-                pwrdm->name);
+       pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n", pwrdm->name);
 
        if (arch_pwrdm && arch_pwrdm->pwrdm_disable_hdwr_sar)
                ret = arch_pwrdm->pwrdm_disable_hdwr_sar(pwrdm);
index 0f0a9f1..3950ccf 100644 (file)
@@ -122,8 +122,8 @@ static int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm)
                        udelay(1);
 
        if (c > PWRDM_TRANSITION_BAILOUT) {
-               printk(KERN_ERR "powerdomain: waited too long for "
-                       "powerdomain %s to complete transition\n", pwrdm->name);
+               pr_err("powerdomain: %s: waited too long to complete transition\n",
+                      pwrdm->name);
                return -EAGAIN;
        }
 
index 601325b..aeac6f3 100644 (file)
@@ -198,8 +198,8 @@ static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
                udelay(1);
 
        if (c > PWRDM_TRANSITION_BAILOUT) {
-               printk(KERN_ERR "powerdomain: waited too long for "
-                      "powerdomain %s to complete transition\n", pwrdm->name);
+               pr_err("powerdomain: %s: waited too long to complete transition\n",
+                      pwrdm->name);
                return -EAGAIN;
        }
 
index bb883e4..8b23d23 100644 (file)
 #include <linux/init.h>
 #include <linux/bug.h>
 
-#include <plat/cpu.h>
-
+#include "soc.h"
 #include "powerdomain.h"
 #include "powerdomains2xxx_3xxx_data.h"
-
 #include "prcm-common.h"
 #include "prm2xxx_3xxx.h"
 #include "prm-regbits-34xx.h"
index 053e24e..0f51e03 100644 (file)
@@ -27,7 +27,6 @@
 
 #include "common.h"
 #include <plat/prcm.h>
-#include <plat/irqs.h>
 
 #include "clock.h"
 #include "clock2xxx.h"
@@ -140,11 +139,11 @@ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
                          MAX_MODULE_ENABLE_WAIT, i);
 
        if (i < MAX_MODULE_ENABLE_WAIT)
-               pr_debug("cm: Module associated with clock %s ready after %d "
-                        "loops\n", name, i);
+               pr_debug("cm: Module associated with clock %s ready after %d loops\n",
+                        name, i);
        else
-               pr_err("cm: Module associated with clock %s didn't enable in "
-                      "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
+               pr_err("cm: Module associated with clock %s didn't enable in %d tries\n",
+                      name, MAX_MODULE_ENABLE_WAIT);
 
        return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
 };
index a0309de..9529984 100644 (file)
 #include <linux/io.h>
 #include <linux/irq.h>
 
-#include "common.h"
-#include <plat/cpu.h>
 #include <plat/prcm.h>
-#include <plat/irqs.h>
 
+#include "soc.h"
+#include "common.h"
 #include "vp.h"
 
 #include "prm2xxx_3xxx.h"
@@ -40,7 +39,7 @@ static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
        .nr_regs                = 1,
        .irqs                   = omap3_prcm_irqs,
        .nr_irqs                = ARRAY_SIZE(omap3_prcm_irqs),
-       .irq                    = INT_34XX_PRCM_MPU_IRQ,
+       .irq                    = 11 + OMAP_INTC_START,
        .read_pending_irqs      = &omap3xxx_prm_read_pending_irqs,
        .ocp_barrier            = &omap3xxx_prm_ocp_barrier,
        .save_and_clear_irqen   = &omap3xxx_prm_save_and_clear_irqen,
index bb727c2..f0c4d5f 100644 (file)
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include <plat/cpu.h>
-#include <plat/irqs.h>
 #include <plat/prcm.h>
 
+#include "soc.h"
 #include "iomap.h"
 #include "common.h"
 #include "vp.h"
@@ -40,7 +39,7 @@ static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
        .nr_regs                = 2,
        .irqs                   = omap4_prcm_irqs,
        .nr_irqs                = ARRAY_SIZE(omap4_prcm_irqs),
-       .irq                    = OMAP44XX_IRQ_PRCM,
+       .irq                    = 11 + OMAP44XX_IRQ_GIC_START,
        .read_pending_irqs      = &omap44xx_prm_read_pending_irqs,
        .ocp_barrier            = &omap44xx_prm_ocp_barrier,
        .save_and_clear_irqen   = &omap44xx_prm_save_and_clear_irqen,
index 03b126d..6b4d332 100644 (file)
@@ -26,7 +26,6 @@
 
 #include <plat/common.h>
 #include <plat/prcm.h>
-#include <plat/irqs.h>
 
 #include "prm2xxx_3xxx.h"
 #include "prm44xx.h"
index 1133bb2..73e55e4 100644 (file)
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/hardware.h>
 #include <plat/clock.h>
 #include <plat/sram.h>
 #include <plat/sdrc.h>
 
+#include "soc.h"
 #include "iomap.h"
 #include "common.h"
 #include "prm2xxx_3xxx.h"
index 9e80d20..0405c81 100644 (file)
 
 #include <plat/omap-serial.h>
 #include "common.h"
-#include <plat/board.h>
 #include <plat/dma.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
 #include <plat/omap-pm.h>
+#include <plat/serial.h>
 
 #include "prm2xxx_3xxx.h"
 #include "pm.h"
@@ -232,9 +232,8 @@ static int __init omap_serial_early_init(void)
 
                        if (console_loglevel >= 10) {
                                uart_debug = true;
-                               pr_info("%s used as console in debug mode"
-                                               " uart%d clocks will not be"
-                                               " gated", uart_name, uart->num);
+                               pr_info("%s used as console in debug mode: uart%d clocks will not be gated",
+                                       uart_name, uart->num);
                        }
 
                        if (cmdline_find_option("no_console_suspend"))
@@ -319,8 +318,11 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
 
        pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size,
                                 NULL, 0, false);
-       WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
-            name, oh->name);
+       if (IS_ERR(pdev)) {
+               WARN(1, "Could not build omap_device for %s: %s.\n", name,
+                    oh->name);
+               return;
+       }
 
        if ((console_uart_id == bdata->id) && no_console_suspend)
                omap_device_disable_idle_on_suspend(pdev);
index d4bf904..ce0ccd2 100644 (file)
@@ -28,8 +28,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
-#include <plat/omap24xx.h>
-
+#include "omap24xx.h"
 #include "sdrc.h"
 
 /* First address of reserved address space?  apparently valid for OMAP2 & 3 */
index 1f62f23..5069879 100644 (file)
@@ -26,9 +26,9 @@
 
 #include <asm/assembler.h>
 
-#include <plat/hardware.h>
 #include <plat/sram.h>
 
+#include "omap34xx.h"
 #include "iomap.h"
 #include "cm2xxx_3xxx.h"
 #include "prm2xxx_3xxx.h"
index 91e71d8..88ff83a 100644 (file)
 #include <asm/memory.h>
 #include <asm/hardware/cache-l2x0.h>
 
-#include <plat/omap44xx.h>
-#include <mach/omap-secure.h>
+#include "omap-secure.h"
 
 #include "common.h"
+#include "omap44xx.h"
 #include "omap4-sar-layout.h"
 
 #if defined(CONFIG_SMP) && defined(CONFIG_PM)
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
new file mode 100644 (file)
index 0000000..fc9b96d
--- /dev/null
@@ -0,0 +1,7 @@
+#include <plat/cpu.h>
+#include "omap24xx.h"
+#include "omap34xx.h"
+#include "omap44xx.h"
+#include "ti81xx.h"
+#include "am33xx.h"
+#include "omap54xx.h"
index d033a65..cbeae56 100644 (file)
@@ -104,16 +104,15 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
 
        sr_data = kzalloc(sizeof(struct omap_sr_data), GFP_KERNEL);
        if (!sr_data) {
-               pr_err("%s: Unable to allocate memory for %s sr_data.Error!\n",
-                       __func__, oh->name);
+               pr_err("%s: Unable to allocate memory for %s sr_data\n",
+                      __func__, oh->name);
                return -ENOMEM;
        }
 
        sr_dev_attr = (struct omap_smartreflex_dev_attr *)oh->dev_attr;
        if (!sr_dev_attr || !sr_dev_attr->sensor_voltdm_name) {
-               pr_err("%s: No voltage domain specified for %s."
-                               "Cannot initialize\n", __func__,
-                                       oh->name);
+               pr_err("%s: No voltage domain specified for %s. Cannot initialize\n",
+                      __func__, oh->name);
                goto exit;
        }
 
@@ -131,8 +130,8 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
 
        omap_voltage_get_volttable(sr_data->voltdm, &volt_data);
        if (!volt_data) {
-               pr_warning("%s: No Voltage table registered fo VDD%d."
-                       "Something really wrong\n\n", __func__, i + 1);
+               pr_err("%s: No Voltage table registered for VDD%d\n",
+                      __func__, i + 1);
                goto exit;
        }
 
index ee0bfcc..8f7326c 100644 (file)
@@ -32,8 +32,7 @@
 
 #include <asm/assembler.h>
 
-#include <mach/hardware.h>
-
+#include "soc.h"
 #include "iomap.h"
 #include "prm2xxx_3xxx.h"
 #include "cm2xxx_3xxx.h"
index d4d39ef..b140d65 100644 (file)
@@ -32,8 +32,7 @@
 
 #include <asm/assembler.h>
 
-#include <mach/hardware.h>
-
+#include "soc.h"
 #include "iomap.h"
 #include "prm2xxx_3xxx.h"
 #include "cm2xxx_3xxx.h"
index df5a213..2d0ceaa 100644 (file)
@@ -29,8 +29,7 @@
 
 #include <asm/assembler.h>
 
-#include <mach/hardware.h>
-
+#include "soc.h"
 #include "iomap.h"
 #include "sdrc.h"
 #include "cm2xxx_3xxx.h"
index 2ba4f57..5214d5b 100644 (file)
 #include <linux/slab.h>
 
 #include <asm/mach/time.h>
-#include <plat/dmtimer.h>
 #include <asm/smp_twd.h>
 #include <asm/sched_clock.h>
-#include "common.h"
+
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
+#include <plat/dmtimer.h>
 #include <plat/omap-pm.h>
 
+#include "soc.h"
+#include "common.h"
 #include "powerdomain.h"
 
 /* Parent clocks, eventually these will come from the clock framework */
@@ -211,7 +213,7 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
        res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
        BUG_ON(res);
 
-       omap2_gp_timer_irq.dev_id = (void *)&clkev;
+       omap2_gp_timer_irq.dev_id = &clkev;
        setup_irq(clkev.irq, &omap2_gp_timer_irq);
 
        __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
@@ -380,8 +382,7 @@ OMAP_SYS_TIMER(3_am33xx)
 #ifdef CONFIG_ARCH_OMAP4
 #ifdef CONFIG_LOCAL_TIMERS
 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
-                             OMAP44XX_LOCAL_TWD_BASE,
-                             OMAP44XX_IRQ_LOCALTIMER);
+                             OMAP44XX_LOCAL_TWD_BASE, 29 + OMAP_INTC_START);
 #endif
 
 static void __init omap4_timer_init(void)
index 329b726..45f7741 100644 (file)
@@ -29,6 +29,7 @@
 #include <plat/i2c.h>
 #include <plat/usb.h>
 
+#include "soc.h"
 #include "twl-common.h"
 #include "pm.h"
 #include "voltage.h"
@@ -39,16 +40,6 @@ static struct i2c_board_info __initdata pmic_i2c_board_info = {
        .flags          = I2C_CLIENT_WAKE,
 };
 
-static struct i2c_board_info __initdata omap4_i2c1_board_info[] = {
-       {
-               .addr           = 0x48,
-               .flags          = I2C_CLIENT_WAKE,
-       },
-       {
-               I2C_BOARD_INFO("twl6040", 0x4b),
-       },
-};
-
 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 static int twl_set_voltage(void *data, int target_uV)
 {
@@ -78,30 +69,25 @@ void __init omap_pmic_init(int bus, u32 clkrate,
 
 void __init omap4_pmic_init(const char *pmic_type,
                    struct twl4030_platform_data *pmic_data,
-                   struct twl6040_platform_data *twl6040_data, int twl6040_irq)
+                   struct i2c_board_info *devices, int nr_devices)
 {
        /* PMIC part*/
        omap_mux_init_signal("sys_nirq1", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
-       strncpy(omap4_i2c1_board_info[0].type, pmic_type,
-               sizeof(omap4_i2c1_board_info[0].type));
-       omap4_i2c1_board_info[0].irq = OMAP44XX_IRQ_SYS_1N;
-       omap4_i2c1_board_info[0].platform_data = pmic_data;
-
-       /* TWL6040 audio IC part */
-       omap4_i2c1_board_info[1].irq = twl6040_irq;
-       omap4_i2c1_board_info[1].platform_data = twl6040_data;
-
-       omap_register_i2c_bus(1, 400, omap4_i2c1_board_info, 2);
+       omap_pmic_init(1, 400, pmic_type, 7 + OMAP44XX_IRQ_GIC_START, pmic_data);
 
+       /* Register additional devices on i2c1 bus if needed */
+       if (devices)
+               i2c_register_board_info(1, devices, nr_devices);
 }
 
 void __init omap_pmic_late_init(void)
 {
-       /* Init the OMAP TWL parameters (if PMIC has been registered) */
-       if (pmic_i2c_board_info.irq)
-               omap3_twl_init();
-       if (omap4_i2c1_board_info[0].irq)
-               omap4_twl_init();
+       /* Init the OMAP TWL parameters (if PMIC has been registerd) */
+       if (!pmic_i2c_board_info.irq)
+               return;
+
+       omap3_twl_init();
+       omap4_twl_init();
 }
 
 #if defined(CONFIG_ARCH_OMAP3)
index 8fe71cf..2256efe 100644 (file)
@@ -1,7 +1,7 @@
 #ifndef __OMAP_PMIC_COMMON__
 #define __OMAP_PMIC_COMMON__
 
-#include <plat/irqs.h>
+#include "common.h"
 
 #define TWL_COMMON_PDATA_USB           (1 << 0)
 #define TWL_COMMON_PDATA_BCI           (1 << 1)
@@ -32,6 +32,7 @@
 
 struct twl4030_platform_data;
 struct twl6040_platform_data;
+struct i2c_board_info;
 
 void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
                    struct twl4030_platform_data *pmic_data);
@@ -40,18 +41,18 @@ void omap_pmic_late_init(void);
 static inline void omap2_pmic_init(const char *pmic_type,
                                   struct twl4030_platform_data *pmic_data)
 {
-       omap_pmic_init(2, 2600, pmic_type, INT_24XX_SYS_NIRQ, pmic_data);
+       omap_pmic_init(2, 2600, pmic_type, 7 + OMAP_INTC_START, pmic_data);
 }
 
 static inline void omap3_pmic_init(const char *pmic_type,
                                   struct twl4030_platform_data *pmic_data)
 {
-       omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data);
+       omap_pmic_init(1, 2600, pmic_type, 7 + OMAP_INTC_START, pmic_data);
 }
 
 void omap4_pmic_init(const char *pmic_type,
                    struct twl4030_platform_data *pmic_data,
-                   struct twl6040_platform_data *audio_data, int twl6040_irq);
+                   struct i2c_board_info *devices, int nr_devices);
 
 void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
                           u32 pdata_flags, u32 regulators_flags);
index dde8a11..ac95daa 100644 (file)
@@ -25,8 +25,6 @@
 
 #include <asm/io.h>
 
-#include <mach/hardware.h>
-#include <mach/irqs.h>
 #include <plat/usb.h>
 #include <plat/omap_device.h>
 
index e9b4b23..51da21c 100644 (file)
 #include <linux/clk.h>
 #include <linux/dma-mapping.h>
 #include <linux/io.h>
-
 #include <linux/usb/musb.h>
 
-#include <mach/hardware.h>
-#include <mach/irqs.h>
-#include <mach/am35xx.h>
 #include <plat/usb.h>
 #include <plat/omap_device.h>
+
+#include "am35xx.h"
+
 #include "mux.h"
 
 static struct musb_hdrc_config musb_config = {
index 84da34f..880249b 100644 (file)
@@ -12,8 +12,7 @@
 #include <linux/init.h>
 #include <linux/bug.h>
 
-#include <plat/cpu.h>
-
+#include "soc.h"
 #include "voltage.h"
 #include "vc.h"
 #include "prm-regbits-34xx.h"
@@ -116,9 +115,8 @@ int omap_vc_pre_scale(struct voltagedomain *voltdm,
        }
 
        if (!voltdm->pmic->uv_to_vsel) {
-               pr_err("%s: PMIC function to convert voltage in uV to"
-                       "vsel not registered. Hence unable to scale voltage"
-                       "for vdd_%s\n", __func__, voltdm->name);
+               pr_err("%s: PMIC function to convert voltage in uV to vsel not registered. Hence unable to scale voltage for vdd_%s\n",
+                      __func__, voltdm->name);
                return -ENODATA;
        }
 
index 4dc60e8..3ac8fe1 100644 (file)
@@ -195,8 +195,8 @@ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
                        return &voltdm->volt_data[i];
        }
 
-       pr_notice("%s: Unable to match the current voltage with the voltage"
-               "table for vdd_%s\n", __func__, voltdm->name);
+       pr_notice("%s: Unable to match the current voltage with the voltage table for vdd_%s\n",
+                 __func__, voltdm->name);
 
        return ERR_PTR(-ENODATA);
 }
@@ -249,8 +249,8 @@ void omap_change_voltscale_method(struct voltagedomain *voltdm,
                voltdm->scale = omap_vc_bypass_scale;
                return;
        default:
-               pr_warning("%s: Trying to change the method of voltage scaling"
-                       "to an unsupported one!\n", __func__);
+               pr_warn("%s: Trying to change the method of voltage scaling to an unsupported one!\n",
+                       __func__);
        }
 }
 
@@ -331,8 +331,8 @@ int voltdm_add_pwrdm(struct voltagedomain *voltdm, struct powerdomain *pwrdm)
        if (!voltdm || !pwrdm)
                return -EINVAL;
 
-       pr_debug("voltagedomain: associating powerdomain %s with voltagedomain "
-                "%s\n", pwrdm->name, voltdm->name);
+       pr_debug("voltagedomain: %s: associating powerdomain %s\n",
+                voltdm->name, pwrdm->name);
 
        list_add(&pwrdm->voltdm_node, &voltdm->pwrdm_list);
 
index 0ac2caf..7283b7e 100644 (file)
@@ -16,7 +16,7 @@
 
 #include <linux/err.h>
 
-#include <plat/voltage.h>
+#include <linux/platform_data/voltage-omap.h>
 
 #include "vc.h"
 #include "vp.h"
index d0103c8..63afbfe 100644 (file)
@@ -18,9 +18,8 @@
 #include <linux/err.h>
 #include <linux/init.h>
 
+#include "soc.h"
 #include "common.h"
-#include <plat/cpu.h>
-
 #include "prm-regbits-34xx.h"
 #include "omap_opp_data.h"
 #include "voltage.h"
index f95c1ba..85241b8 100644 (file)
@@ -138,8 +138,8 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
                udelay(1);
        }
        if (timeout >= VP_TRANXDONE_TIMEOUT) {
-               pr_warning("%s: vdd_%s TRANXDONE timeout exceeded."
-                       "Voltage change aborted", __func__, voltdm->name);
+               pr_warn("%s: vdd_%s TRANXDONE timeout exceeded. Voltage change aborted",
+                       __func__, voltdm->name);
                return -ETIMEDOUT;
        }
 
@@ -157,9 +157,8 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
        omap_test_timeout(vp->common->ops->check_txdone(vp->id),
                          VP_TRANXDONE_TIMEOUT, timeout);
        if (timeout >= VP_TRANXDONE_TIMEOUT)
-               pr_err("%s: vdd_%s TRANXDONE timeout exceeded."
-                       "TRANXDONE never got set after the voltage update\n",
-                       __func__, voltdm->name);
+               pr_err("%s: vdd_%s TRANXDONE timeout exceeded. TRANXDONE never got set after the voltage update\n",
+                      __func__, voltdm->name);
 
        omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
 
@@ -176,8 +175,7 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
        }
 
        if (timeout >= VP_TRANXDONE_TIMEOUT)
-               pr_warning("%s: vdd_%s TRANXDONE timeout exceeded while trying"
-                       "to clear the TRANXDONE status\n",
+               pr_warn("%s: vdd_%s TRANXDONE timeout exceeded while trying to clear the TRANXDONE status\n",
                        __func__, voltdm->name);
 
        /* Clear force bit */
@@ -257,8 +255,8 @@ void omap_vp_disable(struct voltagedomain *voltdm)
 
        /* If VP is already disabled, do nothing. Return */
        if (!vp->enabled) {
-               pr_warning("%s: Trying to disable VP for vdd_%s when"
-                       "it is already disabled\n", __func__, voltdm->name);
+               pr_warn("%s: Trying to disable VP for vdd_%s when it is already disabled\n",
+                       __func__, voltdm->name);
                return;
        }
 
index a6cd14a..2fdd4e4 100644 (file)
@@ -47,16 +47,6 @@ static struct map_desc orion5x_io_desc[] __initdata = {
                .length         = ORION5X_REGS_SIZE,
                .type           = MT_DEVICE,
        }, {
-               .virtual        = ORION5X_PCIE_IO_VIRT_BASE,
-               .pfn            = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
-               .length         = ORION5X_PCIE_IO_SIZE,
-               .type           = MT_DEVICE,
-       }, {
-               .virtual        = ORION5X_PCI_IO_VIRT_BASE,
-               .pfn            = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
-               .length         = ORION5X_PCI_IO_SIZE,
-               .type           = MT_DEVICE,
-       }, {
                .virtual        = ORION5X_PCIE_WA_VIRT_BASE,
                .pfn            = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
                .length         = ORION5X_PCIE_WA_SIZE,
diff --git a/arch/arm/mach-orion5x/include/mach/io.h b/arch/arm/mach-orion5x/include/mach/io.h
deleted file mode 100644 (file)
index 1aa5d0a..0000000
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * arch/arm/mach-orion5x/include/mach/io.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#include <mach/orion5x.h>
-#include <asm/sizes.h>
-
-#define IO_SPACE_LIMIT         SZ_2M
-static inline void __iomem *__io(unsigned long addr)
-{
-       return (void __iomem *)(addr + ORION5X_PCIE_IO_VIRT_BASE);
-}
-
-#define __io(a)                         __io(a)
-#endif
index 683e085..1b60131 100644 (file)
  * fc000000    device bus mappings (cs0/cs1)
  *
  * virt                phys            size
- * fdd00000    f1000000        1M      on-chip peripheral registers
- * fde00000    f2000000        1M      PCIe I/O space
- * fdf00000    f2100000        1M      PCI I/O space
- * fe000000    f0000000        16M     PCIe WA space (Orion-1/Orion-NAS only)
+ * fe000000    f1000000        1M      on-chip peripheral registers
+ * fee00000    f2000000        64K     PCIe I/O space
+ * fee10000    f2100000        64K     PCI I/O space
+ * fd000000    f0000000        16M     PCIe WA space (Orion-1/Orion-NAS only)
  ****************************************************************************/
 #define ORION5X_REGS_PHYS_BASE         0xf1000000
-#define ORION5X_REGS_VIRT_BASE         0xfdd00000
+#define ORION5X_REGS_VIRT_BASE         0xfe000000
 #define ORION5X_REGS_SIZE              SZ_1M
 
 #define ORION5X_PCIE_IO_PHYS_BASE      0xf2000000
-#define ORION5X_PCIE_IO_VIRT_BASE      0xfde00000
 #define ORION5X_PCIE_IO_BUS_BASE       0x00000000
-#define ORION5X_PCIE_IO_SIZE           SZ_1M
+#define ORION5X_PCIE_IO_SIZE           SZ_64K
 
 #define ORION5X_PCI_IO_PHYS_BASE       0xf2100000
-#define ORION5X_PCI_IO_VIRT_BASE       0xfdf00000
-#define ORION5X_PCI_IO_BUS_BASE                0x00100000
-#define ORION5X_PCI_IO_SIZE            SZ_1M
+#define ORION5X_PCI_IO_BUS_BASE                0x00010000
+#define ORION5X_PCI_IO_SIZE            SZ_64K
 
 #define ORION5X_SRAM_PHYS_BASE         (0xf2200000)
 #define ORION5X_SRAM_SIZE              SZ_8K
 
 /* Relevant only for Orion-1/Orion-NAS */
 #define ORION5X_PCIE_WA_PHYS_BASE      0xf0000000
-#define ORION5X_PCIE_WA_VIRT_BASE      0xfe000000
+#define ORION5X_PCIE_WA_VIRT_BASE      0xfd000000
 #define ORION5X_PCIE_WA_SIZE           SZ_16M
 
 #define ORION5X_PCIE_MEM_PHYS_BASE     0xe0000000
index cb19e16..6921d49 100644 (file)
@@ -162,35 +162,25 @@ static int __init pcie_setup(struct pci_sys_data *sys)
                pcie_ops.read = pcie_rd_conf_wa;
        }
 
+       pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCIE_IO_PHYS_BASE);
+
        /*
         * Request resources.
         */
-       res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
+       res = kzalloc(sizeof(struct resource), GFP_KERNEL);
        if (!res)
                panic("pcie_setup unable to alloc resources");
 
        /*
-        * IORESOURCE_IO
-        */
-       sys->io_offset = 0;
-       res[0].name = "PCIe I/O Space";
-       res[0].flags = IORESOURCE_IO;
-       res[0].start = ORION5X_PCIE_IO_BUS_BASE;
-       res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1;
-       if (request_resource(&ioport_resource, &res[0]))
-               panic("Request PCIe IO resource failed\n");
-       pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
-
-       /*
         * IORESOURCE_MEM
         */
-       res[1].name = "PCIe Memory Space";
-       res[1].flags = IORESOURCE_MEM;
-       res[1].start = ORION5X_PCIE_MEM_PHYS_BASE;
-       res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1;
-       if (request_resource(&iomem_resource, &res[1]))
+       res->name = "PCIe Memory Space";
+       res->flags = IORESOURCE_MEM;
+       res->start = ORION5X_PCIE_MEM_PHYS_BASE;
+       res->end = res->start + ORION5X_PCIE_MEM_SIZE - 1;
+       if (request_resource(&iomem_resource, res))
                panic("Request PCIe Memory resource failed\n");
-       pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
+       pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
 
        return 1;
 }
@@ -489,35 +479,25 @@ static int __init pci_setup(struct pci_sys_data *sys)
         */
        orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
 
+       pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCI_IO_PHYS_BASE);
+
        /*
         * Request resources
         */
-       res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
+       res = kzalloc(sizeof(struct resource), GFP_KERNEL);
        if (!res)
                panic("pci_setup unable to alloc resources");
 
        /*
-        * IORESOURCE_IO
-        */
-       sys->io_offset = 0;
-       res[0].name = "PCI I/O Space";
-       res[0].flags = IORESOURCE_IO;
-       res[0].start = ORION5X_PCI_IO_BUS_BASE;
-       res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1;
-       if (request_resource(&ioport_resource, &res[0]))
-               panic("Request PCI IO resource failed\n");
-       pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
-
-       /*
         * IORESOURCE_MEM
         */
-       res[1].name = "PCI Memory Space";
-       res[1].flags = IORESOURCE_MEM;
-       res[1].start = ORION5X_PCI_MEM_PHYS_BASE;
-       res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1;
-       if (request_resource(&iomem_resource, &res[1]))
+       res->name = "PCI Memory Space";
+       res->flags = IORESOURCE_MEM;
+       res->start = ORION5X_PCI_MEM_PHYS_BASE;
+       res->end = res->start + ORION5X_PCI_MEM_SIZE - 1;
+       if (request_resource(&iomem_resource, res))
                panic("Request PCI Memory resource failed\n");
-       pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
+       pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
 
        return 1;
 }
diff --git a/arch/arm/mach-pnx4008/Makefile b/arch/arm/mach-pnx4008/Makefile
deleted file mode 100644 (file)
index 777564c..0000000
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-obj-y                  := core.o irq.o time.o clock.o gpio.o serial.o dma.o i2c.o
-obj-m                  :=
-obj-n                  :=
-obj-                   :=
-
-# Power Management
-obj-$(CONFIG_PM) += pm.o sleep.o
-
diff --git a/arch/arm/mach-pnx4008/Makefile.boot b/arch/arm/mach-pnx4008/Makefile.boot
deleted file mode 100644 (file)
index 9fa19ba..0000000
+++ /dev/null
@@ -1,4 +0,0 @@
-   zreladdr-y          += 0x80008000
-params_phys-y          := 0x80000100
-initrd_phys-y          := 0x80800000
-
diff --git a/arch/arm/mach-pnx4008/clock.c b/arch/arm/mach-pnx4008/clock.c
deleted file mode 100644 (file)
index a4a3819..0000000
+++ /dev/null
@@ -1,1001 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/clock.c
- *
- * Clock control driver for PNX4008
- *
- * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
- * Generic clock management functions are partially based on:
- *  linux/arch/arm/mach-omap/clock.c
- *
- * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/device.h>
-#include <linux/err.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-
-#include <mach/hardware.h>
-#include <mach/clock.h>
-#include "clock.h"
-
-/*forward declaration*/
-static struct clk per_ck;
-static struct clk hclk_ck;
-static struct clk ck_1MHz;
-static struct clk ck_13MHz;
-static struct clk ck_pll1;
-static int local_set_rate(struct clk *clk, u32 rate);
-
-static inline void clock_lock(void)
-{
-       local_irq_disable();
-}
-
-static inline void clock_unlock(void)
-{
-       local_irq_enable();
-}
-
-static void propagate_rate(struct clk *clk)
-{
-       struct clk *tmp_clk;
-
-       tmp_clk = clk;
-       while (tmp_clk->propagate_next) {
-               tmp_clk = tmp_clk->propagate_next;
-               local_set_rate(tmp_clk, tmp_clk->user_rate);
-       }
-}
-
-static void clk_reg_disable(struct clk *clk)
-{
-       if (clk->enable_reg)
-               __raw_writel(__raw_readl(clk->enable_reg) &
-                            ~(1 << clk->enable_shift), clk->enable_reg);
-}
-
-static int clk_reg_enable(struct clk *clk)
-{
-       if (clk->enable_reg)
-               __raw_writel(__raw_readl(clk->enable_reg) |
-                            (1 << clk->enable_shift), clk->enable_reg);
-       return 0;
-}
-
-static inline void clk_reg_disable1(struct clk *clk)
-{
-       if (clk->enable_reg1)
-               __raw_writel(__raw_readl(clk->enable_reg1) &
-                            ~(1 << clk->enable_shift1), clk->enable_reg1);
-}
-
-static inline void clk_reg_enable1(struct clk *clk)
-{
-       if (clk->enable_reg1)
-               __raw_writel(__raw_readl(clk->enable_reg1) |
-                            (1 << clk->enable_shift1), clk->enable_reg1);
-}
-
-static int clk_wait_for_pll_lock(struct clk *clk)
-{
-       int i;
-       i = 0;
-       while (i++ < 0xFFF && !(__raw_readl(clk->scale_reg) & 1)) ;     /*wait for PLL to lock */
-
-       if (!(__raw_readl(clk->scale_reg) & 1)) {
-               printk(KERN_ERR
-                      "%s ERROR: failed to lock, scale reg data: %x\n",
-                      clk->name, __raw_readl(clk->scale_reg));
-               return -1;
-       }
-       return 0;
-}
-
-static int switch_to_dirty_13mhz(struct clk *clk)
-{
-       int i;
-       int ret;
-       u32 tmp_reg;
-
-       ret = 0;
-
-       if (!clk->rate)
-               clk_reg_enable1(clk);
-
-       tmp_reg = __raw_readl(clk->parent_switch_reg);
-       /*if 13Mhz clock selected, select 13'MHz (dirty) source from OSC */
-       if (!(tmp_reg & 1)) {
-               tmp_reg |= (1 << 1);    /* Trigger switch to 13'MHz (dirty) clock */
-               __raw_writel(tmp_reg, clk->parent_switch_reg);
-               i = 0;
-               while (i++ < 0xFFF && !(__raw_readl(clk->parent_switch_reg) & 1)) ;     /*wait for 13'MHz selection status */
-
-               if (!(__raw_readl(clk->parent_switch_reg) & 1)) {
-                       printk(KERN_ERR
-                              "%s ERROR: failed to select 13'MHz, parent sw reg data: %x\n",
-                              clk->name, __raw_readl(clk->parent_switch_reg));
-                       ret = -1;
-               }
-       }
-
-       if (!clk->rate)
-               clk_reg_disable1(clk);
-
-       return ret;
-}
-
-static int switch_to_clean_13mhz(struct clk *clk)
-{
-       int i;
-       int ret;
-       u32 tmp_reg;
-
-       ret = 0;
-
-       if (!clk->rate)
-               clk_reg_enable1(clk);
-
-       tmp_reg = __raw_readl(clk->parent_switch_reg);
-       /*if 13'Mhz clock selected, select 13MHz (clean) source from OSC */
-       if (tmp_reg & 1) {
-               tmp_reg &= ~(1 << 1);   /* Trigger switch to 13MHz (clean) clock */
-               __raw_writel(tmp_reg, clk->parent_switch_reg);
-               i = 0;
-               while (i++ < 0xFFF && (__raw_readl(clk->parent_switch_reg) & 1)) ;      /*wait for 13MHz selection status */
-
-               if (__raw_readl(clk->parent_switch_reg) & 1) {
-                       printk(KERN_ERR
-                              "%s ERROR: failed to select 13MHz, parent sw reg data: %x\n",
-                              clk->name, __raw_readl(clk->parent_switch_reg));
-                       ret = -1;
-               }
-       }
-
-       if (!clk->rate)
-               clk_reg_disable1(clk);
-
-       return ret;
-}
-
-static int set_13MHz_parent(struct clk *clk, struct clk *parent)
-{
-       int ret = -EINVAL;
-
-       if (parent == &ck_13MHz)
-               ret = switch_to_clean_13mhz(clk);
-       else if (parent == &ck_pll1)
-               ret = switch_to_dirty_13mhz(clk);
-
-       return ret;
-}
-
-#define PLL160_MIN_FCCO 156000
-#define PLL160_MAX_FCCO 320000
-
-/*
- * Calculate pll160 settings.
- * Possible input: up to 320MHz with step of clk->parent->rate.
- * In PNX4008 parent rate for pll160s may be either 1 or 13MHz.
- * Ignored paths: "feedback" (bit 13 set), "div-by-N".
- * Setting ARM PLL4 rate to 0 will put CPU into direct run mode.
- * Setting PLL5 and PLL3 rate to 0 will disable USB and DSP clock input.
- * Please refer to PNX4008 IC manual for details.
- */
-
-static int pll160_set_rate(struct clk *clk, u32 rate)
-{
-       u32 tmp_reg, tmp_m, tmp_2p, i;
-       u32 parent_rate;
-       int ret = -EINVAL;
-
-       parent_rate = clk->parent->rate;
-
-       if (!parent_rate)
-               goto out;
-
-       /* set direct run for ARM or disable output for others  */
-       clk_reg_disable(clk);
-
-       /* disable source input as well (ignored for ARM) */
-       clk_reg_disable1(clk);
-
-       tmp_reg = __raw_readl(clk->scale_reg);
-       tmp_reg &= ~0x1ffff;    /*clear all settings, power down */
-       __raw_writel(tmp_reg, clk->scale_reg);
-
-       rate -= rate % parent_rate;     /*round down the input */
-
-       if (rate > PLL160_MAX_FCCO)
-               rate = PLL160_MAX_FCCO;
-
-       if (!rate) {
-               clk->rate = 0;
-               ret = 0;
-               goto out;
-       }
-
-       clk_reg_enable1(clk);
-       tmp_reg = __raw_readl(clk->scale_reg);
-
-       if (rate == parent_rate) {
-               /*enter direct bypass mode */
-               tmp_reg |= ((1 << 14) | (1 << 15));
-               __raw_writel(tmp_reg, clk->scale_reg);
-               clk->rate = parent_rate;
-               clk_reg_enable(clk);
-               ret = 0;
-               goto out;
-       }
-
-       i = 0;
-       for (tmp_2p = 1; tmp_2p < 16; tmp_2p <<= 1) {
-               if (rate * tmp_2p >= PLL160_MIN_FCCO)
-                       break;
-               i++;
-       }
-
-       if (tmp_2p > 1)
-               tmp_reg |= ((i - 1) << 11);
-       else
-               tmp_reg |= (1 << 14);   /*direct mode, no divide */
-
-       tmp_m = rate * tmp_2p;
-       tmp_m /= parent_rate;
-
-       tmp_reg |= (tmp_m - 1) << 1;    /*calculate M */
-       tmp_reg |= (1 << 16);   /*power up PLL */
-       __raw_writel(tmp_reg, clk->scale_reg);
-
-       if (clk_wait_for_pll_lock(clk) < 0) {
-               clk_reg_disable(clk);
-               clk_reg_disable1(clk);
-
-               tmp_reg = __raw_readl(clk->scale_reg);
-               tmp_reg &= ~0x1ffff;    /*clear all settings, power down */
-               __raw_writel(tmp_reg, clk->scale_reg);
-               clk->rate = 0;
-               ret = -EFAULT;
-               goto out;
-       }
-
-       clk->rate = (tmp_m * parent_rate) / tmp_2p;
-
-       if (clk->flags & RATE_PROPAGATES)
-               propagate_rate(clk);
-
-       clk_reg_enable(clk);
-       ret = 0;
-
-out:
-       return ret;
-}
-
-/*configure PER_CLK*/
-static int per_clk_set_rate(struct clk *clk, u32 rate)
-{
-       u32 tmp;
-
-       tmp = __raw_readl(clk->scale_reg);
-       tmp &= ~(0x1f << 2);
-       tmp |= ((clk->parent->rate / clk->rate) - 1) << 2;
-       __raw_writel(tmp, clk->scale_reg);
-       clk->rate = rate;
-       return 0;
-}
-
-/*configure HCLK*/
-static int hclk_set_rate(struct clk *clk, u32 rate)
-{
-       u32 tmp;
-       tmp = __raw_readl(clk->scale_reg);
-       tmp = tmp & ~0x3;
-       switch (rate) {
-       case 1:
-               break;
-       case 2:
-               tmp |= 1;
-               break;
-       case 4:
-               tmp |= 2;
-               break;
-       }
-
-       __raw_writel(tmp, clk->scale_reg);
-       clk->rate = rate;
-       return 0;
-}
-
-static u32 hclk_round_rate(struct clk *clk, u32 rate)
-{
-       switch (rate) {
-       case 1:
-       case 4:
-               return rate;
-       }
-       return 2;
-}
-
-static u32 per_clk_round_rate(struct clk *clk, u32 rate)
-{
-       return CLK_RATE_13MHZ;
-}
-
-static int on_off_set_rate(struct clk *clk, u32 rate)
-{
-       if (rate) {
-               clk_reg_enable(clk);
-               clk->rate = 1;
-       } else {
-               clk_reg_disable(clk);
-               clk->rate = 0;
-       }
-       return 0;
-}
-
-static int on_off_inv_set_rate(struct clk *clk, u32 rate)
-{
-       if (rate) {
-               clk_reg_disable(clk);   /*enable bit is inverted */
-               clk->rate = 1;
-       } else {
-               clk_reg_enable(clk);
-               clk->rate = 0;
-       }
-       return 0;
-}
-
-static u32 on_off_round_rate(struct clk *clk, u32 rate)
-{
-       return (rate ? 1 : 0);
-}
-
-static u32 pll4_round_rate(struct clk *clk, u32 rate)
-{
-       if (rate > CLK_RATE_208MHZ)
-               rate = CLK_RATE_208MHZ;
-       if (rate == CLK_RATE_208MHZ && hclk_ck.user_rate == 1)
-               rate = CLK_RATE_208MHZ - CLK_RATE_13MHZ;
-       return (rate - (rate % (hclk_ck.user_rate * CLK_RATE_13MHZ)));
-}
-
-static u32 pll3_round_rate(struct clk *clk, u32 rate)
-{
-       if (rate > CLK_RATE_208MHZ)
-               rate = CLK_RATE_208MHZ;
-       return (rate - rate % CLK_RATE_13MHZ);
-}
-
-static u32 pll5_round_rate(struct clk *clk, u32 rate)
-{
-       return (rate ? CLK_RATE_48MHZ : 0);
-}
-
-static u32 ck_13MHz_round_rate(struct clk *clk, u32 rate)
-{
-       return (rate ? CLK_RATE_13MHZ : 0);
-}
-
-static int ck_13MHz_set_rate(struct clk *clk, u32 rate)
-{
-       if (rate) {
-               clk_reg_disable(clk);   /*enable bit is inverted */
-               udelay(500);
-               clk->rate = CLK_RATE_13MHZ;
-               ck_1MHz.rate = CLK_RATE_1MHZ;
-       } else {
-               clk_reg_enable(clk);
-               clk->rate = 0;
-               ck_1MHz.rate = 0;
-       }
-       return 0;
-}
-
-static int pll1_set_rate(struct clk *clk, u32 rate)
-{
-#if 0 /* doesn't work on some boards, probably a HW BUG */
-       if (rate) {
-               clk_reg_disable(clk);   /*enable bit is inverted */
-               if (!clk_wait_for_pll_lock(clk)) {
-                       clk->rate = CLK_RATE_13MHZ;
-               } else {
-                       clk_reg_enable(clk);
-                       clk->rate = 0;
-               }
-
-       } else {
-               clk_reg_enable(clk);
-               clk->rate = 0;
-       }
-#endif
-       return 0;
-}
-
-/* Clock sources */
-
-static struct clk osc_13MHz = {
-       .name = "osc_13MHz",
-       .flags = FIXED_RATE,
-       .rate = CLK_RATE_13MHZ,
-};
-
-static struct clk ck_13MHz = {
-       .name = "ck_13MHz",
-       .parent = &osc_13MHz,
-       .flags = NEEDS_INITIALIZATION,
-       .round_rate = &ck_13MHz_round_rate,
-       .set_rate = &ck_13MHz_set_rate,
-       .enable_reg = OSC13CTRL_REG,
-       .enable_shift = 0,
-       .rate = CLK_RATE_13MHZ,
-};
-
-static struct clk osc_32KHz = {
-       .name = "osc_32KHz",
-       .flags = FIXED_RATE,
-       .rate = CLK_RATE_32KHZ,
-};
-
-/*attached to PLL5*/
-static struct clk ck_1MHz = {
-       .name = "ck_1MHz",
-       .flags = FIXED_RATE | PARENT_SET_RATE,
-       .parent = &ck_13MHz,
-};
-
-/* PLL1 (397) - provides 13' MHz clock */
-static struct clk ck_pll1 = {
-       .name = "ck_pll1",
-       .parent = &osc_32KHz,
-       .flags = NEEDS_INITIALIZATION,
-       .round_rate = &ck_13MHz_round_rate,
-       .set_rate = &pll1_set_rate,
-       .enable_reg = PLLCTRL_REG,
-       .enable_shift = 1,
-       .scale_reg = PLLCTRL_REG,
-       .rate = CLK_RATE_13MHZ,
-};
-
-/* CPU/Bus PLL */
-static struct clk ck_pll4 = {
-       .name = "ck_pll4",
-       .parent = &ck_pll1,
-       .flags = RATE_PROPAGATES | NEEDS_INITIALIZATION,
-       .propagate_next = &per_ck,
-       .round_rate = &pll4_round_rate,
-       .set_rate = &pll160_set_rate,
-       .rate = CLK_RATE_208MHZ,
-       .scale_reg = HCLKPLLCTRL_REG,
-       .enable_reg = PWRCTRL_REG,
-       .enable_shift = 2,
-       .parent_switch_reg = SYSCLKCTRL_REG,
-       .set_parent = &set_13MHz_parent,
-};
-
-/* USB PLL */
-static struct clk ck_pll5 = {
-       .name = "ck_pll5",
-       .parent = &ck_1MHz,
-       .flags = NEEDS_INITIALIZATION,
-       .round_rate = &pll5_round_rate,
-       .set_rate = &pll160_set_rate,
-       .scale_reg = USBCTRL_REG,
-       .enable_reg = USBCTRL_REG,
-       .enable_shift = 18,
-       .enable_reg1 = USBCTRL_REG,
-       .enable_shift1 = 17,
-};
-
-/* XPERTTeak DSP PLL */
-static struct clk ck_pll3 = {
-       .name = "ck_pll3",
-       .parent = &ck_pll1,
-       .flags = NEEDS_INITIALIZATION,
-       .round_rate = &pll3_round_rate,
-       .set_rate = &pll160_set_rate,
-       .scale_reg = DSPPLLCTRL_REG,
-       .enable_reg = DSPCLKCTRL_REG,
-       .enable_shift = 3,
-       .enable_reg1 = DSPCLKCTRL_REG,
-       .enable_shift1 = 2,
-       .parent_switch_reg = DSPCLKCTRL_REG,
-       .set_parent = &set_13MHz_parent,
-};
-
-static struct clk hclk_ck = {
-       .name = "hclk_ck",
-       .parent = &ck_pll4,
-       .flags = PARENT_SET_RATE,
-       .set_rate = &hclk_set_rate,
-       .round_rate = &hclk_round_rate,
-       .scale_reg = HCLKDIVCTRL_REG,
-       .rate = 2,
-       .user_rate = 2,
-};
-
-static struct clk per_ck = {
-       .name = "per_ck",
-       .parent = &ck_pll4,
-       .flags = FIXED_RATE,
-       .propagate_next = &hclk_ck,
-       .set_rate = &per_clk_set_rate,
-       .round_rate = &per_clk_round_rate,
-       .scale_reg = HCLKDIVCTRL_REG,
-       .rate = CLK_RATE_13MHZ,
-       .user_rate = CLK_RATE_13MHZ,
-};
-
-static struct clk m2hclk_ck = {
-       .name = "m2hclk_ck",
-       .parent = &hclk_ck,
-       .flags = NEEDS_INITIALIZATION,
-       .round_rate = &on_off_round_rate,
-       .set_rate = &on_off_inv_set_rate,
-       .rate = 1,
-       .enable_shift = 6,
-       .enable_reg = PWRCTRL_REG,
-};
-
-static struct clk vfp9_ck = {
-       .name = "vfp9_ck",
-       .parent = &ck_pll4,
-       .flags = NEEDS_INITIALIZATION,
-       .round_rate = &on_off_round_rate,
-       .set_rate = &on_off_set_rate,
-       .rate = 1,
-       .enable_shift = 4,
-       .enable_reg = VFP9CLKCTRL_REG,
-};
-
-static struct clk keyscan_ck = {
-       .name = "keyscan_ck",
-       .parent = &osc_32KHz,
-       .flags = NEEDS_INITIALIZATION,
-       .round_rate = &on_off_round_rate,
-       .set_rate = &on_off_set_rate,
-       .enable_shift = 0,
-       .enable_reg = KEYCLKCTRL_REG,
-};
-
-static struct clk touch_ck = {
-       .name = "touch_ck",
-       .parent = &osc_32KHz,
-       .flags = NEEDS_INITIALIZATION,
-       .round_rate = &on_off_round_rate,
-       .set_rate = &on_off_set_rate,
-       .enable_shift = 0,
-       .enable_reg = TSCLKCTRL_REG,
-};
-
-static struct clk pwm1_ck = {
-       .name = "pwm1_ck",
-       .parent = &osc_32KHz,
-       .flags = NEEDS_INITIALIZATION,
-       .round_rate = &on_off_round_rate,
-       .set_rate = &on_off_set_rate,
-       .enable_shift = 0,
-       .enable_reg = PWMCLKCTRL_REG,
-};
-
-static struct clk pwm2_ck = {
-       .name = "pwm2_ck",
-       .parent = &osc_32KHz,
-       .flags = NEEDS_INITIALIZATION,
-       .round_rate = &on_off_round_rate,
-       .set_rate = &on_off_set_rate,
-       .enable_shift = 2,
-       .enable_reg = PWMCLKCTRL_REG,
-};
-
-static struct clk jpeg_ck = {
-       .name = "jpeg_ck",
-       .parent = &hclk_ck,
-       .flags = NEEDS_INITIALIZATION,
-       .round_rate = &on_off_round_rate,
-       .set_rate = &on_off_set_rate,
-       .enable_shift = 0,
-       .enable_reg = JPEGCLKCTRL_REG,
-};
-
-static struct clk ms_ck = {
-       .name = "ms_ck",
-       .parent = &ck_pll4,
-       .flags = NEEDS_INITIALIZATION,
-       .round_rate = &on_off_round_rate,
-       .set_rate = &on_off_set_rate,
-       .enable_shift = 5,
-       .enable_reg = MSCTRL_REG,
-};
-
-static struct clk dum_ck = {
-       .name = "dum_ck",
-       .parent = &hclk_ck,
-       .flags = NEEDS_INITIALIZATION,
-       .round_rate = &on_off_round_rate,
-       .set_rate = &on_off_set_rate,
-       .enable_shift = 0,
-       .enable_reg = DUMCLKCTRL_REG,
-};
-
-static struct clk flash_ck = {
-       .name = "flash_ck",
-       .parent = &hclk_ck,
-       .round_rate = &on_off_round_rate,
-       .set_rate = &on_off_set_rate,
-       .enable_shift = 1,      /* Only MLC clock supported */
-       .enable_reg = FLASHCLKCTRL_REG,
-};
-
-static struct clk i2c0_ck = {
-       .name = "i2c0_ck",
-       .parent = &per_ck,
-       .flags = NEEDS_INITIALIZATION | FIXED_RATE,
-       .enable_shift = 0,
-       .enable_reg = I2CCLKCTRL_REG,
-       .rate = 13000000,
-       .enable = clk_reg_enable,
-       .disable = clk_reg_disable,
-};
-
-static struct clk i2c1_ck = {
-       .name = "i2c1_ck",
-       .parent = &per_ck,
-       .flags = NEEDS_INITIALIZATION | FIXED_RATE,
-       .enable_shift = 1,
-       .enable_reg = I2CCLKCTRL_REG,
-       .rate = 13000000,
-       .enable = clk_reg_enable,
-       .disable = clk_reg_disable,
-};
-
-static struct clk i2c2_ck = {
-       .name = "i2c2_ck",
-       .parent = &per_ck,
-       .flags = NEEDS_INITIALIZATION | FIXED_RATE,
-       .enable_shift = 2,
-       .enable_reg = USB_OTG_CLKCTRL_REG,
-       .rate = 13000000,
-       .enable = clk_reg_enable,
-       .disable = clk_reg_disable,
-};
-
-static struct clk spi0_ck = {
-       .name = "spi0_ck",
-       .parent = &hclk_ck,
-       .flags = NEEDS_INITIALIZATION,
-       .round_rate = &on_off_round_rate,
-       .set_rate = &on_off_set_rate,
-       .enable_shift = 0,
-       .enable_reg = SPICTRL_REG,
-};
-
-static struct clk spi1_ck = {
-       .name = "spi1_ck",
-       .parent = &hclk_ck,
-       .flags = NEEDS_INITIALIZATION,
-       .round_rate = &on_off_round_rate,
-       .set_rate = &on_off_set_rate,
-       .enable_shift = 4,
-       .enable_reg = SPICTRL_REG,
-};
-
-static struct clk dma_ck = {
-       .name = "dma_ck",
-       .parent = &hclk_ck,
-       .round_rate = &on_off_round_rate,
-       .set_rate = &on_off_set_rate,
-       .enable_shift = 0,
-       .enable_reg = DMACLKCTRL_REG,
-};
-
-static struct clk uart3_ck = {
-       .name = "uart3_ck",
-       .parent = &per_ck,
-       .flags = NEEDS_INITIALIZATION,
-       .round_rate = &on_off_round_rate,
-       .set_rate = &on_off_set_rate,
-       .rate = 1,
-       .enable_shift = 0,
-       .enable_reg = UARTCLKCTRL_REG,
-};
-
-static struct clk uart4_ck = {
-       .name = "uart4_ck",
-       .parent = &per_ck,
-       .flags = NEEDS_INITIALIZATION,
-       .round_rate = &on_off_round_rate,
-       .set_rate = &on_off_set_rate,
-       .enable_shift = 1,
-       .enable_reg = UARTCLKCTRL_REG,
-};
-
-static struct clk uart5_ck = {
-       .name = "uart5_ck",
-       .parent = &per_ck,
-       .flags = NEEDS_INITIALIZATION,
-       .round_rate = &on_off_round_rate,
-       .set_rate = &on_off_set_rate,
-       .rate = 1,
-       .enable_shift = 2,
-       .enable_reg = UARTCLKCTRL_REG,
-};
-
-static struct clk uart6_ck = {
-       .name = "uart6_ck",
-       .parent = &per_ck,
-       .flags = NEEDS_INITIALIZATION,
-       .round_rate = &on_off_round_rate,
-       .set_rate = &on_off_set_rate,
-       .enable_shift = 3,
-       .enable_reg = UARTCLKCTRL_REG,
-};
-
-static struct clk wdt_ck = {
-       .name = "wdt_ck",
-       .parent = &per_ck,
-       .flags = NEEDS_INITIALIZATION,
-       .enable_shift = 0,
-       .enable_reg = TIMCLKCTRL_REG,
-       .enable = clk_reg_enable,
-       .disable = clk_reg_disable,
-};
-
-/* These clocks are visible outside this module
- * and can be initialized
- */
-static struct clk *onchip_clks[] __initdata = {
-       &ck_13MHz,
-       &ck_pll1,
-       &ck_pll4,
-       &ck_pll5,
-       &ck_pll3,
-       &vfp9_ck,
-       &m2hclk_ck,
-       &hclk_ck,
-       &dma_ck,
-       &flash_ck,
-       &dum_ck,
-       &keyscan_ck,
-       &pwm1_ck,
-       &pwm2_ck,
-       &jpeg_ck,
-       &ms_ck,
-       &touch_ck,
-       &i2c0_ck,
-       &i2c1_ck,
-       &i2c2_ck,
-       &spi0_ck,
-       &spi1_ck,
-       &uart3_ck,
-       &uart4_ck,
-       &uart5_ck,
-       &uart6_ck,
-       &wdt_ck,
-};
-
-static struct clk_lookup onchip_clkreg[] = {
-       { .clk = &ck_13MHz,     .con_id = "ck_13MHz"    },
-       { .clk = &ck_pll1,      .con_id = "ck_pll1"     },
-       { .clk = &ck_pll4,      .con_id = "ck_pll4"     },
-       { .clk = &ck_pll5,      .con_id = "ck_pll5"     },
-       { .clk = &ck_pll3,      .con_id = "ck_pll3"     },
-       { .clk = &vfp9_ck,      .con_id = "vfp9_ck"     },
-       { .clk = &m2hclk_ck,    .con_id = "m2hclk_ck"   },
-       { .clk = &hclk_ck,      .con_id = "hclk_ck"     },
-       { .clk = &dma_ck,       .con_id = "dma_ck"      },
-       { .clk = &flash_ck,     .con_id = "flash_ck"    },
-       { .clk = &dum_ck,       .con_id = "dum_ck"      },
-       { .clk = &keyscan_ck,   .con_id = "keyscan_ck"  },
-       { .clk = &pwm1_ck,      .con_id = "pwm1_ck"     },
-       { .clk = &pwm2_ck,      .con_id = "pwm2_ck"     },
-       { .clk = &jpeg_ck,      .con_id = "jpeg_ck"     },
-       { .clk = &ms_ck,        .con_id = "ms_ck"       },
-       { .clk = &touch_ck,     .con_id = "touch_ck"    },
-       { .clk = &i2c0_ck,      .dev_id = "pnx-i2c.0"   },
-       { .clk = &i2c1_ck,      .dev_id = "pnx-i2c.1"   },
-       { .clk = &i2c2_ck,      .dev_id = "pnx-i2c.2"   },
-       { .clk = &spi0_ck,      .con_id = "spi0_ck"     },
-       { .clk = &spi1_ck,      .con_id = "spi1_ck"     },
-       { .clk = &uart3_ck,     .con_id = "uart3_ck"    },
-       { .clk = &uart4_ck,     .con_id = "uart4_ck"    },
-       { .clk = &uart5_ck,     .con_id = "uart5_ck"    },
-       { .clk = &uart6_ck,     .con_id = "uart6_ck"    },
-       { .clk = &wdt_ck,       .dev_id = "pnx4008-watchdog" },
-};
-
-static void local_clk_disable(struct clk *clk)
-{
-       if (WARN_ON(clk->usecount == 0))
-               return;
-
-       if (!(--clk->usecount)) {
-               if (clk->disable)
-                       clk->disable(clk);
-               else if (!(clk->flags & FIXED_RATE) && clk->rate && clk->set_rate)
-                       clk->set_rate(clk, 0);
-               if (clk->parent)
-                       local_clk_disable(clk->parent);
-       }
-}
-
-static int local_clk_enable(struct clk *clk)
-{
-       int ret = 0;
-
-       if (clk->usecount == 0) {
-               if (clk->parent) {
-                       ret = local_clk_enable(clk->parent);
-                       if (ret != 0)
-                               goto out;
-               }
-
-               if (clk->enable)
-                       ret = clk->enable(clk);
-               else if (!(clk->flags & FIXED_RATE) && !clk->rate && clk->set_rate
-                           && clk->user_rate)
-                       ret = clk->set_rate(clk, clk->user_rate);
-
-               if (ret != 0 && clk->parent) {
-                       local_clk_disable(clk->parent);
-                       goto out;
-               }
-
-               clk->usecount++;
-       }
-out:
-       return ret;
-}
-
-static int local_set_rate(struct clk *clk, u32 rate)
-{
-       int ret = -EINVAL;
-       if (clk->set_rate) {
-
-               if (clk->user_rate == clk->rate && clk->parent->rate) {
-                       /* if clock enabled or rate not set */
-                       clk->user_rate = clk->round_rate(clk, rate);
-                       ret = clk->set_rate(clk, clk->user_rate);
-               } else
-                       clk->user_rate = clk->round_rate(clk, rate);
-               ret = 0;
-       }
-       return ret;
-}
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-       int ret = -EINVAL;
-
-       if (clk->flags & FIXED_RATE)
-               goto out;
-
-       clock_lock();
-       if ((clk->flags & PARENT_SET_RATE) && clk->parent) {
-
-               clk->user_rate = clk->round_rate(clk, rate);
-               /* parent clock needs to be refreshed
-                  for the setting to take effect */
-       } else {
-               ret = local_set_rate(clk, rate);
-       }
-       ret = 0;
-       clock_unlock();
-
-out:
-       return ret;
-}
-
-EXPORT_SYMBOL(clk_set_rate);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-       unsigned long ret;
-       clock_lock();
-       ret = clk->rate;
-       clock_unlock();
-       return ret;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-int clk_enable(struct clk *clk)
-{
-       int ret;
-
-       clock_lock();
-       ret = local_clk_enable(clk);
-       clock_unlock();
-       return ret;
-}
-
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-       clock_lock();
-       local_clk_disable(clk);
-       clock_unlock();
-}
-
-EXPORT_SYMBOL(clk_disable);
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-       long ret;
-       clock_lock();
-       if (clk->round_rate)
-               ret = clk->round_rate(clk, rate);
-       else
-               ret = clk->rate;
-       clock_unlock();
-       return ret;
-}
-
-EXPORT_SYMBOL(clk_round_rate);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-       int ret = -ENODEV;
-       if (!clk->set_parent)
-               goto out;
-
-       clock_lock();
-       ret = clk->set_parent(clk, parent);
-       if (!ret)
-               clk->parent = parent;
-       clock_unlock();
-
-out:
-       return ret;
-}
-
-EXPORT_SYMBOL(clk_set_parent);
-
-static int __init clk_init(void)
-{
-       struct clk **clkp;
-
-       /* Disable autoclocking, as it doesn't seem to work */
-       __raw_writel(0xff, AUTOCLK_CTRL);
-
-       for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
-            clkp++) {
-               struct clk *clk = *clkp;
-               if (clk->flags & NEEDS_INITIALIZATION) {
-                       if (clk->set_rate) {
-                               clk->user_rate = clk->rate;
-                               local_set_rate(clk, clk->user_rate);
-                               if (clk->set_parent)
-                                       clk->set_parent(clk, clk->parent);
-                       }
-                       if (clk->enable && clk->usecount)
-                               clk->enable(clk);
-                       if (clk->disable && !clk->usecount)
-                               clk->disable(clk);
-               }
-               pr_debug("%s: clock %s, rate %ld\n",
-                       __func__, clk->name, clk->rate);
-       }
-
-       local_clk_enable(&ck_pll4);
-
-       /* if ck_13MHz is not used, disable it. */
-       if (ck_13MHz.usecount == 0)
-               local_clk_disable(&ck_13MHz);
-
-       /* Disable autoclocking */
-       __raw_writeb(0xff, AUTOCLK_CTRL);
-
-       clkdev_add_table(onchip_clkreg, ARRAY_SIZE(onchip_clkreg));
-
-       return 0;
-}
-
-arch_initcall(clk_init);
diff --git a/arch/arm/mach-pnx4008/clock.h b/arch/arm/mach-pnx4008/clock.h
deleted file mode 100644 (file)
index 39720d6..0000000
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/clock.h
- *
- * Clock control driver for PNX4008 - internal header file
- *
- * Author: Vitaly Wool <source@mvista.com>
- *
- * 2006 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ARCH_ARM_PNX4008_CLOCK_H__
-#define __ARCH_ARM_PNX4008_CLOCK_H__
-
-struct clk {
-       const char *name;
-       struct clk *parent;
-       struct clk *propagate_next;
-       u32 rate;
-       u32 user_rate;
-       s8 usecount;
-       u32 flags;
-       u32 scale_reg;
-       u8 enable_shift;
-       u32 enable_reg;
-       u8 enable_shift1;
-       u32 enable_reg1;
-       u32 parent_switch_reg;
-       u32(*round_rate) (struct clk *, u32);
-       int (*set_rate) (struct clk *, u32);
-       int (*set_parent) (struct clk * clk, struct clk * parent);
-       int (*enable)(struct clk *);
-       void (*disable)(struct clk *);
-};
-
-/* Flags */
-#define RATE_PROPAGATES      (1<<0)
-#define NEEDS_INITIALIZATION (1<<1)
-#define PARENT_SET_RATE      (1<<2)
-#define FIXED_RATE           (1<<3)
-
-#endif
diff --git a/arch/arm/mach-pnx4008/core.c b/arch/arm/mach-pnx4008/core.c
deleted file mode 100644 (file)
index a00d2f1..0000000
+++ /dev/null
@@ -1,290 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/core.c
- *
- * PNX4008 core startup code
- *
- * Authors: Vitaly Wool, Dmitry Chigirev,
- * Grigory Tolstolytkin, Dmitry Pervushin <source@mvista.com>
- *
- * Based on reference code received from Philips:
- * Copyright (C) 2003 Philips Semiconductors
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/serial_8250.h>
-#include <linux/device.h>
-#include <linux/spi/spi.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/system_misc.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-
-#include <mach/irq.h>
-#include <mach/clock.h>
-#include <mach/dma.h>
-
-struct resource spipnx_0_resources[] = {
-       {
-               .start = PNX4008_SPI1_BASE,
-               .end = PNX4008_SPI1_BASE + SZ_4K,
-               .flags = IORESOURCE_MEM,
-       }, {
-               .start = PER_SPI1_REC_XMIT,
-               .flags = IORESOURCE_DMA,
-       }, {
-               .start = SPI1_INT,
-               .flags = IORESOURCE_IRQ,
-       }, {
-               .flags = 0,
-       },
-};
-
-struct resource spipnx_1_resources[] = {
-       {
-               .start = PNX4008_SPI2_BASE,
-               .end = PNX4008_SPI2_BASE + SZ_4K,
-               .flags = IORESOURCE_MEM,
-       }, {
-               .start = PER_SPI2_REC_XMIT,
-               .flags = IORESOURCE_DMA,
-       }, {
-               .start = SPI2_INT,
-               .flags = IORESOURCE_IRQ,
-       }, {
-               .flags = 0,
-       }
-};
-
-static struct spi_board_info spi_board_info[] __initdata = {
-       {
-               .modalias       = "m25p80",
-               .max_speed_hz   = 1000000,
-               .bus_num        = 1,
-               .chip_select    = 0,
-       },
-};
-
-static struct platform_device spipnx_1 = {
-       .name = "spipnx",
-       .id = 1,
-       .num_resources = ARRAY_SIZE(spipnx_0_resources),
-       .resource = spipnx_0_resources,
-       .dev = {
-               .coherent_dma_mask = 0xFFFFFFFF,
-               },
-};
-
-static struct platform_device spipnx_2 = {
-       .name = "spipnx",
-       .id = 2,
-       .num_resources = ARRAY_SIZE(spipnx_1_resources),
-       .resource = spipnx_1_resources,
-       .dev = {
-               .coherent_dma_mask = 0xFFFFFFFF,
-               },
-};
-
-static struct plat_serial8250_port platform_serial_ports[] = {
-       {
-               .membase = (void *)__iomem(IO_ADDRESS(PNX4008_UART5_BASE)),
-               .mapbase = (unsigned long)PNX4008_UART5_BASE,
-               .irq = IIR5_INT,
-               .uartclk = PNX4008_UART_CLK,
-               .regshift = 2,
-               .iotype = UPIO_MEM,
-               .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | UPF_SKIP_TEST,
-       },
-       {
-               .membase = (void *)__iomem(IO_ADDRESS(PNX4008_UART3_BASE)),
-               .mapbase = (unsigned long)PNX4008_UART3_BASE,
-               .irq = IIR3_INT,
-               .uartclk = PNX4008_UART_CLK,
-               .regshift = 2,
-               .iotype = UPIO_MEM,
-               .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | UPF_SKIP_TEST,
-        },
-       {}
-};
-
-static struct platform_device serial_device = {
-       .name = "serial8250",
-       .id = PLAT8250_DEV_PLATFORM,
-       .dev = {
-               .platform_data = &platform_serial_ports,
-       },
-};
-
-static struct platform_device nand_flash_device = {
-       .name = "pnx4008-flash",
-       .id = -1,
-       .dev = {
-               .coherent_dma_mask = 0xFFFFFFFF,
-       },
-};
-
-/* The dmamask must be set for OHCI to work */
-static u64 ohci_dmamask = ~(u32) 0;
-
-static struct resource ohci_resources[] = {
-       {
-               .start = IO_ADDRESS(PNX4008_USB_CONFIG_BASE),
-               .end = IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0x100),
-               .flags = IORESOURCE_MEM,
-       }, {
-               .start = USB_HOST_INT,
-               .flags = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device ohci_device = {
-       .name = "pnx4008-usb-ohci",
-       .id = -1,
-       .dev = {
-               .dma_mask = &ohci_dmamask,
-               .coherent_dma_mask = 0xffffffff,
-               },
-       .num_resources = ARRAY_SIZE(ohci_resources),
-       .resource = ohci_resources,
-};
-
-static struct platform_device sdum_device = {
-       .name = "pnx4008-sdum",
-       .id = 0,
-       .dev = {
-               .coherent_dma_mask = 0xffffffff,
-       },
-};
-
-static struct platform_device rgbfb_device = {
-       .name = "pnx4008-rgbfb",
-       .id = 0,
-       .dev = {
-               .coherent_dma_mask = 0xffffffff,
-       }
-};
-
-struct resource watchdog_resources[] = {
-       {
-               .start = PNX4008_WDOG_BASE,
-               .end = PNX4008_WDOG_BASE + SZ_4K - 1,
-               .flags = IORESOURCE_MEM,
-       },
-};
-
-static struct platform_device watchdog_device = {
-       .name = "pnx4008-watchdog",
-       .id = -1,
-       .num_resources = ARRAY_SIZE(watchdog_resources),
-       .resource = watchdog_resources,
-};
-
-static struct platform_device *devices[] __initdata = {
-       &spipnx_1,
-       &spipnx_2,
-       &serial_device,
-       &ohci_device,
-       &nand_flash_device,
-       &sdum_device,
-       &rgbfb_device,
-       &watchdog_device,
-};
-
-
-extern void pnx4008_uart_init(void);
-
-static void __init pnx4008_init(void)
-{
-       /*disable all START interrupt sources,
-          and clear all START interrupt flags */
-       __raw_writel(0, START_INT_ER_REG(SE_PIN_BASE_INT));
-       __raw_writel(0, START_INT_ER_REG(SE_INT_BASE_INT));
-       __raw_writel(0xffffffff, START_INT_RSR_REG(SE_PIN_BASE_INT));
-       __raw_writel(0xffffffff, START_INT_RSR_REG(SE_INT_BASE_INT));
-
-       platform_add_devices(devices, ARRAY_SIZE(devices));
-       spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
-       /* Switch on the UART clocks */
-       pnx4008_uart_init();
-}
-
-static struct map_desc pnx4008_io_desc[] __initdata = {
-       {
-               .virtual        = IO_ADDRESS(PNX4008_IRAM_BASE),
-               .pfn            = __phys_to_pfn(PNX4008_IRAM_BASE),
-               .length         = SZ_64K,
-               .type           = MT_DEVICE,
-       }, {
-               .virtual        = IO_ADDRESS(PNX4008_NDF_FLASH_BASE),
-               .pfn            = __phys_to_pfn(PNX4008_NDF_FLASH_BASE),
-               .length         = SZ_1M - SZ_128K,
-               .type           = MT_DEVICE,
-       }, {
-               .virtual        = IO_ADDRESS(PNX4008_JPEG_CONFIG_BASE),
-               .pfn            = __phys_to_pfn(PNX4008_JPEG_CONFIG_BASE),
-               .length         = SZ_128K * 3,
-               .type           = MT_DEVICE,
-       }, {
-               .virtual        = IO_ADDRESS(PNX4008_DMA_CONFIG_BASE),
-               .pfn            = __phys_to_pfn(PNX4008_DMA_CONFIG_BASE),
-               .length         = SZ_1M,
-               .type           = MT_DEVICE,
-       }, {
-               .virtual        = IO_ADDRESS(PNX4008_AHB2FAB_BASE),
-               .pfn            = __phys_to_pfn(PNX4008_AHB2FAB_BASE),
-               .length         = SZ_1M,
-               .type           = MT_DEVICE,
-       },
-};
-
-void __init pnx4008_map_io(void)
-{
-       iotable_init(pnx4008_io_desc, ARRAY_SIZE(pnx4008_io_desc));
-}
-
-static void pnx4008_restart(char mode, const char *cmd)
-{
-       soft_restart(0);
-}
-
-#ifdef CONFIG_PM
-extern int pnx4008_pm_init(void);
-#else
-static inline int pnx4008_pm_init(void) { return 0; }
-#endif
-
-void __init pnx4008_init_late(void)
-{
-       pnx4008_pm_init();
-}
-
-extern struct sys_timer pnx4008_timer;
-
-MACHINE_START(PNX4008, "Philips PNX4008")
-       /* Maintainer: MontaVista Software Inc. */
-       .atag_offset            = 0x100,
-       .map_io                 = pnx4008_map_io,
-       .init_irq               = pnx4008_init_irq,
-       .init_machine           = pnx4008_init,
-       .init_late              = pnx4008_init_late,
-       .timer                  = &pnx4008_timer,
-       .restart                = pnx4008_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pnx4008/dma.c b/arch/arm/mach-pnx4008/dma.c
deleted file mode 100644 (file)
index a4739e9..0000000
+++ /dev/null
@@ -1,1105 +0,0 @@
-/*
- *  linux/arch/arm/mach-pnx4008/dma.c
- *
- *  PNX4008 DMA registration and IRQ dispatching
- *
- *  Author:    Vitaly Wool
- *  Copyright: MontaVista Software Inc. (c) 2005
- *
- *  Based on the code from Nicolas Pitre
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/dma-mapping.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/gfp.h>
-
-#include <mach/hardware.h>
-#include <mach/dma.h>
-#include <asm/dma-mapping.h>
-#include <mach/clock.h>
-
-static struct dma_channel {
-       char *name;
-       void (*irq_handler) (int, int, void *);
-       void *data;
-       struct pnx4008_dma_ll *ll;
-       u32 ll_dma;
-       void *target_addr;
-       int target_id;
-} dma_channels[MAX_DMA_CHANNELS];
-
-static struct ll_pool {
-       void *vaddr;
-       void *cur;
-       dma_addr_t dma_addr;
-       int count;
-} ll_pool;
-
-static DEFINE_SPINLOCK(ll_lock);
-
-struct pnx4008_dma_ll *pnx4008_alloc_ll_entry(dma_addr_t * ll_dma)
-{
-       struct pnx4008_dma_ll *ll = NULL;
-       unsigned long flags;
-
-       spin_lock_irqsave(&ll_lock, flags);
-       if (ll_pool.count > 4) { /* can give one more */
-               ll = *(struct pnx4008_dma_ll **) ll_pool.cur;
-               *ll_dma = ll_pool.dma_addr + ((void *)ll - ll_pool.vaddr);
-               *(void **)ll_pool.cur = **(void ***)ll_pool.cur;
-               memset(ll, 0, sizeof(*ll));
-               ll_pool.count--;
-       }
-       spin_unlock_irqrestore(&ll_lock, flags);
-
-       return ll;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_alloc_ll_entry);
-
-void pnx4008_free_ll_entry(struct pnx4008_dma_ll * ll, dma_addr_t ll_dma)
-{
-       unsigned long flags;
-
-       if (ll) {
-               if ((unsigned long)((long)ll - (long)ll_pool.vaddr) > 0x4000) {
-                       printk(KERN_ERR "Trying to free entry not allocated by DMA\n");
-                       BUG();
-               }
-
-               if (ll->flags & DMA_BUFFER_ALLOCATED)
-                       ll->free(ll->alloc_data);
-
-               spin_lock_irqsave(&ll_lock, flags);
-               *(long *)ll = *(long *)ll_pool.cur;
-               *(long *)ll_pool.cur = (long)ll;
-               ll_pool.count++;
-               spin_unlock_irqrestore(&ll_lock, flags);
-       }
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_free_ll_entry);
-
-void pnx4008_free_ll(u32 ll_dma, struct pnx4008_dma_ll * ll)
-{
-       struct pnx4008_dma_ll *ptr;
-       u32 dma;
-
-       while (ll) {
-               dma = ll->next_dma;
-               ptr = ll->next;
-               pnx4008_free_ll_entry(ll, ll_dma);
-
-               ll_dma = dma;
-               ll = ptr;
-       }
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_free_ll);
-
-static int dma_channels_requested = 0;
-
-static inline void dma_increment_usage(void)
-{
-       if (!dma_channels_requested++) {
-               struct clk *clk = clk_get(0, "dma_ck");
-               if (!IS_ERR(clk)) {
-                       clk_set_rate(clk, 1);
-                       clk_put(clk);
-               }
-               pnx4008_config_dma(-1, -1, 1);
-       }
-}
-static inline void dma_decrement_usage(void)
-{
-       if (!--dma_channels_requested) {
-               struct clk *clk = clk_get(0, "dma_ck");
-               if (!IS_ERR(clk)) {
-                       clk_set_rate(clk, 0);
-                       clk_put(clk);
-               }
-               pnx4008_config_dma(-1, -1, 0);
-
-       }
-}
-
-static DEFINE_SPINLOCK(dma_lock);
-
-static inline void pnx4008_dma_lock(void)
-{
-       spin_lock_irq(&dma_lock);
-}
-
-static inline void pnx4008_dma_unlock(void)
-{
-       spin_unlock_irq(&dma_lock);
-}
-
-#define VALID_CHANNEL(c)       (((c) >= 0) && ((c) < MAX_DMA_CHANNELS))
-
-int pnx4008_request_channel(char *name, int ch,
-                           void (*irq_handler) (int, int, void *), void *data)
-{
-       int i, found = 0;
-
-       /* basic sanity checks */
-       if (!name || (ch != -1 && !VALID_CHANNEL(ch)))
-               return -EINVAL;
-
-       pnx4008_dma_lock();
-
-       /* try grabbing a DMA channel with the requested priority */
-       for (i = MAX_DMA_CHANNELS - 1; i >= 0; i--) {
-               if (!dma_channels[i].name && (ch == -1 || ch == i)) {
-                       found = 1;
-                       break;
-               }
-       }
-
-       if (found) {
-               dma_increment_usage();
-               dma_channels[i].name = name;
-               dma_channels[i].irq_handler = irq_handler;
-               dma_channels[i].data = data;
-               dma_channels[i].ll = NULL;
-               dma_channels[i].ll_dma = 0;
-       } else {
-               printk(KERN_WARNING "No more available DMA channels for %s\n",
-                      name);
-               i = -ENODEV;
-       }
-
-       pnx4008_dma_unlock();
-       return i;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_request_channel);
-
-void pnx4008_free_channel(int ch)
-{
-       if (!dma_channels[ch].name) {
-               printk(KERN_CRIT
-                      "%s: trying to free channel %d which is already freed\n",
-                      __func__, ch);
-               return;
-       }
-
-       pnx4008_dma_lock();
-       pnx4008_free_ll(dma_channels[ch].ll_dma, dma_channels[ch].ll);
-       dma_channels[ch].ll = NULL;
-       dma_decrement_usage();
-
-       dma_channels[ch].name = NULL;
-       pnx4008_dma_unlock();
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_free_channel);
-
-int pnx4008_config_dma(int ahb_m1_be, int ahb_m2_be, int enable)
-{
-       unsigned long dma_cfg = __raw_readl(DMAC_CONFIG);
-
-       switch (ahb_m1_be) {
-       case 0:
-               dma_cfg &= ~(1 << 1);
-               break;
-       case 1:
-               dma_cfg |= (1 << 1);
-               break;
-       default:
-               break;
-       }
-
-       switch (ahb_m2_be) {
-       case 0:
-               dma_cfg &= ~(1 << 2);
-               break;
-       case 1:
-               dma_cfg |= (1 << 2);
-               break;
-       default:
-               break;
-       }
-
-       switch (enable) {
-       case 0:
-               dma_cfg &= ~(1 << 0);
-               break;
-       case 1:
-               dma_cfg |= (1 << 0);
-               break;
-       default:
-               break;
-       }
-
-       pnx4008_dma_lock();
-       __raw_writel(dma_cfg, DMAC_CONFIG);
-       pnx4008_dma_unlock();
-
-       return 0;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_config_dma);
-
-int pnx4008_dma_pack_control(const struct pnx4008_dma_ch_ctrl * ch_ctrl,
-                            unsigned long *ctrl)
-{
-       int i = 0, dbsize, sbsize, err = 0;
-
-       if (!ctrl || !ch_ctrl) {
-               err = -EINVAL;
-               goto out;
-       }
-
-       *ctrl = 0;
-
-       switch (ch_ctrl->tc_mask) {
-       case 0:
-               break;
-       case 1:
-               *ctrl |= (1 << 31);
-               break;
-
-       default:
-               err = -EINVAL;
-               goto out;
-       }
-
-       switch (ch_ctrl->cacheable) {
-       case 0:
-               break;
-       case 1:
-               *ctrl |= (1 << 30);
-               break;
-
-       default:
-               err = -EINVAL;
-               goto out;
-       }
-       switch (ch_ctrl->bufferable) {
-       case 0:
-               break;
-       case 1:
-               *ctrl |= (1 << 29);
-               break;
-
-       default:
-               err = -EINVAL;
-               goto out;
-       }
-       switch (ch_ctrl->priv_mode) {
-       case 0:
-               break;
-       case 1:
-               *ctrl |= (1 << 28);
-               break;
-
-       default:
-               err = -EINVAL;
-               goto out;
-       }
-       switch (ch_ctrl->di) {
-       case 0:
-               break;
-       case 1:
-               *ctrl |= (1 << 27);
-               break;
-
-       default:
-               err = -EINVAL;
-               goto out;
-       }
-       switch (ch_ctrl->si) {
-       case 0:
-               break;
-       case 1:
-               *ctrl |= (1 << 26);
-               break;
-
-       default:
-               err = -EINVAL;
-               goto out;
-       }
-       switch (ch_ctrl->dest_ahb1) {
-       case 0:
-               break;
-       case 1:
-               *ctrl |= (1 << 25);
-               break;
-
-       default:
-               err = -EINVAL;
-               goto out;
-       }
-       switch (ch_ctrl->src_ahb1) {
-       case 0:
-               break;
-       case 1:
-               *ctrl |= (1 << 24);
-               break;
-
-       default:
-               err = -EINVAL;
-               goto out;
-       }
-       switch (ch_ctrl->dwidth) {
-       case WIDTH_BYTE:
-               *ctrl &= ~(7 << 21);
-               break;
-       case WIDTH_HWORD:
-               *ctrl &= ~(7 << 21);
-               *ctrl |= (1 << 21);
-               break;
-       case WIDTH_WORD:
-               *ctrl &= ~(7 << 21);
-               *ctrl |= (2 << 21);
-               break;
-
-       default:
-               err = -EINVAL;
-               goto out;
-       }
-       switch (ch_ctrl->swidth) {
-       case WIDTH_BYTE:
-               *ctrl &= ~(7 << 18);
-               break;
-       case WIDTH_HWORD:
-               *ctrl &= ~(7 << 18);
-               *ctrl |= (1 << 18);
-               break;
-       case WIDTH_WORD:
-               *ctrl &= ~(7 << 18);
-               *ctrl |= (2 << 18);
-               break;
-
-       default:
-               err = -EINVAL;
-               goto out;
-       }
-       dbsize = ch_ctrl->dbsize;
-       while (!(dbsize & 1)) {
-               i++;
-               dbsize >>= 1;
-       }
-       if (ch_ctrl->dbsize != 1 || i > 8 || i == 1) {
-               err = -EINVAL;
-               goto out;
-       } else if (i > 1)
-               i--;
-       *ctrl &= ~(7 << 15);
-       *ctrl |= (i << 15);
-
-       sbsize = ch_ctrl->sbsize;
-       while (!(sbsize & 1)) {
-               i++;
-               sbsize >>= 1;
-       }
-       if (ch_ctrl->sbsize != 1 || i > 8 || i == 1) {
-               err = -EINVAL;
-               goto out;
-       } else if (i > 1)
-               i--;
-       *ctrl &= ~(7 << 12);
-       *ctrl |= (i << 12);
-
-       if (ch_ctrl->tr_size > 0x7ff) {
-               err = -E2BIG;
-               goto out;
-       }
-       *ctrl &= ~0x7ff;
-       *ctrl |= ch_ctrl->tr_size & 0x7ff;
-
-out:
-       return err;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_pack_control);
-
-int pnx4008_dma_parse_control(unsigned long ctrl,
-                             struct pnx4008_dma_ch_ctrl * ch_ctrl)
-{
-       int err = 0;
-
-       if (!ch_ctrl) {
-               err = -EINVAL;
-               goto out;
-       }
-
-       ch_ctrl->tr_size = ctrl & 0x7ff;
-       ctrl >>= 12;
-
-       ch_ctrl->sbsize = 1 << (ctrl & 7);
-       if (ch_ctrl->sbsize > 1)
-               ch_ctrl->sbsize <<= 1;
-       ctrl >>= 3;
-
-       ch_ctrl->dbsize = 1 << (ctrl & 7);
-       if (ch_ctrl->dbsize > 1)
-               ch_ctrl->dbsize <<= 1;
-       ctrl >>= 3;
-
-       switch (ctrl & 7) {
-       case 0:
-               ch_ctrl->swidth = WIDTH_BYTE;
-               break;
-       case 1:
-               ch_ctrl->swidth = WIDTH_HWORD;
-               break;
-       case 2:
-               ch_ctrl->swidth = WIDTH_WORD;
-               break;
-       default:
-               err = -EINVAL;
-               goto out;
-       }
-       ctrl >>= 3;
-
-       switch (ctrl & 7) {
-       case 0:
-               ch_ctrl->dwidth = WIDTH_BYTE;
-               break;
-       case 1:
-               ch_ctrl->dwidth = WIDTH_HWORD;
-               break;
-       case 2:
-               ch_ctrl->dwidth = WIDTH_WORD;
-               break;
-       default:
-               err = -EINVAL;
-               goto out;
-       }
-       ctrl >>= 3;
-
-       ch_ctrl->src_ahb1 = ctrl & 1;
-       ctrl >>= 1;
-
-       ch_ctrl->dest_ahb1 = ctrl & 1;
-       ctrl >>= 1;
-
-       ch_ctrl->si = ctrl & 1;
-       ctrl >>= 1;
-
-       ch_ctrl->di = ctrl & 1;
-       ctrl >>= 1;
-
-       ch_ctrl->priv_mode = ctrl & 1;
-       ctrl >>= 1;
-
-       ch_ctrl->bufferable = ctrl & 1;
-       ctrl >>= 1;
-
-       ch_ctrl->cacheable = ctrl & 1;
-       ctrl >>= 1;
-
-       ch_ctrl->tc_mask = ctrl & 1;
-
-out:
-       return err;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_parse_control);
-
-int pnx4008_dma_pack_config(const struct pnx4008_dma_ch_config * ch_cfg,
-                           unsigned long *cfg)
-{
-       int err = 0;
-
-       if (!cfg || !ch_cfg) {
-               err = -EINVAL;
-               goto out;
-       }
-
-       *cfg = 0;
-
-       switch (ch_cfg->halt) {
-       case 0:
-               break;
-       case 1:
-               *cfg |= (1 << 18);
-               break;
-
-       default:
-               err = -EINVAL;
-               goto out;
-       }
-       switch (ch_cfg->active) {
-       case 0:
-               break;
-       case 1:
-               *cfg |= (1 << 17);
-               break;
-
-       default:
-               err = -EINVAL;
-               goto out;
-       }
-       switch (ch_cfg->lock) {
-       case 0:
-               break;
-       case 1:
-               *cfg |= (1 << 16);
-               break;
-
-       default:
-               err = -EINVAL;
-               goto out;
-       }
-       switch (ch_cfg->itc) {
-       case 0:
-               break;
-       case 1:
-               *cfg |= (1 << 15);
-               break;
-
-       default:
-               err = -EINVAL;
-               goto out;
-       }
-       switch (ch_cfg->ie) {
-       case 0:
-               break;
-       case 1:
-               *cfg |= (1 << 14);
-               break;
-
-       default:
-               err = -EINVAL;
-               goto out;
-       }
-       switch (ch_cfg->flow_cntrl) {
-       case FC_MEM2MEM_DMA:
-               *cfg &= ~(7 << 11);
-               break;
-       case FC_MEM2PER_DMA:
-               *cfg &= ~(7 << 11);
-               *cfg |= (1 << 11);
-               break;
-       case FC_PER2MEM_DMA:
-               *cfg &= ~(7 << 11);
-               *cfg |= (2 << 11);
-               break;
-       case FC_PER2PER_DMA:
-               *cfg &= ~(7 << 11);
-               *cfg |= (3 << 11);
-               break;
-       case FC_PER2PER_DPER:
-               *cfg &= ~(7 << 11);
-               *cfg |= (4 << 11);
-               break;
-       case FC_MEM2PER_PER:
-               *cfg &= ~(7 << 11);
-               *cfg |= (5 << 11);
-               break;
-       case FC_PER2MEM_PER:
-               *cfg &= ~(7 << 11);
-               *cfg |= (6 << 11);
-               break;
-       case FC_PER2PER_SPER:
-               *cfg |= (7 << 11);
-               break;
-
-       default:
-               err = -EINVAL;
-               goto out;
-       }
-       *cfg &= ~(0x1f << 6);
-       *cfg |= ((ch_cfg->dest_per & 0x1f) << 6);
-
-       *cfg &= ~(0x1f << 1);
-       *cfg |= ((ch_cfg->src_per & 0x1f) << 1);
-
-out:
-       return err;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_pack_config);
-
-int pnx4008_dma_parse_config(unsigned long cfg,
-                            struct pnx4008_dma_ch_config * ch_cfg)
-{
-       int err = 0;
-
-       if (!ch_cfg) {
-               err = -EINVAL;
-               goto out;
-       }
-
-       cfg >>= 1;
-
-       ch_cfg->src_per = cfg & 0x1f;
-       cfg >>= 5;
-
-       ch_cfg->dest_per = cfg & 0x1f;
-       cfg >>= 5;
-
-       switch (cfg & 7) {
-       case 0:
-               ch_cfg->flow_cntrl = FC_MEM2MEM_DMA;
-               break;
-       case 1:
-               ch_cfg->flow_cntrl = FC_MEM2PER_DMA;
-               break;
-       case 2:
-               ch_cfg->flow_cntrl = FC_PER2MEM_DMA;
-               break;
-       case 3:
-               ch_cfg->flow_cntrl = FC_PER2PER_DMA;
-               break;
-       case 4:
-               ch_cfg->flow_cntrl = FC_PER2PER_DPER;
-               break;
-       case 5:
-               ch_cfg->flow_cntrl = FC_MEM2PER_PER;
-               break;
-       case 6:
-               ch_cfg->flow_cntrl = FC_PER2MEM_PER;
-               break;
-       case 7:
-               ch_cfg->flow_cntrl = FC_PER2PER_SPER;
-       }
-       cfg >>= 3;
-
-       ch_cfg->ie = cfg & 1;
-       cfg >>= 1;
-
-       ch_cfg->itc = cfg & 1;
-       cfg >>= 1;
-
-       ch_cfg->lock = cfg & 1;
-       cfg >>= 1;
-
-       ch_cfg->active = cfg & 1;
-       cfg >>= 1;
-
-       ch_cfg->halt = cfg & 1;
-
-out:
-       return err;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_parse_config);
-
-void pnx4008_dma_split_head_entry(struct pnx4008_dma_config * config,
-                                 struct pnx4008_dma_ch_ctrl * ctrl)
-{
-       int new_len = ctrl->tr_size, num_entries = 0;
-       int old_len = new_len;
-       int src_width, dest_width, count = 1;
-
-       switch (ctrl->swidth) {
-       case WIDTH_BYTE:
-               src_width = 1;
-               break;
-       case WIDTH_HWORD:
-               src_width = 2;
-               break;
-       case WIDTH_WORD:
-               src_width = 4;
-               break;
-       default:
-               return;
-       }
-
-       switch (ctrl->dwidth) {
-       case WIDTH_BYTE:
-               dest_width = 1;
-               break;
-       case WIDTH_HWORD:
-               dest_width = 2;
-               break;
-       case WIDTH_WORD:
-               dest_width = 4;
-               break;
-       default:
-               return;
-       }
-
-       while (new_len > 0x7FF) {
-               num_entries++;
-               new_len = (ctrl->tr_size + num_entries) / (num_entries + 1);
-       }
-       if (num_entries != 0) {
-               struct pnx4008_dma_ll *ll = NULL;
-               config->ch_ctrl &= ~0x7ff;
-               config->ch_ctrl |= new_len;
-               if (!config->is_ll) {
-                       config->is_ll = 1;
-                       while (num_entries) {
-                               if (!ll) {
-                                       config->ll =
-                                           pnx4008_alloc_ll_entry(&config->
-                                                                  ll_dma);
-                                       ll = config->ll;
-                               } else {
-                                       ll->next =
-                                           pnx4008_alloc_ll_entry(&ll->
-                                                                  next_dma);
-                                       ll = ll->next;
-                               }
-
-                               if (ctrl->si)
-                                       ll->src_addr =
-                                           config->src_addr +
-                                           src_width * new_len * count;
-                               else
-                                       ll->src_addr = config->src_addr;
-                               if (ctrl->di)
-                                       ll->dest_addr =
-                                           config->dest_addr +
-                                           dest_width * new_len * count;
-                               else
-                                       ll->dest_addr = config->dest_addr;
-                               ll->ch_ctrl = config->ch_ctrl & 0x7fffffff;
-                               ll->next_dma = 0;
-                               ll->next = NULL;
-                               num_entries--;
-                               count++;
-                       }
-               } else {
-                       struct pnx4008_dma_ll *ll_old = config->ll;
-                       unsigned long ll_dma_old = config->ll_dma;
-                       while (num_entries) {
-                               if (!ll) {
-                                       config->ll =
-                                           pnx4008_alloc_ll_entry(&config->
-                                                                  ll_dma);
-                                       ll = config->ll;
-                               } else {
-                                       ll->next =
-                                           pnx4008_alloc_ll_entry(&ll->
-                                                                  next_dma);
-                                       ll = ll->next;
-                               }
-
-                               if (ctrl->si)
-                                       ll->src_addr =
-                                           config->src_addr +
-                                           src_width * new_len * count;
-                               else
-                                       ll->src_addr = config->src_addr;
-                               if (ctrl->di)
-                                       ll->dest_addr =
-                                           config->dest_addr +
-                                           dest_width * new_len * count;
-                               else
-                                       ll->dest_addr = config->dest_addr;
-                               ll->ch_ctrl = config->ch_ctrl & 0x7fffffff;
-                               ll->next_dma = 0;
-                               ll->next = NULL;
-                               num_entries--;
-                               count++;
-                       }
-                       ll->next_dma = ll_dma_old;
-                       ll->next = ll_old;
-               }
-               /* adjust last length/tc */
-               ll->ch_ctrl = config->ch_ctrl & (~0x7ff);
-               ll->ch_ctrl |= old_len - new_len * (count - 1);
-               config->ch_ctrl &= 0x7fffffff;
-       }
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_split_head_entry);
-
-void pnx4008_dma_split_ll_entry(struct pnx4008_dma_ll * cur_ll,
-                               struct pnx4008_dma_ch_ctrl * ctrl)
-{
-       int new_len = ctrl->tr_size, num_entries = 0;
-       int old_len = new_len;
-       int src_width, dest_width, count = 1;
-
-       switch (ctrl->swidth) {
-       case WIDTH_BYTE:
-               src_width = 1;
-               break;
-       case WIDTH_HWORD:
-               src_width = 2;
-               break;
-       case WIDTH_WORD:
-               src_width = 4;
-               break;
-       default:
-               return;
-       }
-
-       switch (ctrl->dwidth) {
-       case WIDTH_BYTE:
-               dest_width = 1;
-               break;
-       case WIDTH_HWORD:
-               dest_width = 2;
-               break;
-       case WIDTH_WORD:
-               dest_width = 4;
-               break;
-       default:
-               return;
-       }
-
-       while (new_len > 0x7FF) {
-               num_entries++;
-               new_len = (ctrl->tr_size + num_entries) / (num_entries + 1);
-       }
-       if (num_entries != 0) {
-               struct pnx4008_dma_ll *ll = NULL;
-               cur_ll->ch_ctrl &= ~0x7ff;
-               cur_ll->ch_ctrl |= new_len;
-               if (!cur_ll->next) {
-                       while (num_entries) {
-                               if (!ll) {
-                                       cur_ll->next =
-                                           pnx4008_alloc_ll_entry(&cur_ll->
-                                                                  next_dma);
-                                       ll = cur_ll->next;
-                               } else {
-                                       ll->next =
-                                           pnx4008_alloc_ll_entry(&ll->
-                                                                  next_dma);
-                                       ll = ll->next;
-                               }
-
-                               if (ctrl->si)
-                                       ll->src_addr =
-                                           cur_ll->src_addr +
-                                           src_width * new_len * count;
-                               else
-                                       ll->src_addr = cur_ll->src_addr;
-                               if (ctrl->di)
-                                       ll->dest_addr =
-                                           cur_ll->dest_addr +
-                                           dest_width * new_len * count;
-                               else
-                                       ll->dest_addr = cur_ll->dest_addr;
-                               ll->ch_ctrl = cur_ll->ch_ctrl & 0x7fffffff;
-                               ll->next_dma = 0;
-                               ll->next = NULL;
-                               num_entries--;
-                               count++;
-                       }
-               } else {
-                       struct pnx4008_dma_ll *ll_old = cur_ll->next;
-                       unsigned long ll_dma_old = cur_ll->next_dma;
-                       while (num_entries) {
-                               if (!ll) {
-                                       cur_ll->next =
-                                           pnx4008_alloc_ll_entry(&cur_ll->
-                                                                  next_dma);
-                                       ll = cur_ll->next;
-                               } else {
-                                       ll->next =
-                                           pnx4008_alloc_ll_entry(&ll->
-                                                                  next_dma);
-                                       ll = ll->next;
-                               }
-
-                               if (ctrl->si)
-                                       ll->src_addr =
-                                           cur_ll->src_addr +
-                                           src_width * new_len * count;
-                               else
-                                       ll->src_addr = cur_ll->src_addr;
-                               if (ctrl->di)
-                                       ll->dest_addr =
-                                           cur_ll->dest_addr +
-                                           dest_width * new_len * count;
-                               else
-                                       ll->dest_addr = cur_ll->dest_addr;
-                               ll->ch_ctrl = cur_ll->ch_ctrl & 0x7fffffff;
-                               ll->next_dma = 0;
-                               ll->next = NULL;
-                               num_entries--;
-                               count++;
-                       }
-
-                       ll->next_dma = ll_dma_old;
-                       ll->next = ll_old;
-               }
-               /* adjust last length/tc */
-               ll->ch_ctrl = cur_ll->ch_ctrl & (~0x7ff);
-               ll->ch_ctrl |= old_len - new_len * (count - 1);
-               cur_ll->ch_ctrl &= 0x7fffffff;
-       }
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_split_ll_entry);
-
-int pnx4008_config_channel(int ch, struct pnx4008_dma_config * config)
-{
-       if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
-               return -EINVAL;
-
-       pnx4008_dma_lock();
-       __raw_writel(config->src_addr, DMAC_Cx_SRC_ADDR(ch));
-       __raw_writel(config->dest_addr, DMAC_Cx_DEST_ADDR(ch));
-
-       if (config->is_ll)
-               __raw_writel(config->ll_dma, DMAC_Cx_LLI(ch));
-       else
-               __raw_writel(0, DMAC_Cx_LLI(ch));
-
-       __raw_writel(config->ch_ctrl, DMAC_Cx_CONTROL(ch));
-       __raw_writel(config->ch_cfg, DMAC_Cx_CONFIG(ch));
-       pnx4008_dma_unlock();
-
-       return 0;
-
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_config_channel);
-
-int pnx4008_channel_get_config(int ch, struct pnx4008_dma_config * config)
-{
-       if (!VALID_CHANNEL(ch) || !dma_channels[ch].name || !config)
-               return -EINVAL;
-
-       pnx4008_dma_lock();
-       config->ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
-       config->ch_ctrl = __raw_readl(DMAC_Cx_CONTROL(ch));
-
-       config->ll_dma = __raw_readl(DMAC_Cx_LLI(ch));
-       config->is_ll = config->ll_dma ? 1 : 0;
-
-       config->src_addr = __raw_readl(DMAC_Cx_SRC_ADDR(ch));
-       config->dest_addr = __raw_readl(DMAC_Cx_DEST_ADDR(ch));
-       pnx4008_dma_unlock();
-
-       return 0;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_channel_get_config);
-
-int pnx4008_dma_ch_enable(int ch)
-{
-       unsigned long ch_cfg;
-
-       if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
-               return -EINVAL;
-
-       pnx4008_dma_lock();
-       ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
-       ch_cfg |= 1;
-       __raw_writel(ch_cfg, DMAC_Cx_CONFIG(ch));
-       pnx4008_dma_unlock();
-
-       return 0;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_ch_enable);
-
-int pnx4008_dma_ch_disable(int ch)
-{
-       unsigned long ch_cfg;
-
-       if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
-               return -EINVAL;
-
-       pnx4008_dma_lock();
-       ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
-       ch_cfg &= ~1;
-       __raw_writel(ch_cfg, DMAC_Cx_CONFIG(ch));
-       pnx4008_dma_unlock();
-
-       return 0;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_ch_disable);
-
-int pnx4008_dma_ch_enabled(int ch)
-{
-       unsigned long ch_cfg;
-
-       if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
-               return -EINVAL;
-
-       pnx4008_dma_lock();
-       ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
-       pnx4008_dma_unlock();
-
-       return ch_cfg & 1;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_ch_enabled);
-
-static irqreturn_t dma_irq_handler(int irq, void *dev_id)
-{
-       int i;
-       unsigned long dint = __raw_readl(DMAC_INT_STAT);
-       unsigned long tcint = __raw_readl(DMAC_INT_TC_STAT);
-       unsigned long eint = __raw_readl(DMAC_INT_ERR_STAT);
-       unsigned long i_bit;
-
-       for (i = MAX_DMA_CHANNELS - 1; i >= 0; i--) {
-               i_bit = 1 << i;
-               if (dint & i_bit) {
-                       struct dma_channel *channel = &dma_channels[i];
-
-                       if (channel->name && channel->irq_handler) {
-                               int cause = 0;
-
-                               if (eint & i_bit)
-                                       cause |= DMA_ERR_INT;
-                               if (tcint & i_bit)
-                                       cause |= DMA_TC_INT;
-                               channel->irq_handler(i, cause, channel->data);
-                       } else {
-                               /*
-                                * IRQ for an unregistered DMA channel
-                                */
-                               printk(KERN_WARNING
-                                      "spurious IRQ for DMA channel %d\n", i);
-                       }
-                       if (tcint & i_bit)
-                               __raw_writel(i_bit, DMAC_INT_TC_CLEAR);
-                       if (eint & i_bit)
-                               __raw_writel(i_bit, DMAC_INT_ERR_CLEAR);
-               }
-       }
-       return IRQ_HANDLED;
-}
-
-static int __init pnx4008_dma_init(void)
-{
-       int ret, i;
-
-       ret = request_irq(DMA_INT, dma_irq_handler, 0, "DMA", NULL);
-       if (ret) {
-               printk(KERN_CRIT "Wow!  Can't register IRQ for DMA\n");
-               goto out;
-       }
-
-       ll_pool.count = 0x4000 / sizeof(struct pnx4008_dma_ll);
-       ll_pool.cur = ll_pool.vaddr =
-           dma_alloc_coherent(NULL, ll_pool.count * sizeof(struct pnx4008_dma_ll),
-                              &ll_pool.dma_addr, GFP_KERNEL);
-
-       if (!ll_pool.vaddr) {
-               ret = -ENOMEM;
-               free_irq(DMA_INT, NULL);
-               goto out;
-       }
-
-       for (i = 0; i < ll_pool.count - 1; i++) {
-               void **addr = ll_pool.vaddr + i * sizeof(struct pnx4008_dma_ll);
-               *addr = (void *)addr + sizeof(struct pnx4008_dma_ll);
-       }
-       *(long *)(ll_pool.vaddr +
-                 (ll_pool.count - 1) * sizeof(struct pnx4008_dma_ll)) =
-           (long)ll_pool.vaddr;
-
-       __raw_writel(1, DMAC_CONFIG);
-
-out:
-       return ret;
-}
-arch_initcall(pnx4008_dma_init);
diff --git a/arch/arm/mach-pnx4008/gpio.c b/arch/arm/mach-pnx4008/gpio.c
deleted file mode 100644 (file)
index d3e71d3..0000000
+++ /dev/null
@@ -1,328 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/gpio.c
- *
- * PNX4008 GPIO driver
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * Based on reference code by Iwo Mergler and Z.Tabaaloute from Philips:
- * Copyright (c) 2005 Koninklijke Philips Electronics N.V.
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
-#include <mach/gpio-pnx4008.h>
-
-/* register definitions */
-#define PIO_VA_BASE    IO_ADDRESS(PNX4008_PIO_BASE)
-
-#define PIO_INP_STATE  (0x00U)
-#define PIO_OUTP_SET   (0x04U)
-#define PIO_OUTP_CLR   (0x08U)
-#define PIO_OUTP_STATE (0x0CU)
-#define PIO_DRV_SET    (0x10U)
-#define PIO_DRV_CLR    (0x14U)
-#define PIO_DRV_STATE  (0x18U)
-#define PIO_SDINP_STATE        (0x1CU)
-#define PIO_SDOUTP_SET (0x20U)
-#define PIO_SDOUTP_CLR (0x24U)
-#define PIO_MUX_SET    (0x28U)
-#define PIO_MUX_CLR    (0x2CU)
-#define PIO_MUX_STATE  (0x30U)
-
-static inline void gpio_lock(void)
-{
-       local_irq_disable();
-}
-
-static inline void gpio_unlock(void)
-{
-       local_irq_enable();
-}
-
-/* Inline functions */
-static inline int gpio_read_bit(u32 reg, int gpio)
-{
-       u32 bit, val;
-       int ret = -EFAULT;
-
-       if (gpio < 0)
-               goto out;
-
-       bit = GPIO_BIT(gpio);
-       if (bit) {
-               val = __raw_readl(PIO_VA_BASE + reg);
-               ret = (val & bit) ? 1 : 0;
-       }
-out:
-       return ret;
-}
-
-static inline int gpio_set_bit(u32 reg, int gpio)
-{
-       u32 bit, val;
-       int ret = -EFAULT;
-
-       if (gpio < 0)
-               goto out;
-
-       bit = GPIO_BIT(gpio);
-       if (bit) {
-               val = __raw_readl(PIO_VA_BASE + reg);
-               val |= bit;
-               __raw_writel(val, PIO_VA_BASE + reg);
-               ret = 0;
-       }
-out:
-       return ret;
-}
-
-/* Very simple access control, bitmap for allocated/free */
-static unsigned long access_map[4];
-#define INP_INDEX      0
-#define OUTP_INDEX     1
-#define GPIO_INDEX     2
-#define MUX_INDEX      3
-
-/*GPIO to Input Mapping */
-static short gpio_to_inp_map[32] = {
-       -1, -1, -1, -1, -1, -1, -1, -1,
-       -1, -1, -1, -1, -1, -1, -1, -1,
-       -1, -1, -1, -1, -1, -1, -1, -1,
-       -1, 10, 11, 12, 13, 14, 24, -1
-};
-
-/*GPIO to Mux Mapping */
-static short gpio_to_mux_map[32] = {
-       -1, -1, -1, -1, -1, -1, -1, -1,
-       -1, -1, -1, -1, -1, -1, -1, -1,
-       -1, -1, -1, -1, -1, -1, -1, -1,
-       -1, -1, -1, 0, 1, 4, 5, -1
-};
-
-/*Output to Mux Mapping */
-static short outp_to_mux_map[32] = {
-       -1, -1, -1, 6, -1, -1, -1, -1,
-       -1, -1, -1, -1, -1, -1, -1, -1,
-       -1, -1, -1, -1, -1, 2, -1, -1,
-       -1, -1, -1, -1, -1, -1, -1, -1
-};
-
-int pnx4008_gpio_register_pin(unsigned short pin)
-{
-       unsigned long bit = GPIO_BIT(pin);
-       int ret = -EBUSY;       /* Already in use */
-
-       gpio_lock();
-
-       if (GPIO_ISBID(pin)) {
-               if (access_map[GPIO_INDEX] & bit)
-                       goto out;
-               access_map[GPIO_INDEX] |= bit;
-
-       } else if (GPIO_ISRAM(pin)) {
-               if (access_map[GPIO_INDEX] & bit)
-                       goto out;
-               access_map[GPIO_INDEX] |= bit;
-
-       } else if (GPIO_ISMUX(pin)) {
-               if (access_map[MUX_INDEX] & bit)
-                       goto out;
-               access_map[MUX_INDEX] |= bit;
-
-       } else if (GPIO_ISOUT(pin)) {
-               if (access_map[OUTP_INDEX] & bit)
-                       goto out;
-               access_map[OUTP_INDEX] |= bit;
-
-       } else if (GPIO_ISIN(pin)) {
-               if (access_map[INP_INDEX] & bit)
-                       goto out;
-               access_map[INP_INDEX] |= bit;
-       } else
-               goto out;
-       ret = 0;
-
-out:
-       gpio_unlock();
-       return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_register_pin);
-
-int pnx4008_gpio_unregister_pin(unsigned short pin)
-{
-       unsigned long bit = GPIO_BIT(pin);
-       int ret = -EFAULT;      /* Not registered */
-
-       gpio_lock();
-
-       if (GPIO_ISBID(pin)) {
-               if (~access_map[GPIO_INDEX] & bit)
-                       goto out;
-               access_map[GPIO_INDEX] &= ~bit;
-       } else if (GPIO_ISRAM(pin)) {
-               if (~access_map[GPIO_INDEX] & bit)
-                       goto out;
-               access_map[GPIO_INDEX] &= ~bit;
-       } else if (GPIO_ISMUX(pin)) {
-               if (~access_map[MUX_INDEX] & bit)
-                       goto out;
-               access_map[MUX_INDEX] &= ~bit;
-       } else if (GPIO_ISOUT(pin)) {
-               if (~access_map[OUTP_INDEX] & bit)
-                       goto out;
-               access_map[OUTP_INDEX] &= ~bit;
-       } else if (GPIO_ISIN(pin)) {
-               if (~access_map[INP_INDEX] & bit)
-                       goto out;
-               access_map[INP_INDEX] &= ~bit;
-       } else
-               goto out;
-       ret = 0;
-
-out:
-       gpio_unlock();
-       return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_unregister_pin);
-
-unsigned long pnx4008_gpio_read_pin(unsigned short pin)
-{
-       unsigned long ret = -EFAULT;
-       int gpio = GPIO_BIT_MASK(pin);
-       gpio_lock();
-       if (GPIO_ISOUT(pin)) {
-               ret = gpio_read_bit(PIO_OUTP_STATE, gpio);
-       } else if (GPIO_ISRAM(pin)) {
-               if (gpio_read_bit(PIO_DRV_STATE, gpio) == 0) {
-                       ret = gpio_read_bit(PIO_SDINP_STATE, gpio);
-               }
-       } else if (GPIO_ISBID(pin)) {
-               ret = gpio_read_bit(PIO_DRV_STATE, gpio);
-               if (ret > 0)
-                       ret = gpio_read_bit(PIO_OUTP_STATE, gpio);
-               else if (ret == 0)
-                       ret =
-                           gpio_read_bit(PIO_INP_STATE, gpio_to_inp_map[gpio]);
-       } else if (GPIO_ISIN(pin)) {
-               ret = gpio_read_bit(PIO_INP_STATE, gpio);
-       }
-       gpio_unlock();
-       return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_read_pin);
-
-/* Write Value to output */
-int pnx4008_gpio_write_pin(unsigned short pin, int output)
-{
-       int gpio = GPIO_BIT_MASK(pin);
-       int ret = -EFAULT;
-
-       gpio_lock();
-       if (GPIO_ISOUT(pin)) {
-               printk( "writing '%x' to '%x'\n",
-                               gpio, output ? PIO_OUTP_SET : PIO_OUTP_CLR );
-               ret = gpio_set_bit(output ? PIO_OUTP_SET : PIO_OUTP_CLR, gpio);
-       } else if (GPIO_ISRAM(pin)) {
-               if (gpio_read_bit(PIO_DRV_STATE, gpio) > 0)
-                       ret = gpio_set_bit(output ? PIO_SDOUTP_SET :
-                                          PIO_SDOUTP_CLR, gpio);
-       } else if (GPIO_ISBID(pin)) {
-               if (gpio_read_bit(PIO_DRV_STATE, gpio) > 0)
-                       ret = gpio_set_bit(output ? PIO_OUTP_SET :
-                                          PIO_OUTP_CLR, gpio);
-       }
-       gpio_unlock();
-       return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_write_pin);
-
-/* Value = 1 : Set GPIO pin as output */
-/* Value = 0 : Set GPIO pin as input */
-int pnx4008_gpio_set_pin_direction(unsigned short pin, int output)
-{
-       int gpio = GPIO_BIT_MASK(pin);
-       int ret = -EFAULT;
-
-       gpio_lock();
-       if (GPIO_ISBID(pin) || GPIO_ISRAM(pin)) {
-               ret = gpio_set_bit(output ? PIO_DRV_SET : PIO_DRV_CLR, gpio);
-       }
-       gpio_unlock();
-       return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_set_pin_direction);
-
-/* Read GPIO pin direction: 0= pin used as input, 1= pin used as output*/
-int pnx4008_gpio_read_pin_direction(unsigned short pin)
-{
-       int gpio = GPIO_BIT_MASK(pin);
-       int ret = -EFAULT;
-
-       gpio_lock();
-       if (GPIO_ISBID(pin) || GPIO_ISRAM(pin)) {
-               ret = gpio_read_bit(PIO_DRV_STATE, gpio);
-       }
-       gpio_unlock();
-       return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_read_pin_direction);
-
-/* Value = 1 : Set pin to muxed function  */
-/* Value = 0 : Set pin as GPIO */
-int pnx4008_gpio_set_pin_mux(unsigned short pin, int output)
-{
-       int gpio = GPIO_BIT_MASK(pin);
-       int ret = -EFAULT;
-
-       gpio_lock();
-       if (GPIO_ISBID(pin)) {
-               ret =
-                   gpio_set_bit(output ? PIO_MUX_SET : PIO_MUX_CLR,
-                                gpio_to_mux_map[gpio]);
-       } else if (GPIO_ISOUT(pin)) {
-               ret =
-                   gpio_set_bit(output ? PIO_MUX_SET : PIO_MUX_CLR,
-                                outp_to_mux_map[gpio]);
-       } else if (GPIO_ISMUX(pin)) {
-               ret = gpio_set_bit(output ? PIO_MUX_SET : PIO_MUX_CLR, gpio);
-       }
-       gpio_unlock();
-       return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_set_pin_mux);
-
-/* Read pin mux function: 0= pin used as GPIO, 1= pin used for muxed function*/
-int pnx4008_gpio_read_pin_mux(unsigned short pin)
-{
-       int gpio = GPIO_BIT_MASK(pin);
-       int ret = -EFAULT;
-
-       gpio_lock();
-       if (GPIO_ISBID(pin)) {
-               ret = gpio_read_bit(PIO_MUX_STATE, gpio_to_mux_map[gpio]);
-       } else if (GPIO_ISOUT(pin)) {
-               ret = gpio_read_bit(PIO_MUX_STATE, outp_to_mux_map[gpio]);
-       } else if (GPIO_ISMUX(pin)) {
-               ret = gpio_read_bit(PIO_MUX_STATE, gpio);
-       }
-       gpio_unlock();
-       return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_read_pin_mux);
diff --git a/arch/arm/mach-pnx4008/i2c.c b/arch/arm/mach-pnx4008/i2c.c
deleted file mode 100644 (file)
index 550cfc2..0000000
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * I2C initialization for PNX4008.
- *
- * Author: Vitaly Wool <vitalywool@gmail.com>
- *
- * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/clk.h>
-#include <linux/i2c.h>
-#include <linux/i2c-pnx.h>
-#include <linux/platform_device.h>
-#include <linux/err.h>
-#include <mach/platform.h>
-#include <mach/irqs.h>
-
-static struct resource i2c0_resources[] = {
-       {
-               .start = PNX4008_I2C1_BASE,
-               .end = PNX4008_I2C1_BASE + SZ_4K - 1,
-               .flags = IORESOURCE_MEM,
-       }, {
-               .start = I2C_1_INT,
-               .end = I2C_1_INT,
-               .flags = IORESOURCE_IRQ,
-       },
-};
-
-static struct resource i2c1_resources[] = {
-       {
-               .start = PNX4008_I2C2_BASE,
-               .end = PNX4008_I2C2_BASE + SZ_4K - 1,
-               .flags = IORESOURCE_MEM,
-       }, {
-               .start = I2C_2_INT,
-               .end = I2C_2_INT,
-               .flags = IORESOURCE_IRQ,
-       },
-};
-
-static struct resource i2c2_resources[] = {
-       {
-               .start = PNX4008_USB_CONFIG_BASE + 0x300,
-               .end = PNX4008_USB_CONFIG_BASE + 0x300 + SZ_4K - 1,
-               .flags = IORESOURCE_MEM,
-       }, {
-               .start = USB_I2C_INT,
-               .end = USB_I2C_INT,
-               .flags = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device i2c0_device = {
-       .name = "pnx-i2c.0",
-       .id = 0,
-       .resource = i2c0_resources,
-       .num_resources = ARRAY_SIZE(i2c0_resources),
-};
-
-static struct platform_device i2c1_device = {
-       .name = "pnx-i2c.1",
-       .id = 1,
-       .resource = i2c1_resources,
-       .num_resources = ARRAY_SIZE(i2c1_resources),
-};
-
-static struct platform_device i2c2_device = {
-       .name = "pnx-i2c.2",
-       .id = 2,
-       .resource = i2c2_resources,
-       .num_resources = ARRAY_SIZE(i2c2_resources),
-};
-
-static struct platform_device *devices[] __initdata = {
-       &i2c0_device,
-       &i2c1_device,
-       &i2c2_device,
-};
-
-void __init pnx4008_register_i2c_devices(void)
-{
-       platform_add_devices(devices, ARRAY_SIZE(devices));
-}
diff --git a/arch/arm/mach-pnx4008/include/mach/clock.h b/arch/arm/mach-pnx4008/include/mach/clock.h
deleted file mode 100644 (file)
index 8d2a5ef..0000000
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/clock.h
- *
- * Clock control driver for PNX4008 - header file
- *
- * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __PNX4008_CLOCK_H__
-#define __PNX4008_CLOCK_H__
-
-struct module;
-struct clk;
-
-#define PWRMAN_VA_BASE         IO_ADDRESS(PNX4008_PWRMAN_BASE)
-#define HCLKDIVCTRL_REG                (PWRMAN_VA_BASE + 0x40)
-#define PWRCTRL_REG            (PWRMAN_VA_BASE + 0x44)
-#define PLLCTRL_REG            (PWRMAN_VA_BASE + 0x48)
-#define OSC13CTRL_REG          (PWRMAN_VA_BASE + 0x4c)
-#define SYSCLKCTRL_REG         (PWRMAN_VA_BASE + 0x50)
-#define HCLKPLLCTRL_REG                (PWRMAN_VA_BASE + 0x58)
-#define USBCTRL_REG            (PWRMAN_VA_BASE + 0x64)
-#define SDRAMCLKCTRL_REG       (PWRMAN_VA_BASE + 0x68)
-#define MSCTRL_REG             (PWRMAN_VA_BASE + 0x80)
-#define BTCLKCTRL              (PWRMAN_VA_BASE + 0x84)
-#define DUMCLKCTRL_REG         (PWRMAN_VA_BASE + 0x90)
-#define I2CCLKCTRL_REG         (PWRMAN_VA_BASE + 0xac)
-#define KEYCLKCTRL_REG         (PWRMAN_VA_BASE + 0xb0)
-#define TSCLKCTRL_REG          (PWRMAN_VA_BASE + 0xb4)
-#define PWMCLKCTRL_REG         (PWRMAN_VA_BASE + 0xb8)
-#define TIMCLKCTRL_REG         (PWRMAN_VA_BASE + 0xbc)
-#define SPICTRL_REG            (PWRMAN_VA_BASE + 0xc4)
-#define FLASHCLKCTRL_REG       (PWRMAN_VA_BASE + 0xc8)
-#define UART3CLK_REG           (PWRMAN_VA_BASE + 0xd0)
-#define UARTCLKCTRL_REG                (PWRMAN_VA_BASE + 0xe4)
-#define DMACLKCTRL_REG         (PWRMAN_VA_BASE + 0xe8)
-#define AUTOCLK_CTRL           (PWRMAN_VA_BASE + 0xec)
-#define JPEGCLKCTRL_REG                (PWRMAN_VA_BASE + 0xfc)
-
-#define AUDIOCONFIG_VA_BASE    IO_ADDRESS(PNX4008_AUDIOCONFIG_BASE)
-#define DSPPLLCTRL_REG         (AUDIOCONFIG_VA_BASE + 0x60)
-#define DSPCLKCTRL_REG         (AUDIOCONFIG_VA_BASE + 0x64)
-#define AUDIOCLKCTRL_REG       (AUDIOCONFIG_VA_BASE + 0x68)
-#define AUDIOPLLCTRL_REG       (AUDIOCONFIG_VA_BASE + 0x6C)
-
-#define USB_OTG_CLKCTRL_REG    IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xff4)
-
-#define VFP9CLKCTRL_REG                IO_ADDRESS(PNX4008_DEBUG_BASE)
-
-#define CLK_RATE_13MHZ 13000
-#define CLK_RATE_1MHZ 1000
-#define CLK_RATE_208MHZ 208000
-#define CLK_RATE_48MHZ 48000
-#define CLK_RATE_32KHZ 32
-
-#define PNX4008_UART_CLK CLK_RATE_13MHZ * 1000 /* in MHz */
-
-#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/debug-macro.S b/arch/arm/mach-pnx4008/include/mach/debug-macro.S
deleted file mode 100644 (file)
index 469d60d..0000000
+++ /dev/null
@@ -1,21 +0,0 @@
-/* arch/arm/mach-pnx4008/include/mach/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-               .macro  addruart, rp, rv, tmp
-               mov     \rp, #0x00090000
-               add     \rv, \rp, #0xf4000000   @ virtual
-               add     \rp, \rp, #0x40000000   @ physical
-               .endm
-
-#define UART_SHIFT     2
-#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-pnx4008/include/mach/dma.h b/arch/arm/mach-pnx4008/include/mach/dma.h
deleted file mode 100644 (file)
index f094bf8..0000000
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- *  arch/arm/mach-pnx4008/include/mach/dma.h
- *
- *  PNX4008 DMA header file
- *
- *  Author:    Vitaly Wool
- *  Copyright: MontaVista Software Inc. (c) 2005
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-
-#include "platform.h"
-
-#define MAX_DMA_CHANNELS       8
-
-#define DMAC_BASE              IO_ADDRESS(PNX4008_DMA_CONFIG_BASE)
-#define DMAC_INT_STAT          (DMAC_BASE + 0x0000)
-#define DMAC_INT_TC_STAT       (DMAC_BASE + 0x0004)
-#define DMAC_INT_TC_CLEAR      (DMAC_BASE + 0x0008)
-#define DMAC_INT_ERR_STAT      (DMAC_BASE + 0x000c)
-#define DMAC_INT_ERR_CLEAR     (DMAC_BASE + 0x0010)
-#define DMAC_SOFT_SREQ         (DMAC_BASE + 0x0024)
-#define DMAC_CONFIG            (DMAC_BASE + 0x0030)
-#define DMAC_Cx_SRC_ADDR(c)    (DMAC_BASE + 0x0100 + (c) * 0x20)
-#define DMAC_Cx_DEST_ADDR(c)   (DMAC_BASE + 0x0104 + (c) * 0x20)
-#define DMAC_Cx_LLI(c)         (DMAC_BASE + 0x0108 + (c) * 0x20)
-#define DMAC_Cx_CONTROL(c)     (DMAC_BASE + 0x010c + (c) * 0x20)
-#define DMAC_Cx_CONFIG(c)      (DMAC_BASE + 0x0110 + (c) * 0x20)
-
-enum {
-       WIDTH_BYTE = 0,
-       WIDTH_HWORD,
-       WIDTH_WORD
-};
-
-enum {
-       FC_MEM2MEM_DMA,
-       FC_MEM2PER_DMA,
-       FC_PER2MEM_DMA,
-       FC_PER2PER_DMA,
-       FC_PER2PER_DPER,
-       FC_MEM2PER_PER,
-       FC_PER2MEM_PER,
-       FC_PER2PER_SPER
-};
-
-enum {
-       DMA_INT_UNKNOWN = 0,
-       DMA_ERR_INT = 1,
-       DMA_TC_INT = 2,
-};
-
-enum {
-       DMA_BUFFER_ALLOCATED = 1,
-       DMA_HAS_LL = 2,
-};
-
-enum {
-       PER_CAM_DMA_1 = 0,
-       PER_NDF_FLASH = 1,
-       PER_MBX_SLAVE_FIFO = 2,
-       PER_SPI2_REC_XMIT = 3,
-       PER_MS_SD_RX_XMIT = 4,
-       PER_HS_UART_1_XMIT = 5,
-       PER_HS_UART_1_RX = 6,
-       PER_HS_UART_2_XMIT = 7,
-       PER_HS_UART_2_RX = 8,
-       PER_HS_UART_7_XMIT = 9,
-       PER_HS_UART_7_RX = 10,
-       PER_SPI1_REC_XMIT = 11,
-       PER_MLC_NDF_SREC = 12,
-       PER_CAM_DMA_2 = 13,
-       PER_PRNG_INFIFO = 14,
-       PER_PRNG_OUTFIFO = 15,
-};
-
-struct pnx4008_dma_ch_ctrl {
-       int tc_mask;
-       int cacheable;
-       int bufferable;
-       int priv_mode;
-       int di;
-       int si;
-       int dest_ahb1;
-       int src_ahb1;
-       int dwidth;
-       int swidth;
-       int dbsize;
-       int sbsize;
-       int tr_size;
-};
-
-struct pnx4008_dma_ch_config {
-       int halt;
-       int active;
-       int lock;
-       int itc;
-       int ie;
-       int flow_cntrl;
-       int dest_per;
-       int src_per;
-};
-
-struct pnx4008_dma_ll {
-       unsigned long src_addr;
-       unsigned long dest_addr;
-       u32 next_dma;
-       unsigned long ch_ctrl;
-       struct pnx4008_dma_ll *next;
-       int flags;
-       void *alloc_data;
-       int (*free) (void *);
-};
-
-struct pnx4008_dma_config {
-       int is_ll;
-       unsigned long src_addr;
-       unsigned long dest_addr;
-       unsigned long ch_ctrl;
-       unsigned long ch_cfg;
-       struct pnx4008_dma_ll *ll;
-       u32 ll_dma;
-       int flags;
-       void *alloc_data;
-       int (*free) (void *);
-};
-
-extern struct pnx4008_dma_ll *pnx4008_alloc_ll_entry(dma_addr_t *);
-extern void pnx4008_free_ll_entry(struct pnx4008_dma_ll *, dma_addr_t);
-extern void pnx4008_free_ll(u32 ll_dma, struct pnx4008_dma_ll *);
-
-extern int pnx4008_request_channel(char *, int,
-                                  void (*)(int, int, void *),
-                                  void *);
-extern void pnx4008_free_channel(int);
-extern int pnx4008_config_dma(int, int, int);
-extern int pnx4008_dma_pack_control(const struct pnx4008_dma_ch_ctrl *,
-                                   unsigned long *);
-extern int pnx4008_dma_parse_control(unsigned long,
-                                    struct pnx4008_dma_ch_ctrl *);
-extern int pnx4008_dma_pack_config(const struct pnx4008_dma_ch_config *,
-                                  unsigned long *);
-extern int pnx4008_dma_parse_config(unsigned long,
-                                   struct pnx4008_dma_ch_config *);
-extern int pnx4008_config_channel(int, struct pnx4008_dma_config *);
-extern int pnx4008_channel_get_config(int, struct pnx4008_dma_config *);
-extern int pnx4008_dma_ch_enable(int);
-extern int pnx4008_dma_ch_disable(int);
-extern int pnx4008_dma_ch_enabled(int);
-extern void pnx4008_dma_split_head_entry(struct pnx4008_dma_config *,
-                                        struct pnx4008_dma_ch_ctrl *);
-extern void pnx4008_dma_split_ll_entry(struct pnx4008_dma_ll *,
-                                      struct pnx4008_dma_ch_ctrl *);
-
-#endif                         /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-pnx4008/include/mach/entry-macro.S b/arch/arm/mach-pnx4008/include/mach/entry-macro.S
deleted file mode 100644 (file)
index 77a5558..0000000
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for PNX4008-based platforms
- *
- * 2005-2006 (c) MontaVista Software, Inc.
- * Author: Vitaly Wool <vwool@ru.mvista.com>
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include "platform.h"
-
-#define IO_BASE         0xF0000000
-#define IO_ADDRESS(x)  (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
-
-#define INTRC_MASK                     0x00
-#define INTRC_RAW_STAT                 0x04
-#define INTRC_STAT                     0x08
-#define INTRC_POLAR                    0x0C
-#define INTRC_ACT_TYPE                 0x10
-#define INTRC_TYPE                     0x14
-
-#define SIC1_BASE_INT   32
-#define SIC2_BASE_INT   64
-
-               .macro  get_irqnr_preamble, base, tmp
-               .endm
-
-               .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-/* decode the MIC interrupt numbers */
-               ldr     \base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
-               ldr     \irqstat, [\base, #INTRC_STAT]
-
-               cmp     \irqstat,#1<<16
-               movhs   \irqnr,#16
-               movlo   \irqnr,#0
-               movhs   \irqstat,\irqstat,lsr#16
-               cmp     \irqstat,#1<<8
-               addhs   \irqnr,\irqnr,#8
-               movhs   \irqstat,\irqstat,lsr#8
-               cmp     \irqstat,#1<<4
-               addhs   \irqnr,\irqnr,#4
-               movhs   \irqstat,\irqstat,lsr#4
-               cmp     \irqstat,#1<<2
-               addhs   \irqnr,\irqnr,#2
-               movhs   \irqstat,\irqstat,lsr#2
-               cmp     \irqstat,#1<<1
-               addhs   \irqnr,\irqnr,#1
-
-/* was there an interrupt ? if not then drop out with EQ status */
-               teq     \irqstat,#0
-               beq     1003f
-
-/* and now check for extended IRQ reasons */
-               cmp     \irqnr,#1
-               bls     1003f
-               cmp     \irqnr,#30
-               blo     1002f
-
-/* IRQ 31,30  : High priority cascade IRQ handle */
-/* read the correct SIC */
-/* decoding status after compare : eq is 30 (SIC1) , ne is 31 (SIC2) */
-/* set the base IRQ number */
-               ldreq   \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
-               moveq  \irqnr,#SIC1_BASE_INT
-               ldrne   \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
-               movne   \irqnr,#SIC2_BASE_INT
-               ldr     \irqstat, [\base, #INTRC_STAT]
-               ldr     \tmp,     [\base, #INTRC_TYPE]
-/* and with inverted mask : low priority interrupts  */
-               and     \irqstat,\irqstat,\tmp
-               b       1004f
-
-1003:
-/* IRQ 1,0  : Low priority cascade IRQ handle */
-/* read the correct SIC */
-/* decoding status after compare : eq is 1 (SIC2) , ne is 0 (SIC1)*/
-/* read the correct SIC */
-/* set the base IRQ number  */
-               ldrne   \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
-               movne   \irqnr,#SIC1_BASE_INT
-               ldreq   \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
-               moveq   \irqnr,#SIC2_BASE_INT
-               ldr     \irqstat, [\base, #INTRC_STAT]
-               ldr     \tmp,     [\base, #INTRC_TYPE]
-/* and with inverted mask : low priority interrupts  */
-               bic     \irqstat,\irqstat,\tmp
-
-1004:
-
-               cmp     \irqstat,#1<<16
-               addhs   \irqnr,\irqnr,#16
-               movhs   \irqstat,\irqstat,lsr#16
-               cmp     \irqstat,#1<<8
-               addhs   \irqnr,\irqnr,#8
-               movhs   \irqstat,\irqstat,lsr#8
-               cmp     \irqstat,#1<<4
-               addhs   \irqnr,\irqnr,#4
-               movhs   \irqstat,\irqstat,lsr#4
-               cmp     \irqstat,#1<<2
-               addhs   \irqnr,\irqnr,#2
-               movhs   \irqstat,\irqstat,lsr#2
-               cmp     \irqstat,#1<<1
-               addhs   \irqnr,\irqnr,#1
-
-
-/* is irqstat not zero */
-
-1002:
-/* we assert that irqstat is not equal to zero and return ne status if true*/
-               teq     \irqstat,#0
-1003:
-               .endm
-
diff --git a/arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h b/arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h
deleted file mode 100644 (file)
index 41027dd..0000000
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h
- *
- * PNX4008 GPIO driver - header file
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * Based on reference code by Iwo Mergler and Z.Tabaaloute from Philips:
- * Copyright (c) 2005 Koninklijke Philips Electronics N.V.
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef _PNX4008_GPIO_H_
-#define _PNX4008_GPIO_H_
-
-
-/* Block numbers */
-#define GPIO_IN                (0)
-#define GPIO_OUT               (0x100)
-#define GPIO_BID               (0x200)
-#define GPIO_RAM               (0x300)
-#define GPIO_MUX               (0x400)
-
-#define GPIO_TYPE_MASK(K) ((K) & 0x700)
-
-/* INPUT GPIOs */
-/* GPI */
-#define GPI_00         (GPIO_IN | 0)
-#define GPI_01         (GPIO_IN | 1)
-#define GPI_02         (GPIO_IN | 2)
-#define GPI_03                 (GPIO_IN | 3)
-#define GPI_04         (GPIO_IN | 4)
-#define GPI_05         (GPIO_IN | 5)
-#define GPI_06         (GPIO_IN | 6)
-#define GPI_07         (GPIO_IN | 7)
-#define GPI_08         (GPIO_IN | 8)
-#define GPI_09         (GPIO_IN | 9)
-#define U1_RX          (GPIO_IN | 15)
-#define U2_HTCS        (GPIO_IN | 16)
-#define U2_RX          (GPIO_IN | 17)
-#define U3_RX          (GPIO_IN | 18)
-#define U4_RX          (GPIO_IN | 19)
-#define U5_RX          (GPIO_IN | 20)
-#define U6_IRRX        (GPIO_IN | 21)
-#define U7_HCTS        (GPIO_IN | 22)
-#define U7_RX          (GPIO_IN | 23)
-/* MISC IN */
-#define SPI1_DATIN     (GPIO_IN | 25)
-#define DISP_SYNC      (GPIO_IN | 26)
-#define SPI2_DATIN     (GPIO_IN | 27)
-#define GPI_11         (GPIO_IN | 28)
-
-#define GPIO_IN_MASK   0x1eff83ff
-
-/* OUTPUT GPIOs */
-/* GPO */
-#define GPO_00         (GPIO_OUT | 0)
-#define GPO_01         (GPIO_OUT | 1)
-#define GPO_02         (GPIO_OUT | 2)
-#define GPO_03                 (GPIO_OUT | 3)
-#define GPO_04         (GPIO_OUT | 4)
-#define GPO_05         (GPIO_OUT | 5)
-#define GPO_06         (GPIO_OUT | 6)
-#define GPO_07         (GPIO_OUT | 7)
-#define GPO_08         (GPIO_OUT | 8)
-#define GPO_09         (GPIO_OUT | 9)
-#define GPO_10         (GPIO_OUT | 10)
-#define GPO_11                 (GPIO_OUT | 11)
-#define GPO_12         (GPIO_OUT | 12)
-#define GPO_13         (GPIO_OUT | 13)
-#define GPO_14         (GPIO_OUT | 14)
-#define GPO_15         (GPIO_OUT | 15)
-#define GPO_16         (GPIO_OUT | 16)
-#define GPO_17                 (GPIO_OUT | 17)
-#define GPO_18         (GPIO_OUT | 18)
-#define GPO_19         (GPIO_OUT | 19)
-#define GPO_20         (GPIO_OUT | 20)
-#define GPO_21         (GPIO_OUT | 21)
-#define GPO_22         (GPIO_OUT | 22)
-#define GPO_23         (GPIO_OUT | 23)
-
-#define GPIO_OUT_MASK   0xffffff
-
-/* BIDIRECTIONAL GPIOs */
-/* RAM pins */
-#define RAM_D19                (GPIO_RAM | 0)
-#define RAM_D20        (GPIO_RAM | 1)
-#define RAM_D21        (GPIO_RAM | 2)
-#define RAM_D22        (GPIO_RAM | 3)
-#define RAM_D23        (GPIO_RAM | 4)
-#define RAM_D24        (GPIO_RAM | 5)
-#define RAM_D25        (GPIO_RAM | 6)
-#define RAM_D26        (GPIO_RAM | 7)
-#define RAM_D27                (GPIO_RAM | 8)
-#define RAM_D28        (GPIO_RAM | 9)
-#define RAM_D29        (GPIO_RAM | 10)
-#define RAM_D30        (GPIO_RAM | 11)
-#define RAM_D31        (GPIO_RAM | 12)
-
-#define GPIO_RAM_MASK   0x1fff
-
-/* I/O pins */
-#define GPIO_00        (GPIO_BID | 25)
-#define GPIO_01        (GPIO_BID | 26)
-#define GPIO_02        (GPIO_BID | 27)
-#define GPIO_03        (GPIO_BID | 28)
-#define GPIO_04        (GPIO_BID | 29)
-#define GPIO_05        (GPIO_BID | 30)
-
-#define GPIO_BID_MASK   0x7e000000
-
-/* Non-GPIO multiplexed PIOs. For multiplexing with GPIO, please use GPIO macros */
-#define GPIO_SDRAM_SEL         (GPIO_MUX | 3)
-
-#define GPIO_MUX_MASK   0x8
-
-/* Extraction/assembly macros */
-#define GPIO_BIT_MASK(K) ((K) & 0x1F)
-#define GPIO_BIT(K) (1 << GPIO_BIT_MASK(K))
-#define GPIO_ISMUX(K) ((GPIO_TYPE_MASK(K) == GPIO_MUX) && (GPIO_BIT(K) & GPIO_MUX_MASK))
-#define GPIO_ISRAM(K) ((GPIO_TYPE_MASK(K) == GPIO_RAM) && (GPIO_BIT(K) & GPIO_RAM_MASK))
-#define GPIO_ISBID(K) ((GPIO_TYPE_MASK(K) == GPIO_BID) && (GPIO_BIT(K) & GPIO_BID_MASK))
-#define GPIO_ISOUT(K) ((GPIO_TYPE_MASK(K) == GPIO_OUT) && (GPIO_BIT(K) & GPIO_OUT_MASK))
-#define GPIO_ISIN(K)  ((GPIO_TYPE_MASK(K) == GPIO_IN) && (GPIO_BIT(K) & GPIO_IN_MASK))
-
-/* Start Enable Pin Interrupts - table 58 page 66 */
-
-#define SE_PIN_BASE_INT   32
-
-#define SE_U7_RX_INT            63
-#define SE_U7_HCTS_INT          62
-#define SE_BT_CLKREQ_INT        61
-#define SE_U6_IRRX_INT          60
-/*59 unused*/
-#define SE_U5_RX_INT            58
-#define SE_GPI_11_INT           57
-#define SE_U3_RX_INT            56
-#define SE_U2_HCTS_INT          55
-#define SE_U2_RX_INT            54
-#define SE_U1_RX_INT            53
-#define SE_DISP_SYNC_INT        52
-/*51 unused*/
-#define SE_SDIO_INT_N           50
-#define SE_MSDIO_START_INT      49
-#define SE_GPI_06_INT           48
-#define SE_GPI_05_INT           47
-#define SE_GPI_04_INT           46
-#define SE_GPI_03_INT           45
-#define SE_GPI_02_INT           44
-#define SE_GPI_01_INT           43
-#define SE_GPI_00_INT           42
-#define SE_SYSCLKEN_PIN_INT     41
-#define SE_SPI1_DATAIN_INT      40
-#define SE_GPI_07_INT           39
-#define SE_SPI2_DATAIN_INT      38
-#define SE_GPI_10_INT           37
-#define SE_GPI_09_INT           36
-#define SE_GPI_08_INT           35
-/*34-32 unused*/
-
-/* Start Enable Internal Interrupts - table 57 page 65 */
-
-#define SE_INT_BASE_INT   0
-
-#define SE_TS_IRQ               31
-#define SE_TS_P_INT             30
-#define SE_TS_AUX_INT           29
-/*27-28 unused*/
-#define SE_USB_AHB_NEED_CLK_INT 26
-#define SE_MSTIMER_INT          25
-#define SE_RTC_INT              24
-#define SE_USB_NEED_CLK_INT     23
-#define SE_USB_INT              22
-#define SE_USB_I2C_INT          21
-#define SE_USB_OTG_TIMER_INT    20
-#define SE_USB_OTG_ATX_INT_N    19
-/*18 unused*/
-#define SE_DSP_GPIO4_INT        17
-#define SE_KEY_IRQ              16
-#define SE_DSP_SLAVEPORT_INT    15
-#define SE_DSP_GPIO1_INT        14
-#define SE_DSP_GPIO0_INT        13
-#define SE_DSP_AHB_INT          12
-/*11-6 unused*/
-#define SE_GPIO_05_INT          5
-#define SE_GPIO_04_INT          4
-#define SE_GPIO_03_INT          3
-#define SE_GPIO_02_INT          2
-#define SE_GPIO_01_INT          1
-#define SE_GPIO_00_INT          0
-
-#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F))
-
-#define START_INT_ER_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_RSR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_SR_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_APR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1)))
-
-extern int pnx4008_gpio_register_pin(unsigned short pin);
-extern int pnx4008_gpio_unregister_pin(unsigned short pin);
-extern unsigned long pnx4008_gpio_read_pin(unsigned short pin);
-extern int pnx4008_gpio_write_pin(unsigned short pin, int output);
-extern int pnx4008_gpio_set_pin_direction(unsigned short pin, int output);
-extern int pnx4008_gpio_read_pin_direction(unsigned short pin);
-extern int pnx4008_gpio_set_pin_mux(unsigned short pin, int output);
-extern int pnx4008_gpio_read_pin_mux(unsigned short pin);
-
-static inline void start_int_umask(u8 irq)
-{
-       __raw_writel(__raw_readl(START_INT_ER_REG(irq)) |
-                    START_INT_REG_BIT(irq), START_INT_ER_REG(irq));
-}
-
-static inline void start_int_mask(u8 irq)
-{
-       __raw_writel(__raw_readl(START_INT_ER_REG(irq)) &
-                    ~START_INT_REG_BIT(irq), START_INT_ER_REG(irq));
-}
-
-static inline void start_int_ack(u8 irq)
-{
-       __raw_writel(START_INT_REG_BIT(irq), START_INT_RSR_REG(irq));
-}
-
-static inline void start_int_set_falling_edge(u8 irq)
-{
-       __raw_writel(__raw_readl(START_INT_APR_REG(irq)) &
-                    ~START_INT_REG_BIT(irq), START_INT_APR_REG(irq));
-}
-
-static inline void start_int_set_rising_edge(u8 irq)
-{
-       __raw_writel(__raw_readl(START_INT_APR_REG(irq)) |
-                    START_INT_REG_BIT(irq), START_INT_APR_REG(irq));
-}
-
-#endif                         /* _PNX4008_GPIO_H_ */
diff --git a/arch/arm/mach-pnx4008/include/mach/hardware.h b/arch/arm/mach-pnx4008/include/mach/hardware.h
deleted file mode 100644 (file)
index 7b98b82..0000000
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/hardware.h
- *
- * Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/sizes.h>
-#include <mach/platform.h>
-
-/* Start of virtual addresses for IO devices */
-#define IO_BASE         0xF0000000
-
-/* This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 */
-#define IO_ADDRESS(x)  (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
-
-#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/irq.h b/arch/arm/mach-pnx4008/include/mach/irq.h
deleted file mode 100644 (file)
index 2a690ca..0000000
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/irq.h
- *
- * PNX4008 IRQ controller driver - header file
- * this one is used in entry-arnv.S as well so it cannot contain C code
- *
- * Copyright (c) 2005 Philips Semiconductors
- * Copyright (c) 2005 MontaVista Software, Inc.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- */
-#ifndef __PNX4008_IRQ_H__
-#define __PNX4008_IRQ_H__
-
-#define MIC_VA_BASE             IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
-#define SIC1_VA_BASE            IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
-#define SIC2_VA_BASE            IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
-
-/* Manual: Chapter 20, page 195 */
-
-#define INTC_BIT(irq) (1<< ((irq) & 0x1F))
-
-#define INTC_ER(irq)    IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x0 + (((irq)&(0x3<<5))<<9)))
-#define INTC_RSR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x4 + (((irq)&(0x3<<5))<<9)))
-#define INTC_SR(irq)    IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x8 + (((irq)&(0x3<<5))<<9)))
-#define INTC_APR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0xC + (((irq)&(0x3<<5))<<9)))
-#define INTC_ATR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x10 + (((irq)&(0x3<<5))<<9)))
-#define INTC_ITR(irq)   IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x14 + (((irq)&(0x3<<5))<<9)))
-
-#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F))
-
-#define START_INT_ER_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_RSR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_SR_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_APR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1)))
-
-extern void __init pnx4008_init_irq(void);
-
-#endif /* __PNX4008_IRQ_H__ */
diff --git a/arch/arm/mach-pnx4008/include/mach/irqs.h b/arch/arm/mach-pnx4008/include/mach/irqs.h
deleted file mode 100644 (file)
index f6b33cf..0000000
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/irqs.h
- *
- * PNX4008 IRQ controller driver - header file
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __PNX4008_IRQS_h__
-#define __PNX4008_IRQS_h__
-
-#define NR_IRQS         96
-
-/*Manual: table 259, page 199*/
-
-/*SUB2 Interrupt Routing (SIC2)*/
-
-#define SIC2_BASE_INT   64
-
-#define CLK_SWITCH_ARM_INT 95  /*manual: Clkswitch ARM  */
-#define CLK_SWITCH_DSP_INT 94  /*manual: ClkSwitch DSP  */
-#define CLK_SWITCH_AUD_INT 93  /*manual: Clkswitch AUD  */
-#define GPI_06_INT         92
-#define GPI_05_INT         91
-#define GPI_04_INT         90
-#define GPI_03_INT         89
-#define GPI_02_INT         88
-#define GPI_01_INT         87
-#define GPI_00_INT         86
-#define BT_CLKREQ_INT      85
-#define SPI1_DATIN_INT     84
-#define U5_RX_INT          83
-#define SDIO_INT_N         82
-#define CAM_HS_INT         81
-#define CAM_VS_INT         80
-#define GPI_07_INT         79
-#define DISP_SYNC_INT      78
-#define DSP_INT8           77
-#define U7_HCTS_INT        76
-#define GPI_10_INT         75
-#define GPI_09_INT         74
-#define GPI_08_INT         73
-#define DSP_INT7           72
-#define U2_HCTS_INT        71
-#define SPI2_DATIN_INT     70
-#define GPIO_05_INT        69
-#define GPIO_04_INT        68
-#define GPIO_03_INT        67
-#define GPIO_02_INT        66
-#define GPIO_01_INT        65
-#define GPIO_00_INT        64
-
-/*Manual: table 258, page 198*/
-
-/*SUB1 Interrupt Routing (SIC1)*/
-
-#define SIC1_BASE_INT   32
-
-#define USB_I2C_INT        63
-#define USB_DEV_HP_INT     62
-#define USB_DEV_LP_INT     61
-#define USB_DEV_DMA_INT    60
-#define USB_HOST_INT       59
-#define USB_OTG_ATX_INT_N  58
-#define USB_OTG_TIMER_INT  57
-#define SW_INT             56
-#define SPI1_INT           55
-#define KEY_IRQ            54
-#define DSP_M_INT          53
-#define RTC_INT            52
-#define I2C_1_INT          51
-#define I2C_2_INT          50
-#define PLL1_LOCK_INT      49
-#define PLL2_LOCK_INT      48
-#define PLL3_LOCK_INT      47
-#define PLL4_LOCK_INT      46
-#define PLL5_LOCK_INT      45
-#define SPI2_INT           44
-#define DSP_INT1           43
-#define DSP_INT2           42
-#define DSP_TDM_INT2       41
-#define TS_AUX_INT         40
-#define TS_IRQ             39
-#define TS_P_INT           38
-#define UOUT1_TO_PAD_INT   37
-#define GPI_11_INT         36
-#define DSP_INT4           35
-#define JTAG_COMM_RX_INT   34
-#define JTAG_COMM_TX_INT   33
-#define DSP_INT3           32
-
-/*Manual: table 257, page 197*/
-
-/*MAIN Interrupt Routing*/
-
-#define MAIN_BASE_INT   0
-
-#define SUB2_FIQ_N         31  /*active low */
-#define SUB1_FIQ_N         30  /*active low */
-#define JPEG_INT           29
-#define DMA_INT            28
-#define MSTIMER_INT        27
-#define IIR1_INT           26
-#define IIR2_INT           25
-#define IIR7_INT           24
-#define DSP_TDM_INT0       23
-#define DSP_TDM_INT1       22
-#define DSP_P_INT          21
-#define DSP_INT0           20
-#define DUM_INT            19
-#define UOUT0_TO_PAD_INT   18
-#define MP4_ENC_INT        17
-#define MP4_DEC_INT        16
-#define SD0_INT            15
-#define MBX_INT            14
-#define SD1_INT            13
-#define MS_INT_N           12
-#define FLASH_INT          11 /*NAND*/
-#define IIR6_INT           10
-#define IIR5_INT           9
-#define IIR4_INT           8
-#define IIR3_INT           7
-#define WATCH_INT          6
-#define HSTIMER_INT        5
-#define ARCH_TIMER_IRQ     HSTIMER_INT
-#define CAM_INT            4
-#define PRNG_INT           3
-#define CRYPTO_INT         2
-#define SUB2_IRQ_N         1   /*active low */
-#define SUB1_IRQ_N         0   /*active low */
-
-#define PNX4008_IRQ_TYPES \
-{                                           /*IRQ #'s: */         \
-IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, /*  0, 1, 2, 3 */     \
-IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /*  4, 5, 6, 7 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /*  8, 9,10,11 */     \
-IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 12,13,14,15 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 16,17,18,19 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 20,21,22,23 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 24,25,26,27 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  /* 28,29,30,31 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 32,33,34,35 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_FALLING, IRQ_TYPE_LEVEL_HIGH, /* 36,37,38,39 */  \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 40,41,42,43 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 44,45,46,47 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  /* 48,49,50,51 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 52,53,54,55 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, /* 56,57,58,59 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 60,61,62,63 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 64,65,66,67 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 68,69,70,71 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 72,73,74,75 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 76,77,78,79 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 80,81,82,83 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 84,85,86,87 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 88,89,90,91 */     \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 92,93,94,95 */     \
-}
-
-/* Start Enable Pin Interrupts - table 58 page 66 */
-
-#define SE_PIN_BASE_INT   32
-
-#define SE_U7_RX_INT            63
-#define SE_U7_HCTS_INT          62
-#define SE_BT_CLKREQ_INT        61
-#define SE_U6_IRRX_INT          60
-/*59 unused*/
-#define SE_U5_RX_INT            58
-#define SE_GPI_11_INT           57
-#define SE_U3_RX_INT            56
-#define SE_U2_HCTS_INT          55
-#define SE_U2_RX_INT            54
-#define SE_U1_RX_INT            53
-#define SE_DISP_SYNC_INT        52
-/*51 unused*/
-#define SE_SDIO_INT_N           50
-#define SE_MSDIO_START_INT      49
-#define SE_GPI_06_INT           48
-#define SE_GPI_05_INT           47
-#define SE_GPI_04_INT           46
-#define SE_GPI_03_INT           45
-#define SE_GPI_02_INT           44
-#define SE_GPI_01_INT           43
-#define SE_GPI_00_INT           42
-#define SE_SYSCLKEN_PIN_INT     41
-#define SE_SPI1_DATAIN_INT      40
-#define SE_GPI_07_INT           39
-#define SE_SPI2_DATAIN_INT      38
-#define SE_GPI_10_INT           37
-#define SE_GPI_09_INT           36
-#define SE_GPI_08_INT           35
-/*34-32 unused*/
-
-/* Start Enable Internal Interrupts - table 57 page 65 */
-
-#define SE_INT_BASE_INT   0
-
-#define SE_TS_IRQ               31
-#define SE_TS_P_INT             30
-#define SE_TS_AUX_INT           29
-/*27-28 unused*/
-#define SE_USB_AHB_NEED_CLK_INT 26
-#define SE_MSTIMER_INT          25
-#define SE_RTC_INT              24
-#define SE_USB_NEED_CLK_INT     23
-#define SE_USB_INT              22
-#define SE_USB_I2C_INT          21
-#define SE_USB_OTG_TIMER_INT    20
-
-#endif /* __PNX4008_IRQS_h__ */
diff --git a/arch/arm/mach-pnx4008/include/mach/param.h b/arch/arm/mach-pnx4008/include/mach/param.h
deleted file mode 100644 (file)
index 6ea02f2..0000000
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- *  arch/arm/mach-pnx4008/include/mach/param.h
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#define HZ 100
diff --git a/arch/arm/mach-pnx4008/include/mach/platform.h b/arch/arm/mach-pnx4008/include/mach/platform.h
deleted file mode 100644 (file)
index 368c2c1..0000000
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/platform.h
- *
- * PNX4008 Base addresses - header file
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * Based on reference code received from Philips:
- * Copyright (C) 2003 Philips Semiconductors
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-
-#ifndef __ASM_ARCH_PLATFORM_H__
-#define __ASM_ARCH_PLATFORM_H__
-
-#define PNX4008_IRAM_BASE              0x08000000
-#define PNX4008_IRAM_SIZE              0x00010000
-#define PNX4008_YUV_SLAVE_BASE         0x10000000
-#define PNX4008_DUM_SLAVE_BASE         0x18000000
-#define PNX4008_NDF_FLASH_BASE         0x20020000
-#define PNX4008_SPI1_BASE              0x20088000
-#define PNX4008_SPI2_BASE              0x20090000
-#define PNX4008_SD_CONFIG_BASE         0x20098000
-#define PNX4008_FLASH_DATA             0x200B0000
-#define PNX4008_MLC_FLASH_BASE         0x200B8000
-#define PNX4008_JPEG_CONFIG_BASE       0x300A0000
-#define PNX4008_DMA_CONFIG_BASE                0x31000000
-#define PNX4008_USB_CONFIG_BASE                0x31020000
-#define PNX4008_SDRAM_CFG_BASE         0x31080000
-#define PNX4008_AHB2FAB_BASE           0x40000000
-#define PNX4008_PWRMAN_BASE            0x40004000
-#define PNX4008_INTCTRLMIC_BASE                0x40008000
-#define PNX4008_INTCTRLSIC1_BASE       0x4000C000
-#define PNX4008_INTCTRLSIC2_BASE       0x40010000
-#define PNX4008_HSUART1_BASE           0x40014000
-#define PNX4008_HSUART2_BASE           0x40018000
-#define PNX4008_HSUART7_BASE           0x4001C000
-#define PNX4008_RTC_BASE               0x40024000
-#define PNX4008_PIO_BASE               0x40028000
-#define PNX4008_MSTIMER_BASE           0x40034000
-#define PNX4008_HSTIMER_BASE           0x40038000
-#define PNX4008_WDOG_BASE              0x4003C000
-#define PNX4008_DEBUG_BASE             0x40040000
-#define PNX4008_TOUCH1_BASE            0x40048000
-#define PNX4008_KEYSCAN_BASE           0x40050000
-#define PNX4008_UARTCTRL_BASE          0x40054000
-#define PNX4008_PWM_BASE               0x4005C000
-#define PNX4008_UART3_BASE             0x40080000
-#define PNX4008_UART4_BASE             0x40088000
-#define PNX4008_UART5_BASE             0x40090000
-#define PNX4008_UART6_BASE             0x40098000
-#define PNX4008_I2C1_BASE              0x400A0000
-#define PNX4008_I2C2_BASE              0x400A8000
-#define PNX4008_MAGICGATE_BASE         0x400B0000
-#define PNX4008_DUMCONF_BASE           0x400B8000
-#define PNX4008_DUM_MAINCFG_BASE               0x400BC000
-#define PNX4008_DSP_BASE               0x400C0000
-#define PNX4008_PROFCOUNTER_BASE       0x400C8000
-#define PNX4008_CRYPTO_BASE            0x400D0000
-#define PNX4008_CAMIFCONF_BASE         0x400D8000
-#define PNX4008_YUV2RGB_BASE           0x400E0000
-#define PNX4008_AUDIOCONFIG_BASE       0x400E8000
-
-#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/pm.h b/arch/arm/mach-pnx4008/include/mach/pm.h
deleted file mode 100644 (file)
index 2fa685b..0000000
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/pm.h
- *
- * PNX4008 Power Management Routiness - header file
- *
- * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __ASM_ARCH_PNX4008_PM_H
-#define __ASM_ARCH_PNX4008_PM_H
-
-#ifndef __ASSEMBLER__
-#include "irq.h"
-#include "irqs.h"
-#include "clock.h"
-
-extern void pnx4008_pm_idle(void);
-extern void pnx4008_pm_suspend(void);
-extern unsigned int pnx4008_cpu_suspend_sz;
-extern void pnx4008_cpu_suspend(void);
-extern unsigned int pnx4008_cpu_standby_sz;
-extern void pnx4008_cpu_standby(void);
-
-extern int pnx4008_startup_pll(struct clk *);
-extern int pnx4008_shutdown_pll(struct clk *);
-
-#endif                         /* ASSEMBLER */
-#endif                         /* __ASM_ARCH_PNX4008_PM_H */
diff --git a/arch/arm/mach-pnx4008/include/mach/timex.h b/arch/arm/mach-pnx4008/include/mach/timex.h
deleted file mode 100644 (file)
index b383c7d..0000000
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/timex.h
- *
- * PNX4008 timers header file
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __PNX4008_TIMEX_H
-#define __PNX4008_TIMEX_H
-
-#define CLOCK_TICK_RATE                1000000
-
-#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/uncompress.h b/arch/arm/mach-pnx4008/include/mach/uncompress.h
deleted file mode 100644 (file)
index bb4751e..0000000
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- *  arch/arm/mach-pnx4008/include/mach/uncompress.h
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2006 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#define UART5_BASE 0x40090000
-
-#define UART5_DR    (*(volatile unsigned char *) (UART5_BASE))
-#define UART5_FR    (*(volatile unsigned char *) (UART5_BASE + 18))
-
-static __inline__ void putc(char c)
-{
-       while (UART5_FR & (1 << 5))
-               barrier();
-
-       UART5_DR = c;
-}
-
-/*
- * This does not append a newline
- */
-static inline void flush(void)
-{
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c
deleted file mode 100644 (file)
index 41e4201..0000000
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/irq.c
- *
- * PNX4008 IRQ controller driver
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * Based on reference code received from Philips:
- * Copyright (C) 2003 Philips Semiconductors
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/map.h>
-#include <mach/irq.h>
-
-static u8 pnx4008_irq_type[NR_IRQS] = PNX4008_IRQ_TYPES;
-
-static void pnx4008_mask_irq(struct irq_data *d)
-{
-       __raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq));        /* mask interrupt */
-}
-
-static void pnx4008_unmask_irq(struct irq_data *d)
-{
-       __raw_writel(__raw_readl(INTC_ER(d->irq)) | INTC_BIT(d->irq), INTC_ER(d->irq)); /* unmask interrupt */
-}
-
-static void pnx4008_mask_ack_irq(struct irq_data *d)
-{
-       __raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq));        /* mask interrupt */
-       __raw_writel(INTC_BIT(d->irq), INTC_SR(d->irq));        /* clear interrupt status */
-}
-
-static int pnx4008_set_irq_type(struct irq_data *d, unsigned int type)
-{
-       switch (type) {
-       case IRQ_TYPE_EDGE_RISING:
-               __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq));       /*edge sensitive */
-               __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq));       /*rising edge */
-               irq_set_handler(d->irq, handle_edge_irq);
-               break;
-       case IRQ_TYPE_EDGE_FALLING:
-               __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq));       /*edge sensitive */
-               __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq));      /*falling edge */
-               irq_set_handler(d->irq, handle_edge_irq);
-               break;
-       case IRQ_TYPE_LEVEL_LOW:
-               __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq));      /*level sensitive */
-               __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq));      /*low level */
-               irq_set_handler(d->irq, handle_level_irq);
-               break;
-       case IRQ_TYPE_LEVEL_HIGH:
-               __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq));      /*level sensitive */
-               __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq));       /* high level */
-               irq_set_handler(d->irq, handle_level_irq);
-               break;
-
-       /* IRQ_TYPE_EDGE_BOTH is not supported */
-       default:
-               printk(KERN_ERR "PNX4008 IRQ: Unsupported irq type %d\n", type);
-               return -1;
-       }
-       return 0;
-}
-
-static struct irq_chip pnx4008_irq_chip = {
-       .irq_ack = pnx4008_mask_ack_irq,
-       .irq_mask = pnx4008_mask_irq,
-       .irq_unmask = pnx4008_unmask_irq,
-       .irq_set_type = pnx4008_set_irq_type,
-};
-
-void __init pnx4008_init_irq(void)
-{
-       unsigned int i;
-
-       /* configure IRQ's */
-       for (i = 0; i < NR_IRQS; i++) {
-               set_irq_flags(i, IRQF_VALID);
-               irq_set_chip(i, &pnx4008_irq_chip);
-               pnx4008_set_irq_type(irq_get_irq_data(i), pnx4008_irq_type[i]);
-       }
-
-       /* configure and enable IRQ 0,1,30,31 (cascade interrupts) */
-       pnx4008_set_irq_type(irq_get_irq_data(SUB1_IRQ_N),
-                            pnx4008_irq_type[SUB1_IRQ_N]);
-       pnx4008_set_irq_type(irq_get_irq_data(SUB2_IRQ_N),
-                            pnx4008_irq_type[SUB2_IRQ_N]);
-       pnx4008_set_irq_type(irq_get_irq_data(SUB1_FIQ_N),
-                            pnx4008_irq_type[SUB1_FIQ_N]);
-       pnx4008_set_irq_type(irq_get_irq_data(SUB2_FIQ_N),
-                            pnx4008_irq_type[SUB2_FIQ_N]);
-
-       /* mask all others */
-       __raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) |
-                       (1 << SUB2_IRQ_N) | (1 << SUB1_IRQ_N),
-               INTC_ER(MAIN_BASE_INT));
-       __raw_writel(0, INTC_ER(SIC1_BASE_INT));
-       __raw_writel(0, INTC_ER(SIC2_BASE_INT));
-}
-
diff --git a/arch/arm/mach-pnx4008/pm.c b/arch/arm/mach-pnx4008/pm.c
deleted file mode 100644 (file)
index 26f8d06..0000000
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/pm.c
- *
- * Power Management driver for PNX4008
- *
- * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/pm.h>
-#include <linux/rtc.h>
-#include <linux/sched.h>
-#include <linux/proc_fs.h>
-#include <linux/suspend.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-
-#include <asm/cacheflush.h>
-
-#include <mach/hardware.h>
-#include <mach/pm.h>
-#include <mach/clock.h>
-
-#define SRAM_VA IO_ADDRESS(PNX4008_IRAM_BASE)
-
-static void *saved_sram;
-
-static struct clk *pll4_clk;
-
-static inline void pnx4008_standby(void)
-{
-       void (*pnx4008_cpu_standby_ptr) (void);
-
-       local_irq_disable();
-       local_fiq_disable();
-
-       clk_disable(pll4_clk);
-
-       /*saving portion of SRAM to be used by suspend function. */
-       memcpy(saved_sram, (void *)SRAM_VA, pnx4008_cpu_standby_sz);
-
-       /*make sure SRAM copy gets physically written into SDRAM.
-          SDRAM will be placed into self-refresh during power down */
-       flush_cache_all();
-
-       /*copy suspend function into SRAM */
-       memcpy((void *)SRAM_VA, pnx4008_cpu_standby, pnx4008_cpu_standby_sz);
-
-       /*do suspend */
-       pnx4008_cpu_standby_ptr = (void *)SRAM_VA;
-       pnx4008_cpu_standby_ptr();
-
-       /*restoring portion of SRAM that was used by suspend function */
-       memcpy((void *)SRAM_VA, saved_sram, pnx4008_cpu_standby_sz);
-
-       clk_enable(pll4_clk);
-
-       local_fiq_enable();
-       local_irq_enable();
-}
-
-static inline void pnx4008_suspend(void)
-{
-       void (*pnx4008_cpu_suspend_ptr) (void);
-
-       local_irq_disable();
-       local_fiq_disable();
-
-       clk_disable(pll4_clk);
-
-       __raw_writel(0xffffffff, START_INT_RSR_REG(SE_PIN_BASE_INT));
-       __raw_writel(0xffffffff, START_INT_RSR_REG(SE_INT_BASE_INT));
-
-       /*saving portion of SRAM to be used by suspend function. */
-       memcpy(saved_sram, (void *)SRAM_VA, pnx4008_cpu_suspend_sz);
-
-       /*make sure SRAM copy gets physically written into SDRAM.
-          SDRAM will be placed into self-refresh during power down */
-       flush_cache_all();
-
-       /*copy suspend function into SRAM */
-       memcpy((void *)SRAM_VA, pnx4008_cpu_suspend, pnx4008_cpu_suspend_sz);
-
-       /*do suspend */
-       pnx4008_cpu_suspend_ptr = (void *)SRAM_VA;
-       pnx4008_cpu_suspend_ptr();
-
-       /*restoring portion of SRAM that was used by suspend function */
-       memcpy((void *)SRAM_VA, saved_sram, pnx4008_cpu_suspend_sz);
-
-       clk_enable(pll4_clk);
-
-       local_fiq_enable();
-       local_irq_enable();
-}
-
-static int pnx4008_pm_enter(suspend_state_t state)
-{
-       switch (state) {
-       case PM_SUSPEND_STANDBY:
-               pnx4008_standby();
-               break;
-       case PM_SUSPEND_MEM:
-               pnx4008_suspend();
-               break;
-       }
-       return 0;
-}
-
-static int pnx4008_pm_valid(suspend_state_t state)
-{
-       return (state == PM_SUSPEND_STANDBY) ||
-              (state == PM_SUSPEND_MEM);
-}
-
-static const struct platform_suspend_ops pnx4008_pm_ops = {
-       .enter = pnx4008_pm_enter,
-       .valid = pnx4008_pm_valid,
-};
-
-int __init pnx4008_pm_init(void)
-{
-       u32 sram_size_to_allocate;
-
-       pll4_clk = clk_get(0, "ck_pll4");
-       if (IS_ERR(pll4_clk)) {
-               printk(KERN_ERR
-                      "PM Suspend cannot acquire ARM(PLL4) clock control\n");
-               return PTR_ERR(pll4_clk);
-       }
-
-       if (pnx4008_cpu_standby_sz > pnx4008_cpu_suspend_sz)
-               sram_size_to_allocate = pnx4008_cpu_standby_sz;
-       else
-               sram_size_to_allocate = pnx4008_cpu_suspend_sz;
-
-       saved_sram = kmalloc(sram_size_to_allocate, GFP_ATOMIC);
-       if (!saved_sram) {
-               printk(KERN_ERR
-                      "PM Suspend: cannot allocate memory to save portion of SRAM\n");
-               clk_put(pll4_clk);
-               return -ENOMEM;
-       }
-
-       suspend_set_ops(&pnx4008_pm_ops);
-       return 0;
-}
diff --git a/arch/arm/mach-pnx4008/serial.c b/arch/arm/mach-pnx4008/serial.c
deleted file mode 100644 (file)
index 374c138..0000000
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- *  linux/arch/arm/mach-pnx4008/serial.c
- *
- *  PNX4008 UART initialization
- *
- *  Copyright: MontaVista Software Inc. (c) 2005
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/io.h>
-
-#include <mach/platform.h>
-#include <mach/hardware.h>
-
-#include <linux/serial_core.h>
-#include <linux/serial_reg.h>
-
-#include <mach/gpio-pnx4008.h>
-#include <mach/clock.h>
-
-#define UART_3         0
-#define UART_4         1
-#define UART_5         2
-#define UART_6         3
-#define UART_UNKNOWN   (-1)
-
-#define UART3_BASE_VA  IO_ADDRESS(PNX4008_UART3_BASE)
-#define UART4_BASE_VA  IO_ADDRESS(PNX4008_UART4_BASE)
-#define UART5_BASE_VA  IO_ADDRESS(PNX4008_UART5_BASE)
-#define UART6_BASE_VA  IO_ADDRESS(PNX4008_UART6_BASE)
-
-#define UART_FCR_OFFSET                8
-#define UART_FIFO_SIZE         64
-
-void pnx4008_uart_init(void)
-{
-       u32 tmp;
-       int i = UART_FIFO_SIZE;
-
-       __raw_writel(0xC1, UART5_BASE_VA + UART_FCR_OFFSET);
-       __raw_writel(0xC1, UART3_BASE_VA + UART_FCR_OFFSET);
-
-       /* Send a NULL to fix the UART HW bug */
-       __raw_writel(0x00, UART5_BASE_VA);
-       __raw_writel(0x00, UART3_BASE_VA);
-
-       while (i--) {
-               tmp = __raw_readl(UART5_BASE_VA);
-               tmp = __raw_readl(UART3_BASE_VA);
-       }
-       __raw_writel(0, UART5_BASE_VA + UART_FCR_OFFSET);
-       __raw_writel(0, UART3_BASE_VA + UART_FCR_OFFSET);
-
-       /* setup wakeup interrupt */
-       start_int_set_rising_edge(SE_U3_RX_INT);
-       start_int_ack(SE_U3_RX_INT);
-       start_int_umask(SE_U3_RX_INT);
-
-       start_int_set_rising_edge(SE_U5_RX_INT);
-       start_int_ack(SE_U5_RX_INT);
-       start_int_umask(SE_U5_RX_INT);
-}
-
diff --git a/arch/arm/mach-pnx4008/sleep.S b/arch/arm/mach-pnx4008/sleep.S
deleted file mode 100644 (file)
index f4eed49..0000000
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * linux/arch/arm/mach-pnx4008/sleep.S
- *
- * PNX4008 support for STOP mode and SDRAM self-refresh
- *
- * Authors: Dmitry Chigirev, Vitaly Wool <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <mach/hardware.h>
-
-#define PWRMAN_VA_BASE IO_ADDRESS(PNX4008_PWRMAN_BASE)
-#define PWR_CTRL_REG_OFFS 0x44
-
-#define SDRAM_CFG_VA_BASE IO_ADDRESS(PNX4008_SDRAM_CFG_BASE)
-#define MPMC_STATUS_REG_OFFS 0x4
-
-               .text
-
-ENTRY(pnx4008_cpu_suspend)
-       @this function should be entered in Direct run mode.
-
-       @ save registers on stack
-       stmfd   sp!, {r0 - r6, lr}
-
-       @ setup Power Manager base address in r4
-       @ and put it's value in r5
-       mov     r4, #(PWRMAN_VA_BASE & 0xff000000)
-       orr     r4, r4, #(PWRMAN_VA_BASE & 0x00ff0000)
-       orr     r4, r4, #(PWRMAN_VA_BASE & 0x0000ff00)
-       orr     r4, r4, #(PWRMAN_VA_BASE & 0x000000ff)
-       ldr     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-       @ setup SDRAM controller base address in r2
-       @ and put it's value in r3
-       mov     r2, #(SDRAM_CFG_VA_BASE & 0xff000000)
-       orr     r2, r2, #(SDRAM_CFG_VA_BASE & 0x00ff0000)
-       orr     r2, r2, #(SDRAM_CFG_VA_BASE & 0x0000ff00)
-       orr     r2, r2, #(SDRAM_CFG_VA_BASE & 0x000000ff)
-       ldr     r3, [r2, #MPMC_STATUS_REG_OFFS] @extra read - HW bug workaround
-
-       @ clear SDRAM self-refresh bit latch
-       and     r5, r5, #(~(1 << 8))
-       @ clear SDRAM self-refresh bit
-       and     r5, r5, #(~(1 << 9))
-       str     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-       @ do save current bit settings in r1
-       mov     r1, r5
-
-       @ set SDRAM self-refresh bit
-       orr     r5, r5, #(1 << 9)
-       str     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-       @ set SDRAM self-refresh bit latch
-       orr     r5, r5, #(1 << 8)
-       str     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-       @ clear SDRAM self-refresh bit latch
-       and     r5, r5, #(~(1 << 8))
-       str     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-       @ clear SDRAM self-refresh bit
-       and     r5, r5, #(~(1 << 9))
-       str     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-       @ wait for SDRAM to get into self-refresh mode
-2:     ldr     r3, [r2, #MPMC_STATUS_REG_OFFS]
-       tst     r3, #(1 << 2)
-       beq     2b
-
-       @ to prepare SDRAM to get out of self-refresh mode after wakeup
-       orr     r5, r5, #(1 << 7)
-       str     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-       @ do enter stop mode
-       orr     r5, r5, #(1 << 0)
-       str     r5, [r4, #PWR_CTRL_REG_OFFS]
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-
-       @ sleeping now...
-
-       @ coming out of STOP mode into Direct Run mode
-       @ clear STOP mode and SDRAM self-refresh bits
-       str     r1, [r4, #PWR_CTRL_REG_OFFS]
-
-       @ wait for SDRAM to get out self-refresh mode
-3:     ldr     r3, [r2, #MPMC_STATUS_REG_OFFS]
-       tst     r3, #5
-       bne     3b
-
-       @ restore regs and return
-       ldmfd   sp!, {r0 - r6, pc}
-
-ENTRY(pnx4008_cpu_suspend_sz)
-       .word   . - pnx4008_cpu_suspend
-
-ENTRY(pnx4008_cpu_standby)
-       @ save registers on stack
-       stmfd   sp!, {r0 - r6, lr}
-
-       @ setup Power Manager base address in r4
-       @ and put it's value in r5
-       mov     r4, #(PWRMAN_VA_BASE & 0xff000000)
-       orr     r4, r4, #(PWRMAN_VA_BASE & 0x00ff0000)
-       orr     r4, r4, #(PWRMAN_VA_BASE & 0x0000ff00)
-       orr     r4, r4, #(PWRMAN_VA_BASE & 0x000000ff)
-       ldr     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-       @ setup SDRAM controller base address in r2
-       @ and put it's value in r3
-       mov     r2, #(SDRAM_CFG_VA_BASE & 0xff000000)
-       orr     r2, r2, #(SDRAM_CFG_VA_BASE & 0x00ff0000)
-       orr     r2, r2, #(SDRAM_CFG_VA_BASE & 0x0000ff00)
-       orr     r2, r2, #(SDRAM_CFG_VA_BASE & 0x000000ff)
-       ldr     r3, [r2, #MPMC_STATUS_REG_OFFS] @extra read - HW bug workaround
-
-       @ clear SDRAM self-refresh bit latch
-       and     r5, r5, #(~(1 << 8))
-       @ clear SDRAM self-refresh bit
-       and     r5, r5, #(~(1 << 9))
-       str     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-       @ do save current bit settings in r1
-       mov     r1, r5
-
-       @ set SDRAM self-refresh bit
-       orr     r5, r5, #(1 << 9)
-       str     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-       @ set SDRAM self-refresh bit latch
-       orr     r5, r5, #(1 << 8)
-       str     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-       @ clear SDRAM self-refresh bit latch
-       and     r5, r5, #(~(1 << 8))
-       str     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-       @ clear SDRAM self-refresh bit
-       and     r5, r5, #(~(1 << 9))
-       str     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-       @ wait for SDRAM to get into self-refresh mode
-2:     ldr     r3, [r2, #MPMC_STATUS_REG_OFFS]
-       tst     r3, #(1 << 2)
-       beq     2b
-
-       @ set 'get out of self-refresh mode after wakeup' bit
-       orr     r5, r5, #(1 << 7)
-       str     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-       mcr     p15, 0, r0, c7, c0, 4   @ kinda sleeping now...
-
-       @ set SDRAM self-refresh bit latch
-       orr     r5, r5, #(1 << 8)
-       str     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-       @ clear SDRAM self-refresh bit latch
-       and     r5, r5, #(~(1 << 8))
-       str     r5, [r4, #PWR_CTRL_REG_OFFS]
-
-       @ wait for SDRAM to get out self-refresh mode
-3:     ldr     r3, [r2, #MPMC_STATUS_REG_OFFS]
-       tst     r3, #5
-       bne     3b
-
-       @ restore regs and return
-       ldmfd   sp!, {r0 - r6, pc}
-
-ENTRY(pnx4008_cpu_standby_sz)
-       .word   . - pnx4008_cpu_standby
-
-ENTRY(pnx4008_cache_clean_invalidate)
-       stmfd   sp!, {r0 - r6, lr}
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-       mcr     p15, 0, ip, c7, c6, 0           @ invalidate D cache
-#else
-1:     mrc     p15, 0, r15, c7, c14, 3         @ test,clean,invalidate
-       bne     1b
-#endif
-       ldmfd   sp!, {r0 - r6, pc}
diff --git a/arch/arm/mach-pnx4008/time.c b/arch/arm/mach-pnx4008/time.c
deleted file mode 100644 (file)
index 0cfe8af..0000000
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/time.c
- *
- * PNX4008 Timers
- *
- * Authors: Vitaly Wool, Dmitry Chigirev, Grigory Tolstolytkin <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/sched.h>
-#include <linux/spinlock.h>
-#include <linux/module.h>
-#include <linux/kallsyms.h>
-#include <linux/time.h>
-#include <linux/timex.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <asm/mach/time.h>
-#include <asm/errno.h>
-
-#include "time.h"
-
-/*! Note: all timers are UPCOUNTING */
-
-/*!
- * Returns number of us since last clock interrupt.  Note that interrupts
- * will have been disabled by do_gettimeoffset()
- */
-static unsigned long pnx4008_gettimeoffset(void)
-{
-       u32 ticks_to_match =
-           __raw_readl(HSTIM_MATCH0) - __raw_readl(HSTIM_COUNTER);
-       u32 elapsed = LATCH - ticks_to_match;
-       return (elapsed * (tick_nsec / 1000)) / LATCH;
-}
-
-/*!
- * IRQ handler for the timer
- */
-static irqreturn_t pnx4008_timer_interrupt(int irq, void *dev_id)
-{
-       if (__raw_readl(HSTIM_INT) & MATCH0_INT) {
-
-               do {
-                       timer_tick();
-
-                       /*
-                        * this algorithm takes care of possible delay
-                        * for this interrupt handling longer than a normal
-                        * timer period
-                        */
-                       __raw_writel(__raw_readl(HSTIM_MATCH0) + LATCH,
-                                    HSTIM_MATCH0);
-                       __raw_writel(MATCH0_INT, HSTIM_INT);    /* clear interrupt */
-
-                       /*
-                        * The goal is to keep incrementing HSTIM_MATCH0
-                        * register until HSTIM_MATCH0 indicates time after
-                        * what HSTIM_COUNTER indicates.
-                        */
-               } while ((signed)
-                        (__raw_readl(HSTIM_MATCH0) -
-                         __raw_readl(HSTIM_COUNTER)) < 0);
-       }
-
-       return IRQ_HANDLED;
-}
-
-static struct irqaction pnx4008_timer_irq = {
-       .name = "PNX4008 Tick Timer",
-       .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-       .handler = pnx4008_timer_interrupt
-};
-
-/*!
- * Set up timer and timer interrupt.
- */
-static __init void pnx4008_setup_timer(void)
-{
-       __raw_writel(RESET_COUNT, MSTIM_CTRL);
-       while (__raw_readl(MSTIM_COUNTER)) ;    /* wait for reset to complete. 100% guarantee event */
-       __raw_writel(0, MSTIM_CTRL);    /* stop the timer */
-       __raw_writel(0, MSTIM_MCTRL);
-
-       __raw_writel(RESET_COUNT, HSTIM_CTRL);
-       while (__raw_readl(HSTIM_COUNTER)) ;    /* wait for reset to complete. 100% guarantee event */
-       __raw_writel(0, HSTIM_CTRL);
-       __raw_writel(0, HSTIM_MCTRL);
-       __raw_writel(0, HSTIM_CCR);
-       __raw_writel(12, HSTIM_PMATCH); /* scale down to 1 MHZ */
-       __raw_writel(LATCH, HSTIM_MATCH0);
-       __raw_writel(MR0_INT, HSTIM_MCTRL);
-
-       setup_irq(HSTIMER_INT, &pnx4008_timer_irq);
-
-       __raw_writel(COUNT_ENAB | DEBUG_EN, HSTIM_CTRL);        /*start timer, stop when JTAG active */
-}
-
-/* Timer Clock Control in PM register */
-#define TIMCLK_CTRL_REG  IO_ADDRESS((PNX4008_PWRMAN_BASE + 0xBC))
-#define WATCHDOG_CLK_EN                   1
-#define TIMER_CLK_EN                      2    /* HS and MS timers? */
-
-static u32 timclk_ctrl_reg_save;
-
-void pnx4008_timer_suspend(void)
-{
-       timclk_ctrl_reg_save = __raw_readl(TIMCLK_CTRL_REG);
-       __raw_writel(0, TIMCLK_CTRL_REG);       /* disable timers */
-}
-
-void pnx4008_timer_resume(void)
-{
-       __raw_writel(timclk_ctrl_reg_save, TIMCLK_CTRL_REG);    /* enable timers */
-}
-
-struct sys_timer pnx4008_timer = {
-       .init = pnx4008_setup_timer,
-       .offset = pnx4008_gettimeoffset,
-       .suspend = pnx4008_timer_suspend,
-       .resume = pnx4008_timer_resume,
-};
-
diff --git a/arch/arm/mach-pnx4008/time.h b/arch/arm/mach-pnx4008/time.h
deleted file mode 100644 (file)
index 75e88c5..0000000
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/timex.h
- *
- * PNX4008 timers header file
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef PNX_TIME_H
-#define PNX_TIME_H
-
-#include <linux/io.h>
-#include <mach/hardware.h>
-
-#define TICKS2USECS(x) (x)
-
-/* MilliSecond Timer - Chapter 21 Page 202 */
-
-#define MSTIM_INT     IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x0))
-#define MSTIM_CTRL    IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x4))
-#define MSTIM_COUNTER IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x8))
-#define MSTIM_MCTRL   IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x14))
-#define MSTIM_MATCH0  IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x18))
-#define MSTIM_MATCH1  IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x1c))
-
-/* High Speed Timer - Chpater 22, Page 205 */
-
-#define HSTIM_INT     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x0))
-#define HSTIM_CTRL    IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x4))
-#define HSTIM_COUNTER IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x8))
-#define HSTIM_PMATCH  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0xC))
-#define HSTIM_PCOUNT  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x10))
-#define HSTIM_MCTRL   IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x14))
-#define HSTIM_MATCH0  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x18))
-#define HSTIM_MATCH1  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x1c))
-#define HSTIM_MATCH2  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x20))
-#define HSTIM_CCR     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x28))
-#define HSTIM_CR0     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x2C))
-#define HSTIM_CR1     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x30))
-
-/* IMPORTANT: both timers are UPCOUNTING */
-
-/* xSTIM_MCTRL bit definitions */
-#define MR0_INT        1
-#define RESET_COUNT0   (1<<1)
-#define STOP_COUNT0    (1<<2)
-#define MR1_INT        (1<<3)
-#define RESET_COUNT1   (1<<4)
-#define STOP_COUNT1    (1<<5)
-#define MR2_INT        (1<<6)
-#define RESET_COUNT2   (1<<7)
-#define STOP_COUNT2    (1<<8)
-
-/* xSTIM_CTRL bit definitions */
-#define COUNT_ENAB     1
-#define RESET_COUNT    (1<<1)
-#define DEBUG_EN       (1<<2)
-
-/* xSTIM_INT bit definitions */
-#define MATCH0_INT     1
-#define MATCH1_INT     (1<<1)
-#define MATCH2_INT     (1<<2)
-#define RTC_TICK0      (1<<4)
-#define RTC_TICK1      (1<<5)
-
-#endif
diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig
new file mode 100644 (file)
index 0000000..41fc853
--- /dev/null
@@ -0,0 +1,19 @@
+if ARCH_SIRF
+
+menu "CSR SiRF primaII/Marco/Polo Specific Features"
+
+config ARCH_PRIMA2
+       bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
+       default y
+       select CPU_V7
+       select ZONE_DMA
+       select SIRF_IRQ
+       help
+          Support for CSR SiRFSoC ARM Cortex A9 Platform
+
+endmenu
+
+config SIRF_IRQ
+       bool
+
+endif
index 841847d..fc9ce22 100644 (file)
@@ -1,8 +1,8 @@
 obj-y := timer.o
-obj-y += irq.o
 obj-y += rstc.o
-obj-y += prima2.o
+obj-y += common.o
 obj-y += rtciobrg.o
 obj-$(CONFIG_DEBUG_LL) += lluart.o
 obj-$(CONFIG_CACHE_L2X0) += l2x0.o
 obj-$(CONFIG_SUSPEND) += pm.o sleep.o
+obj-$(CONFIG_SIRF_IRQ) += irq.o
similarity index 81%
rename from arch/arm/mach-prima2/prima2.c
rename to arch/arm/mach-prima2/common.c
index e9a17ae..f25a541 100644 (file)
@@ -30,20 +30,21 @@ void __init sirfsoc_init_late(void)
        sirfsoc_pm_init();
 }
 
-static const char *prima2cb_dt_match[] __initdata = {
-       "sirf,prima2-cb",
+#ifdef CONFIG_ARCH_PRIMA2
+static const char *prima2_dt_match[] __initdata = {
+       "sirf,prima2",
        NULL
 };
 
-MACHINE_START(PRIMA2_EVB, "prima2cb")
+DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
        /* Maintainer: Barry Song <baohua.song@csr.com> */
-       .atag_offset    = 0x100,
        .map_io         = sirfsoc_map_lluart,
        .init_irq       = sirfsoc_of_irq_init,
        .timer          = &sirfsoc_timer,
        .dma_zone_size  = SZ_256M,
        .init_machine   = sirfsoc_mach_init,
        .init_late      = sirfsoc_init_late,
-       .dt_compat      = prima2cb_dt_match,
+       .dt_compat      = prima2_dt_match,
        .restart        = sirfsoc_restart,
 MACHINE_END
+#endif
index 83125c6..0c898fc 100644 (file)
@@ -25,11 +25,11 @@ static __inline__ void putc(char c)
         * during kernel decompression, all mappings are flat:
         *  virt_addr == phys_addr
         */
-       while (__raw_readl(SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_STATUS)
+       while (__raw_readl((void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_STATUS)
                & SIRFSOC_UART1_TXFIFO_FULL)
                barrier();
 
-       __raw_writel(c, SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_DATA);
+       __raw_writel(c, (void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_DATA);
 }
 
 static inline void flush(void)
index a7b9415..7dee917 100644 (file)
@@ -63,7 +63,7 @@ void __init sirfsoc_of_irq_init(void)
 
        np = of_find_matching_node(NULL, intc_ids);
        if (!np)
-               panic("unable to find compatible intc node in dtb\n");
+               return;
 
        sirfsoc_intc_base = of_iomap(np, 0);
        if (!sirfsoc_intc_base)
index 166eee5..c1f3b12 100644 (file)
@@ -6,7 +6,6 @@
 #include <linux/spi/pxa2xx_spi.h>
 #include <linux/i2c/pxa-i2c.h>
 
-#include <asm/pmu.h>
 #include <mach/udc.h>
 #include <mach/pxa3xx-u2d.h>
 #include <mach/pxafb.h>
@@ -42,7 +41,7 @@ static struct resource pxa_resource_pmu = {
 
 struct platform_device pxa_device_pmu = {
        .name           = "arm-pmu",
-       .id             = ARM_PMU_DEVICE_CPU,
+       .id             = -1,
        .resource       = &pxa_resource_pmu,
        .num_resources  = 1,
 };
index a33e33b..ce77476 100644 (file)
@@ -33,7 +33,6 @@
 #include <asm/irq.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
-#include <asm/pmu.h>
 #include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -298,7 +297,7 @@ static struct resource pmu_resources[] = {
 
 static struct platform_device pmu_device = {
        .name                   = "arm-pmu",
-       .id                     = ARM_PMU_DEVICE_CPU,
+       .id                     = -1,
        .num_resources          = ARRAY_SIZE(pmu_resources),
        .resource               = pmu_resources,
 };
index f0298cb..e21711d 100644 (file)
@@ -35,7 +35,6 @@
 #include <asm/irq.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
-#include <asm/pmu.h>
 #include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -281,7 +280,7 @@ static struct resource pmu_resource = {
 
 static struct platform_device pmu_device = {
        .name                   = "arm-pmu",
-       .id                     = ARM_PMU_DEVICE_CPU,
+       .id                     = -1,
        .num_resources          = 1,
        .resource               = &pmu_resource,
 };
index 1f019f7..b442fb2 100644 (file)
@@ -33,7 +33,6 @@
 #include <asm/irq.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
-#include <asm/pmu.h>
 #include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -264,7 +263,7 @@ static struct resource pmu_resources[] = {
 
 static struct platform_device pmu_device = {
        .name                   = "arm-pmu",
-       .id                     = ARM_PMU_DEVICE_CPU,
+       .id                     = -1,
        .num_resources          = ARRAY_SIZE(pmu_resources),
        .resource               = pmu_resources,
 };
index 5032775..1435cd8 100644 (file)
@@ -32,7 +32,6 @@
 #include <asm/irq.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
-#include <asm/pmu.h>
 #include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
 
@@ -242,7 +241,7 @@ static struct resource pmu_resource = {
 
 static struct platform_device pmu_device = {
        .name                   = "arm-pmu",
-       .id                     = ARM_PMU_DEVICE_CPU,
+       .id                     = -1,
        .num_resources          = 1,
        .resource               = &pmu_resource,
 };
index de64ba0..5d2c8be 100644 (file)
@@ -31,7 +31,6 @@
 #include <asm/irq.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
-#include <asm/pmu.h>
 #include <asm/smp_twd.h>
 #include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
@@ -281,7 +280,7 @@ static struct resource pmu_resources[] = {
 
 static struct platform_device pmu_device = {
        .name                   = "arm-pmu",
-       .id                     = ARM_PMU_DEVICE_CPU,
+       .id                     = -1,
        .num_resources          = ARRAY_SIZE(pmu_resources),
        .resource               = pmu_resources,
 };
index a5eeb62..57aee91 100644 (file)
@@ -138,19 +138,7 @@ static struct platform_driver h1940bt_driver = {
        .remove         = h1940bt_remove,
 };
 
-
-static int __init h1940bt_init(void)
-{
-       return platform_driver_register(&h1940bt_driver);
-}
-
-static void __exit h1940bt_exit(void)
-{
-       platform_driver_unregister(&h1940bt_driver);
-}
-
-module_init(h1940bt_init);
-module_exit(h1940bt_exit);
+module_platform_driver(h1940bt_driver);
 
 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>");
 MODULE_DESCRIPTION("Driver for the iPAQ H1940 bluetooth chip");
index 5a7d0c0..0c7ed7a 100644 (file)
@@ -424,7 +424,8 @@ static void __init anubis_map_io(void)
                anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
        } else {
                /* ensure that the GPIO is setup */
-               s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
+               gpio_request_one(S3C2410_GPA(0), GPIOF_OUT_INIT_HIGH, NULL);
+               gpio_free(S3C2410_GPA(0));
        }
 }
 
index ae73ba3..4713347 100644 (file)
@@ -512,8 +512,8 @@ static void jive_power_off(void)
 {
        printk(KERN_INFO "powering system down...\n");
 
-       s3c2410_gpio_setpin(S3C2410_GPC(5), 1);
-       s3c_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT);
+       gpio_request_one(S3C2410_GPC(5), GPIOF_OUT_INIT_HIGH, NULL);
+       gpio_free(S3C2410_GPC(5));
 }
 
 static void __init jive_machine_init(void)
@@ -623,11 +623,11 @@ static void __init jive_machine_init(void)
        gpio_request(S3C2410_GPB(7), "jive spi");
        gpio_direction_output(S3C2410_GPB(7), 1);
 
-       s3c2410_gpio_setpin(S3C2410_GPB(6), 0);
-       s3c_gpio_cfgpin(S3C2410_GPB(6), S3C2410_GPIO_OUTPUT);
+       gpio_request_one(S3C2410_GPB(6), GPIOF_OUT_INIT_LOW, NULL);
+       gpio_free(S3C2410_GPB(6));
 
-       s3c2410_gpio_setpin(S3C2410_GPG(8), 1);
-       s3c_gpio_cfgpin(S3C2410_GPG(8), S3C2410_GPIO_OUTPUT);
+       gpio_request_one(S3C2410_GPG(8), GPIOF_OUT_INIT_HIGH, NULL);
+       gpio_free(S3C2410_GPG(8));
 
        /* initialise the WM8750 spi */
 
index bd6d252..734bbfe 100644 (file)
@@ -638,9 +638,9 @@ static void __init mini2440_init(void)
        gpio_free(S3C2410_GPG(4));
 
        /* remove pullup on optional PWM backlight -- unused on 3.5 and 7"s */
+       gpio_request_one(S3C2410_GPB(1), GPIOF_IN, NULL);
        s3c_gpio_setpull(S3C2410_GPB(1), S3C_GPIO_PULL_UP);
-       s3c2410_gpio_setpin(S3C2410_GPB(1), 0);
-       s3c_gpio_cfgpin(S3C2410_GPB(1), S3C2410_GPIO_INPUT);
+       gpio_free(S3C2410_GPB(1));
 
        /* mark the key as input, without pullups (there is one on the board) */
        for (i = 0; i < ARRAY_SIZE(mini2440_buttons); i++) {
index 5c05ba1..a71a551 100644 (file)
@@ -119,17 +119,17 @@ static struct platform_device *nexcoder_devices[] __initdata = {
 
 static void __init nexcoder_sensorboard_init(void)
 {
-       // Initialize SCCB bus
-       s3c2410_gpio_setpin(S3C2410_GPE(14), 1); // IICSCL
-       s3c_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPIO_OUTPUT);
-       s3c2410_gpio_setpin(S3C2410_GPE(15), 1); // IICSDA
-       s3c_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPIO_OUTPUT);
-
-       // Power up the sensor board
-       s3c2410_gpio_setpin(S3C2410_GPF(1), 1);
-       s3c_gpio_cfgpin(S3C2410_GPF(1), S3C2410_GPIO_OUTPUT); // CAM_GPIO7 => nLDO_PWRDN
-       s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
-       s3c_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); // CAM_GPIO6 => CAM_PWRDN
+       /* Initialize SCCB bus */
+       gpio_request_one(S3C2410_GPE(14), GPIOF_OUT_INIT_HIGH, NULL);
+       gpio_free(S3C2410_GPE(14)); /* IICSCL */
+       gpio_request_one(S3C2410_GPE(15), GPIOF_OUT_INIT_HIGH, NULL);
+       gpio_free(S3C2410_GPE(15)); /* IICSDA */
+
+       /* Power up the sensor board */
+       gpio_request_one(S3C2410_GPF(1), GPIOF_OUT_INIT_HIGH, NULL);
+       gpio_free(S3C2410_GPF(1)); /* CAM_GPIO7 => nLDO_PWRDN */
+       gpio_request_one(S3C2410_GPF(2), GPIOF_OUT_INIT_LOW, NULL);
+       gpio_free(S3C2410_GPF(2)); /* CAM_GPIO6 => CAM_PWRDN */
 }
 
 static void __init nexcoder_map_io(void)
index ad2792d..5876c6b 100644 (file)
@@ -175,18 +175,7 @@ static struct platform_driver osiris_dvs_driver = {
        },
 };
 
-static int __init osiris_dvs_init(void)
-{
-       return platform_driver_register(&osiris_dvs_driver);
-}
-
-static void __exit osiris_dvs_exit(void)
-{
-       platform_driver_unregister(&osiris_dvs_driver);
-}
-
-module_init(osiris_dvs_init);
-module_exit(osiris_dvs_exit);
+module_platform_driver(osiris_dvs_driver);
 
 MODULE_DESCRIPTION("Simtec OSIRIS DVS support");
 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
index 95d0772..c0fb3c1 100644 (file)
@@ -274,8 +274,8 @@ static int osiris_pm_suspend(void)
        __raw_writeb(tmp, OSIRIS_VA_CTRL0);
 
        /* ensure that an nRESET is not generated on resume. */
-       s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
-       s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
+       gpio_request_one(S3C2410_GPA(21), GPIOF_OUT_INIT_HIGH, NULL);
+       gpio_free(S3C2410_GPA(21));
 
        return 0;
 }
@@ -396,7 +396,8 @@ static void __init osiris_map_io(void)
                osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
        } else {
                /* write-protect line to the NAND */
-               s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
+               gpio_request_one(S3C2410_GPA(0), GPIOF_OUT_INIT_HIGH, NULL);
+               gpio_free(S3C2410_GPA(0));
        }
 
        /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
index cdea671..ac2ea76 100644 (file)
@@ -87,7 +87,7 @@
 #define SIMPAD_CS3_PCMCIA_SHORT                (SIMPAD_CS3_GPIO_BASE + 22)
 #define SIMPAD_CS3_GPIO_23             (SIMPAD_CS3_GPIO_BASE + 23)
 
-#define CS3_BASE        0xf1000000
+#define CS3_BASE        IOMEM(0xf1000000)
 
 long simpad_get_cs3_ro(void);
 long simpad_get_cs3_shadow(void);
index fbd5359..6ca92d0 100644 (file)
@@ -124,7 +124,7 @@ static struct map_desc simpad_io_desc[] __initdata = {
                .length         = 0x00800000,
                .type           = MT_DEVICE
        }, {    /* Simpad CS3 */
-               .virtual        = CS3_BASE,
+               .virtual        = (unsigned long)CS3_BASE,
                .pfn            = __phys_to_pfn(SA1100_CS3_PHYS),
                .length         = 0x00100000,
                .type           = MT_DEVICE
index 2704bcd..d35b94e 100644 (file)
@@ -21,9 +21,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
-#define IO_BASE                 0xe0000000
-#define IO_SIZE                 0x08000000
-#define IO_START                0x40000000
 #define ROMCARD_SIZE            0x08000000
 #define ROMCARD_START           0x10000000
 
@@ -104,20 +101,6 @@ arch_initcall(shark_init);
 
 extern void shark_init_irq(void);
 
-static struct map_desc shark_io_desc[] __initdata = {
-       {
-               .virtual        = IO_BASE,
-               .pfn            = __phys_to_pfn(IO_START),
-               .length         = IO_SIZE,
-               .type           = MT_DEVICE
-       }
-};
-
-static void __init shark_map_io(void)
-{
-       iotable_init(shark_io_desc, ARRAY_SIZE(shark_io_desc));
-}
-
 #define IRQ_TIMER 0
 #define HZ_TIME ((1193180 + HZ/2) / HZ)
 
@@ -158,7 +141,6 @@ static void shark_init_early(void)
 MACHINE_START(SHARK, "Shark")
        /* Maintainer: Alexander Schulz */
        .atag_offset    = 0x3000,
-       .map_io         = shark_map_io,
        .init_early     = shark_init_early,
        .init_irq       = shark_init_irq,
        .timer          = &shark_timer,
index 20eb2bf..d129119 100644 (file)
 */
 
                .macro  addruart, rp, rv, tmp
-               mov     \rp, #0xe0000000
-               orr     \rp, \rp, #0x000003f8
-               mov     \rv, \rp
+               mov     \rp, #0x3f8
+               orr     \rv, \rp, #0xfe000000
+               orr     \rv, \rv, #0x00e00000
+               orr     \rp, \rp, #0x40000000
                .endm
 
                .macro  senduart,rd,rx
index 5901b09..c9e49f0 100644 (file)
@@ -8,7 +8,8 @@
  * warranty of any kind, whether express or implied.
  */
                .macro  get_irqnr_preamble, base, tmp
-               mov     \base, #0xe0000000
+               mov     \base, #0xfe000000
+               orr     \base, \base, #0x00e00000
                .endm
 
                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
diff --git a/arch/arm/mach-shark/include/mach/io.h b/arch/arm/mach-shark/include/mach/io.h
deleted file mode 100644 (file)
index 1a45fc0..0000000
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * arch/arm/mach-shark/include/mach/io.h
- *
- * by Alexander Schulz
- *
- * derived from:
- * arch/arm/mach-ebsa110/include/mach/io.h
- * Copyright (C) 1997,1998 Russell King
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define __io(a)                 ((void __iomem *)(0xe0000000 + (a)))
-
-#endif
index 9089407..b8b4ab3 100644 (file)
@@ -8,12 +8,15 @@
 #include <linux/kernel.h>
 #include <linux/pci.h>
 #include <linux/init.h>
+#include <linux/io.h>
 #include <video/vga.h>
 
 #include <asm/irq.h>
 #include <asm/mach/pci.h>
 #include <asm/mach-types.h>
 
+#define IO_START       0x40000000
+
 static int __init shark_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
        if (dev->bus->number == 0)
@@ -44,6 +47,8 @@ static int __init shark_pci_init(void)
        pcibios_min_mem = 0x50000000;
        vga_base = 0xe8000000;
 
+       pci_ioremap_io(0, IO_START);
+
        pci_common_init(&shark_pci);
 
        return 0;
index d82c010..cfc3b5c 100644 (file)
@@ -40,7 +40,6 @@
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mfd/tmio.h>
 #include <linux/sh_clk.h>
-#include <linux/videodev2.h>
 #include <video/sh_mobile_lcdc.h>
 #include <video/sh_mipi_dsi.h>
 #include <sound/sh_fsi.h>
index f172ca8..1089ee5 100644 (file)
@@ -432,7 +432,7 @@ static void usb1_host_port_power(int port, int power)
                return;
 
        /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */
-       __raw_writew(__raw_readw(0xE68B0008) | 0x600, 0xE68B0008);
+       __raw_writew(__raw_readw(IOMEM(0xE68B0008)) | 0x600, IOMEM(0xE68B0008));
 }
 
 static struct r8a66597_platdata usb1_host_data = {
@@ -1224,9 +1224,9 @@ static struct i2c_board_info i2c1_devices[] = {
 };
 
 
-#define GPIO_PORT9CR   0xE6051009
-#define GPIO_PORT10CR  0xE605100A
-#define USCCR1         0xE6058144
+#define GPIO_PORT9CR   IOMEM(0xE6051009)
+#define GPIO_PORT10CR  IOMEM(0xE605100A)
+#define USCCR1         IOMEM(0xE6058144)
 static void __init ap4evb_init(void)
 {
        u32 srcr4;
@@ -1304,7 +1304,7 @@ static void __init ap4evb_init(void)
        gpio_request(GPIO_FN_OVCN2_1,    NULL);
 
        /* setup USB phy */
-       __raw_writew(0x8a0a, 0xE6058130);       /* USBCR4 */
+       __raw_writew(0x8a0a, IOMEM(0xE6058130));        /* USBCR4 */
 
        /* enable FSI2 port A (ak4643) */
        gpio_request(GPIO_FN_FSIAIBT,   NULL);
@@ -1453,7 +1453,7 @@ static void __init ap4evb_init(void)
        gpio_request(GPIO_FN_HDMI_CEC, NULL);
 
        /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
-#define SRCR4 0xe61580bc
+#define SRCR4 IOMEM(0xe61580bc)
        srcr4 = __raw_readl(SRCR4);
        __raw_writel(srcr4 | (1 << 13), SRCR4);
        udelay(50);
index 453a6e5..45b33e0 100644 (file)
  *     usbhsf_power_ctrl()
  */
 #define IRQ7           evt2irq(0x02e0)
-#define USBCR1         0xe605810a
+#define USBCR1         IOMEM(0xe605810a)
 #define USBH           0xC6700000
 #define USBH_USBCTR    0x10834
 
@@ -950,8 +950,8 @@ clock_error:
 /*
  * board init
  */
-#define GPIO_PORT7CR   0xe6050007
-#define GPIO_PORT8CR   0xe6050008
+#define GPIO_PORT7CR   IOMEM(0xe6050007)
+#define GPIO_PORT8CR   IOMEM(0xe6050008)
 static void __init eva_init(void)
 {
        struct platform_device *usb = NULL;
index 4129008..cb8c994 100644 (file)
@@ -108,12 +108,12 @@ static struct regulator_consumer_supply dummy_supplies[] = {
 #define FPGA_ETH_IRQ           (FPGA_IRQ0 + 15)
 static u16 bonito_fpga_read(u32 offset)
 {
-       return __raw_readw(0xf0003000 + offset);
+       return __raw_readw(IOMEM(0xf0003000) + offset);
 }
 
 static void bonito_fpga_write(u32 offset, u16 val)
 {
-       __raw_writew(val, 0xf0003000 + offset);
+       __raw_writew(val, IOMEM(0xf0003000) + offset);
 }
 
 static void bonito_fpga_irq_disable(struct irq_data *data)
@@ -361,8 +361,8 @@ static void __init bonito_map_io(void)
 #define BIT_ON(sw, bit)                (sw & (1 << bit))
 #define BIT_OFF(sw, bit)       (!(sw & (1 << bit)))
 
-#define VCCQ1CR                0xE6058140
-#define VCCQ1LCDCR     0xE6058186
+#define VCCQ1CR                IOMEM(0xE6058140)
+#define VCCQ1LCDCR     IOMEM(0xE6058186)
 
 static void __init bonito_init(void)
 {
index 796fa00..b179d4c 100644 (file)
@@ -106,7 +106,7 @@ static void usb_host_port_power(int port, int power)
                return;
 
        /* set VBOUT/PWEN and EXTLP0 in DVSTCTR */
-       __raw_writew(__raw_readw(0xe6890008) | 0x600, 0xe6890008);
+       __raw_writew(__raw_readw(IOMEM(0xe6890008)) | 0x600, IOMEM(0xe6890008));
 }
 
 static struct r8a66597_platdata usb_host_data = {
@@ -279,10 +279,10 @@ static void __init g3evm_init(void)
        gpio_request(GPIO_FN_IDIN, NULL);
 
        /* setup USB phy */
-       __raw_writew(0x0300, 0xe605810a);       /* USBCR1 */
-       __raw_writew(0x00e0, 0xe60581c0);       /* CPFCH */
-       __raw_writew(0x6010, 0xe60581c6);       /* CGPOSR */
-       __raw_writew(0x8a0a, 0xe605810c);       /* USBCR2 */
+       __raw_writew(0x0300, IOMEM(0xe605810a));        /* USBCR1 */
+       __raw_writew(0x00e0, IOMEM(0xe60581c0));        /* CPFCH */
+       __raw_writew(0x6010, IOMEM(0xe60581c6));        /* CGPOSR */
+       __raw_writew(0x8a0a, IOMEM(0xe605810c));        /* USBCR2 */
 
        /* KEYSC @ CN7 */
        gpio_request(GPIO_FN_PORT42_KEYOUT0, NULL);
@@ -320,7 +320,7 @@ static void __init g3evm_init(void)
        gpio_request(GPIO_FN_WE0_XWR0_FWE, NULL);
        gpio_request(GPIO_FN_FRB, NULL);
        /* FOE, FCDE, FSC on dedicated pins */
-       __raw_writel(__raw_readl(0xe6158048) & ~(1 << 15), 0xe6158048);
+       __raw_writel(__raw_readl(IOMEM(0xe6158048)) & ~(1 << 15), IOMEM(0xe6158048));
 
        /* IrDA */
        gpio_request(GPIO_FN_IRDA_OUT, NULL);
index fa5dfc5..22d6893 100644 (file)
@@ -126,7 +126,7 @@ static void usb_host_port_power(int port, int power)
                return;
 
        /* set VBOUT/PWEN and EXTLP0 in DVSTCTR */
-       __raw_writew(__raw_readw(0xe6890008) | 0x600, 0xe6890008);
+       __raw_writew(__raw_readw(IOMEM(0xe6890008)) | 0x600, IOMEM(0xe6890008));
 }
 
 static struct r8a66597_platdata usb_host_data = {
@@ -270,17 +270,17 @@ static struct platform_device *g4evm_devices[] __initdata = {
        &sdhi1_device,
 };
 
-#define GPIO_SDHID0_D0 0xe60520fc
-#define GPIO_SDHID0_D1 0xe60520fd
-#define GPIO_SDHID0_D2 0xe60520fe
-#define GPIO_SDHID0_D3 0xe60520ff
-#define GPIO_SDHICMD0  0xe6052100
+#define GPIO_SDHID0_D0 IOMEM(0xe60520fc)
+#define GPIO_SDHID0_D1 IOMEM(0xe60520fd)
+#define GPIO_SDHID0_D2 IOMEM(0xe60520fe)
+#define GPIO_SDHID0_D3 IOMEM(0xe60520ff)
+#define GPIO_SDHICMD0  IOMEM(0xe6052100)
 
-#define GPIO_SDHID1_D0 0xe6052103
-#define GPIO_SDHID1_D1 0xe6052104
-#define GPIO_SDHID1_D2 0xe6052105
-#define GPIO_SDHID1_D3 0xe6052106
-#define GPIO_SDHICMD1  0xe6052107
+#define GPIO_SDHID1_D0 IOMEM(0xe6052103)
+#define GPIO_SDHID1_D1 IOMEM(0xe6052104)
+#define GPIO_SDHID1_D2 IOMEM(0xe6052105)
+#define GPIO_SDHID1_D3 IOMEM(0xe6052106)
+#define GPIO_SDHICMD1  IOMEM(0xe6052107)
 
 static void __init g4evm_init(void)
 {
@@ -318,10 +318,10 @@ static void __init g4evm_init(void)
        gpio_request(GPIO_FN_IDIN, NULL);
 
        /* setup USB phy */
-       __raw_writew(0x0200, 0xe605810a);       /* USBCR1 */
-       __raw_writew(0x00e0, 0xe60581c0);       /* CPFCH */
-       __raw_writew(0x6010, 0xe60581c6);       /* CGPOSR */
-       __raw_writew(0x8a0a, 0xe605810c);       /* USBCR2 */
+       __raw_writew(0x0200, IOMEM(0xe605810a));       /* USBCR1 */
+       __raw_writew(0x00e0, IOMEM(0xe60581c0));       /* CPFCH */
+       __raw_writew(0x6010, IOMEM(0xe60581c6));       /* CGPOSR */
+       __raw_writew(0x8a0a, IOMEM(0xe605810c));       /* USBCR2 */
 
        /* KEYSC @ CN31 */
        gpio_request(GPIO_FN_PORT60_KEYOUT5, NULL);
index 3b8a017..99ae066 100644 (file)
@@ -133,8 +133,8 @@ static struct platform_device usb_host_device = {
 
 /* USB Func CN17 */
 struct usbhs_private {
-       unsigned int phy;
-       unsigned int cr2;
+       void __iomem *phy;
+       void __iomem *cr2;
        struct renesas_usbhs_platform_info info;
 };
 
@@ -232,8 +232,8 @@ static u32 usbhs_pipe_cfg[] = {
 };
 
 static struct usbhs_private usbhs_private = {
-       .phy    = 0xe60781e0,           /* USBPHYINT */
-       .cr2    = 0xe605810c,           /* USBCR2 */
+       .phy    = IOMEM(0xe60781e0),            /* USBPHYINT */
+       .cr2    = IOMEM(0xe605810c),            /* USBCR2 */
        .info = {
                .platform_callback = {
                        .hardware_init  = usbhs_hardware_init,
index c129542..0dce90e 100644 (file)
@@ -583,8 +583,8 @@ out:
 #define USBHS0_POLL_INTERVAL (HZ * 5)
 
 struct usbhs_private {
-       unsigned int usbphyaddr;
-       unsigned int usbcrcaddr;
+       void __iomem *usbphyaddr;
+       void __iomem *usbcrcaddr;
        struct renesas_usbhs_platform_info info;
        struct delayed_work work;
        struct platform_device *pdev;
@@ -642,7 +642,7 @@ static void usbhs0_hardware_exit(struct platform_device *pdev)
 }
 
 static struct usbhs_private usbhs0_private = {
-       .usbcrcaddr     = 0xe605810c,           /* USBCR2 */
+       .usbcrcaddr     = IOMEM(0xe605810c),            /* USBCR2 */
        .info = {
                .platform_callback = {
                        .hardware_init  = usbhs0_hardware_init,
@@ -776,8 +776,8 @@ static u32 usbhs1_pipe_cfg[] = {
 };
 
 static struct usbhs_private usbhs1_private = {
-       .usbphyaddr     = 0xe60581e2,           /* USBPHY1INTAP */
-       .usbcrcaddr     = 0xe6058130,           /* USBCR4 */
+       .usbphyaddr     = IOMEM(0xe60581e2),    /* USBPHY1INTAP */
+       .usbcrcaddr     = IOMEM(0xe6058130),    /* USBCR4 */
        .info = {
                .platform_callback = {
                        .hardware_init  = usbhs1_hardware_init,
@@ -1402,12 +1402,12 @@ static struct i2c_board_info i2c1_devices[] = {
        },
 };
 
-#define GPIO_PORT9CR   0xE6051009
-#define GPIO_PORT10CR  0xE605100A
-#define GPIO_PORT167CR 0xE60520A7
-#define GPIO_PORT168CR 0xE60520A8
-#define SRCR4          0xe61580bc
-#define USCCR1         0xE6058144
+#define GPIO_PORT9CR   IOMEM(0xE6051009)
+#define GPIO_PORT10CR  IOMEM(0xE605100A)
+#define GPIO_PORT167CR IOMEM(0xE60520A7)
+#define GPIO_PORT168CR IOMEM(0xE60520A8)
+#define SRCR4          IOMEM(0xe61580bc)
+#define USCCR1         IOMEM(0xE6058144)
 static void __init mackerel_init(void)
 {
        u32 srcr4;
index ad5fccc..6729e00 100644 (file)
  */
 
 /* CPG registers */
-#define FRQCRA         0xe6150000
-#define FRQCRB         0xe6150004
-#define VCLKCR1                0xE6150008
-#define VCLKCR2                0xE615000c
-#define FRQCRC         0xe61500e0
-#define FSIACKCR       0xe6150018
-#define PLLC01CR       0xe6150028
-
-#define SUBCKCR                0xe6150080
-#define USBCKCR                0xe615008c
-
-#define MSTPSR0                0xe6150030
-#define MSTPSR1                0xe6150038
-#define MSTPSR2                0xe6150040
-#define MSTPSR3                0xe6150048
-#define MSTPSR4                0xe615004c
-#define FSIBCKCR       0xe6150090
-#define HDMICKCR       0xe6150094
-#define SMSTPCR0       0xe6150130
-#define SMSTPCR1       0xe6150134
-#define SMSTPCR2       0xe6150138
-#define SMSTPCR3       0xe615013c
-#define SMSTPCR4       0xe6150140
+#define FRQCRA         IOMEM(0xe6150000)
+#define FRQCRB         IOMEM(0xe6150004)
+#define VCLKCR1                IOMEM(0xE6150008)
+#define VCLKCR2                IOMEM(0xE615000c)
+#define FRQCRC         IOMEM(0xe61500e0)
+#define FSIACKCR       IOMEM(0xe6150018)
+#define PLLC01CR       IOMEM(0xe6150028)
+
+#define SUBCKCR                IOMEM(0xe6150080)
+#define USBCKCR                IOMEM(0xe615008c)
+
+#define MSTPSR0                IOMEM(0xe6150030)
+#define MSTPSR1                IOMEM(0xe6150038)
+#define MSTPSR2                IOMEM(0xe6150040)
+#define MSTPSR3                IOMEM(0xe6150048)
+#define MSTPSR4                IOMEM(0xe615004c)
+#define FSIBCKCR       IOMEM(0xe6150090)
+#define HDMICKCR       IOMEM(0xe6150094)
+#define SMSTPCR0       IOMEM(0xe6150130)
+#define SMSTPCR1       IOMEM(0xe6150134)
+#define SMSTPCR2       IOMEM(0xe6150138)
+#define SMSTPCR3       IOMEM(0xe615013c)
+#define SMSTPCR4       IOMEM(0xe6150140)
 
 /* Fixed 32 KHz root clock from EXTALR pin */
 static struct clk extalr_clk = {
index 162b791..ef0a95e 100644 (file)
 #include <mach/common.h>
 
 /* SH7367 registers */
-#define RTFRQCR    0xe6150000
-#define SYFRQCR    0xe6150004
-#define CMFRQCR    0xe61500E0
-#define VCLKCR1    0xe6150008
-#define VCLKCR2    0xe615000C
-#define VCLKCR3    0xe615001C
-#define SCLKACR    0xe6150010
-#define SCLKBCR    0xe6150014
-#define SUBUSBCKCR 0xe6158080
-#define SPUCKCR    0xe6150084
-#define MSUCKCR    0xe6150088
-#define MVI3CKCR   0xe6150090
-#define VOUCKCR    0xe6150094
-#define MFCK1CR    0xe6150098
-#define MFCK2CR    0xe615009C
-#define PLLC1CR    0xe6150028
-#define PLLC2CR    0xe615002C
-#define RTMSTPCR0  0xe6158030
-#define RTMSTPCR2  0xe6158038
-#define SYMSTPCR0  0xe6158040
-#define SYMSTPCR2  0xe6158048
-#define CMMSTPCR0  0xe615804c
+#define RTFRQCR    IOMEM(0xe6150000)
+#define SYFRQCR    IOMEM(0xe6150004)
+#define CMFRQCR    IOMEM(0xe61500E0)
+#define VCLKCR1    IOMEM(0xe6150008)
+#define VCLKCR2    IOMEM(0xe615000C)
+#define VCLKCR3    IOMEM(0xe615001C)
+#define SCLKACR    IOMEM(0xe6150010)
+#define SCLKBCR    IOMEM(0xe6150014)
+#define SUBUSBCKCR IOMEM(0xe6158080)
+#define SPUCKCR    IOMEM(0xe6150084)
+#define MSUCKCR    IOMEM(0xe6150088)
+#define MVI3CKCR   IOMEM(0xe6150090)
+#define VOUCKCR    IOMEM(0xe6150094)
+#define MFCK1CR    IOMEM(0xe6150098)
+#define MFCK2CR    IOMEM(0xe615009C)
+#define PLLC1CR    IOMEM(0xe6150028)
+#define PLLC2CR    IOMEM(0xe615002C)
+#define RTMSTPCR0  IOMEM(0xe6158030)
+#define RTMSTPCR2  IOMEM(0xe6158038)
+#define SYMSTPCR0  IOMEM(0xe6158040)
+#define SYMSTPCR2  IOMEM(0xe6158048)
+#define CMMSTPCR0  IOMEM(0xe615804c)
 
 /* Fixed 32 KHz root clock from EXTALR pin */
 static struct clk r_clk = {
index 5a2894b..430a90f 100644 (file)
 #include <mach/common.h>
 
 /* SH7372 registers */
-#define FRQCRA         0xe6150000
-#define FRQCRB         0xe6150004
-#define FRQCRC         0xe61500e0
-#define FRQCRD         0xe61500e4
-#define VCLKCR1                0xe6150008
-#define VCLKCR2                0xe615000c
-#define VCLKCR3                0xe615001c
-#define FMSICKCR       0xe6150010
-#define FMSOCKCR       0xe6150014
-#define FSIACKCR       0xe6150018
-#define FSIBCKCR       0xe6150090
-#define SUBCKCR                0xe6150080
-#define SPUCKCR                0xe6150084
-#define VOUCKCR                0xe6150088
-#define HDMICKCR       0xe6150094
-#define DSITCKCR       0xe6150060
-#define DSI0PCKCR      0xe6150064
-#define DSI1PCKCR      0xe6150098
-#define PLLC01CR       0xe6150028
-#define PLLC2CR                0xe615002c
-#define RMSTPCR0       0xe6150110
-#define RMSTPCR1       0xe6150114
-#define RMSTPCR2       0xe6150118
-#define RMSTPCR3       0xe615011c
-#define RMSTPCR4       0xe6150120
-#define SMSTPCR0       0xe6150130
-#define SMSTPCR1       0xe6150134
-#define SMSTPCR2       0xe6150138
-#define SMSTPCR3       0xe615013c
-#define SMSTPCR4       0xe6150140
+#define FRQCRA         IOMEM(0xe6150000)
+#define FRQCRB         IOMEM(0xe6150004)
+#define FRQCRC         IOMEM(0xe61500e0)
+#define FRQCRD         IOMEM(0xe61500e4)
+#define VCLKCR1                IOMEM(0xe6150008)
+#define VCLKCR2                IOMEM(0xe615000c)
+#define VCLKCR3                IOMEM(0xe615001c)
+#define FMSICKCR       IOMEM(0xe6150010)
+#define FMSOCKCR       IOMEM(0xe6150014)
+#define FSIACKCR       IOMEM(0xe6150018)
+#define FSIBCKCR       IOMEM(0xe6150090)
+#define SUBCKCR                IOMEM(0xe6150080)
+#define SPUCKCR                IOMEM(0xe6150084)
+#define VOUCKCR                IOMEM(0xe6150088)
+#define HDMICKCR       IOMEM(0xe6150094)
+#define DSITCKCR       IOMEM(0xe6150060)
+#define DSI0PCKCR      IOMEM(0xe6150064)
+#define DSI1PCKCR      IOMEM(0xe6150098)
+#define PLLC01CR       IOMEM(0xe6150028)
+#define PLLC2CR                IOMEM(0xe615002c)
+#define RMSTPCR0       IOMEM(0xe6150110)
+#define RMSTPCR1       IOMEM(0xe6150114)
+#define RMSTPCR2       IOMEM(0xe6150118)
+#define RMSTPCR3       IOMEM(0xe615011c)
+#define RMSTPCR4       IOMEM(0xe6150120)
+#define SMSTPCR0       IOMEM(0xe6150130)
+#define SMSTPCR1       IOMEM(0xe6150134)
+#define SMSTPCR2       IOMEM(0xe6150138)
+#define SMSTPCR3       IOMEM(0xe615013c)
+#define SMSTPCR4       IOMEM(0xe6150140)
 
 #define FSIDIVA                0xFE1F8000
 #define FSIDIVB                0xFE1F8008
index 85f2a3e..b8480d1 100644 (file)
 #include <mach/common.h>
 
 /* SH7377 registers */
-#define RTFRQCR    0xe6150000
-#define SYFRQCR    0xe6150004
-#define CMFRQCR    0xe61500E0
-#define VCLKCR1    0xe6150008
-#define VCLKCR2    0xe615000C
-#define VCLKCR3    0xe615001C
-#define FMSICKCR   0xe6150010
-#define FMSOCKCR   0xe6150014
-#define FSICKCR    0xe6150018
-#define PLLC1CR    0xe6150028
-#define PLLC2CR    0xe615002C
-#define SUBUSBCKCR 0xe6150080
-#define SPUCKCR    0xe6150084
-#define MSUCKCR    0xe6150088
-#define MVI3CKCR   0xe6150090
-#define HDMICKCR   0xe6150094
-#define MFCK1CR    0xe6150098
-#define MFCK2CR    0xe615009C
-#define DSITCKCR   0xe6150060
-#define DSIPCKCR   0xe6150064
-#define SMSTPCR0   0xe6150130
-#define SMSTPCR1   0xe6150134
-#define SMSTPCR2   0xe6150138
-#define SMSTPCR3   0xe615013C
-#define SMSTPCR4   0xe6150140
+#define RTFRQCR    IOMEM(0xe6150000)
+#define SYFRQCR    IOMEM(0xe6150004)
+#define CMFRQCR    IOMEM(0xe61500E0)
+#define VCLKCR1    IOMEM(0xe6150008)
+#define VCLKCR2    IOMEM(0xe615000C)
+#define VCLKCR3    IOMEM(0xe615001C)
+#define FMSICKCR   IOMEM(0xe6150010)
+#define FMSOCKCR   IOMEM(0xe6150014)
+#define FSICKCR    IOMEM(0xe6150018)
+#define PLLC1CR    IOMEM(0xe6150028)
+#define PLLC2CR    IOMEM(0xe615002C)
+#define SUBUSBCKCR IOMEM(0xe6150080)
+#define SPUCKCR    IOMEM(0xe6150084)
+#define MSUCKCR    IOMEM(0xe6150088)
+#define MVI3CKCR   IOMEM(0xe6150090)
+#define HDMICKCR   IOMEM(0xe6150094)
+#define MFCK1CR    IOMEM(0xe6150098)
+#define MFCK2CR    IOMEM(0xe615009C)
+#define DSITCKCR   IOMEM(0xe6150060)
+#define DSIPCKCR   IOMEM(0xe6150064)
+#define SMSTPCR0   IOMEM(0xe6150130)
+#define SMSTPCR1   IOMEM(0xe6150134)
+#define SMSTPCR2   IOMEM(0xe6150138)
+#define SMSTPCR3   IOMEM(0xe615013C)
+#define SMSTPCR4   IOMEM(0xe6150140)
 
 /* Fixed 32 KHz root clock from EXTALR pin */
 static struct clk r_clk = {
index 7f8da18..516ff7f 100644 (file)
 #include <linux/clkdev.h>
 #include <mach/common.h>
 
-#define FRQCRA         0xe6150000
-#define FRQCRB         0xe6150004
-#define FRQCRD         0xe61500e4
-#define VCLKCR1                0xe6150008
-#define VCLKCR2                0xe615000C
-#define VCLKCR3                0xe615001C
-#define ZBCKCR         0xe6150010
-#define FLCKCR         0xe6150014
-#define SD0CKCR                0xe6150074
-#define SD1CKCR                0xe6150078
-#define SD2CKCR                0xe615007C
-#define FSIACKCR       0xe6150018
-#define FSIBCKCR       0xe6150090
-#define SUBCKCR                0xe6150080
-#define SPUACKCR       0xe6150084
-#define SPUVCKCR       0xe6150094
-#define MSUCKCR                0xe6150088
-#define HSICKCR                0xe615008C
-#define MFCK1CR                0xe6150098
-#define MFCK2CR                0xe615009C
-#define DSITCKCR       0xe6150060
-#define DSI0PCKCR      0xe6150064
-#define DSI1PCKCR      0xe6150068
+#define FRQCRA         IOMEM(0xe6150000)
+#define FRQCRB         IOMEM(0xe6150004)
+#define FRQCRD         IOMEM(0xe61500e4)
+#define VCLKCR1                IOMEM(0xe6150008)
+#define VCLKCR2                IOMEM(0xe615000C)
+#define VCLKCR3                IOMEM(0xe615001C)
+#define ZBCKCR         IOMEM(0xe6150010)
+#define FLCKCR         IOMEM(0xe6150014)
+#define SD0CKCR                IOMEM(0xe6150074)
+#define SD1CKCR                IOMEM(0xe6150078)
+#define SD2CKCR                IOMEM(0xe615007C)
+#define FSIACKCR       IOMEM(0xe6150018)
+#define FSIBCKCR       IOMEM(0xe6150090)
+#define SUBCKCR                IOMEM(0xe6150080)
+#define SPUACKCR       IOMEM(0xe6150084)
+#define SPUVCKCR       IOMEM(0xe6150094)
+#define MSUCKCR                IOMEM(0xe6150088)
+#define HSICKCR                IOMEM(0xe615008C)
+#define MFCK1CR                IOMEM(0xe6150098)
+#define MFCK2CR                IOMEM(0xe615009C)
+#define DSITCKCR       IOMEM(0xe6150060)
+#define DSI0PCKCR      IOMEM(0xe6150064)
+#define DSI1PCKCR      IOMEM(0xe6150068)
 #define DSI0PHYCR      0xe615006C
 #define DSI1PHYCR      0xe6150070
-#define PLLECR         0xe61500d0
-#define PLL0CR         0xe61500d8
-#define PLL1CR         0xe6150028
-#define PLL2CR         0xe615002c
-#define PLL3CR         0xe61500dc
-#define SMSTPCR0       0xe6150130
-#define SMSTPCR1       0xe6150134
-#define SMSTPCR2       0xe6150138
-#define SMSTPCR3       0xe615013c
-#define SMSTPCR4       0xe6150140
-#define SMSTPCR5       0xe6150144
-#define CKSCR          0xe61500c0
+#define PLLECR         IOMEM(0xe61500d0)
+#define PLL0CR         IOMEM(0xe61500d8)
+#define PLL1CR         IOMEM(0xe6150028)
+#define PLL2CR         IOMEM(0xe615002c)
+#define PLL3CR         IOMEM(0xe61500dc)
+#define SMSTPCR0       IOMEM(0xe6150130)
+#define SMSTPCR1       IOMEM(0xe6150134)
+#define SMSTPCR2       IOMEM(0xe6150138)
+#define SMSTPCR3       IOMEM(0xe615013c)
+#define SMSTPCR4       IOMEM(0xe6150140)
+#define SMSTPCR5       IOMEM(0xe6150144)
+#define CKSCR          IOMEM(0xe61500c0)
 
 /* Fixed 32 KHz root clock from EXTALR pin */
 static struct clk r_clk = {
index 844507d..90a92b2 100644 (file)
@@ -35,12 +35,12 @@ static inline int irq_to_gpio(unsigned int irq)
  * the method to control only pull up/down/free.
  * this function should be replaced by correct gpio function
  */
-static inline void __init gpio_direction_none(u32 addr)
+static inline void __init gpio_direction_none(void __iomem * addr)
 {
        __raw_writeb(0x00, addr);
 }
 
-static inline void __init gpio_request_pullup(u32 addr)
+static inline void __init gpio_request_pullup(void __iomem * addr)
 {
        u8 data = __raw_readb(addr);
 
@@ -49,7 +49,7 @@ static inline void __init gpio_request_pullup(u32 addr)
        __raw_writeb(data, addr);
 }
 
-static inline void __init gpio_request_pulldown(u32 addr)
+static inline void __init gpio_request_pulldown(void __iomem * addr)
 {
        u8 data = __raw_readb(addr);
 
index f04fad4..ef66f1a 100644 (file)
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#define INT2SMSKCR0 0xfe7822a0
-#define INT2SMSKCR1 0xfe7822a4
-#define INT2SMSKCR2 0xfe7822a8
-#define INT2SMSKCR3 0xfe7822ac
-#define INT2SMSKCR4 0xfe7822b0
+#define INT2SMSKCR0 IOMEM(0xfe7822a0)
+#define INT2SMSKCR1 IOMEM(0xfe7822a4)
+#define INT2SMSKCR2 IOMEM(0xfe7822a8)
+#define INT2SMSKCR3 IOMEM(0xfe7822ac)
+#define INT2SMSKCR4 IOMEM(0xfe7822b0)
 
-#define INT2NTSR0 0xfe700060
-#define INT2NTSR1 0xfe700064
+#define INT2NTSR0 IOMEM(0xfe700060)
+#define INT2NTSR1 IOMEM(0xfe700064)
 
 static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
 {
index 2587a22..a91caad 100644 (file)
@@ -624,6 +624,9 @@ void sh7372_intcs_resume(void)
                __raw_writeb(ffd5[k], intcs_ffd5 + k);
 }
 
+#define E694_BASE IOMEM(0xe6940000)
+#define E695_BASE IOMEM(0xe6950000)
+
 static unsigned short e694[0x200];
 static unsigned short e695[0x200];
 
@@ -632,22 +635,22 @@ void sh7372_intca_suspend(void)
        int k;
 
        for (k = 0x00; k <= 0x38; k += 4)
-               e694[k] = __raw_readw(0xe6940000 + k);
+               e694[k] = __raw_readw(E694_BASE + k);
 
        for (k = 0x80; k <= 0xb4; k += 4)
-               e694[k] = __raw_readb(0xe6940000 + k);
+               e694[k] = __raw_readb(E694_BASE + k);
 
        for (k = 0x180; k <= 0x1b4; k += 4)
-               e694[k] = __raw_readb(0xe6940000 + k);
+               e694[k] = __raw_readb(E694_BASE + k);
 
        for (k = 0x00; k <= 0x50; k += 4)
-               e695[k] = __raw_readw(0xe6950000 + k);
+               e695[k] = __raw_readw(E695_BASE + k);
 
        for (k = 0x80; k <= 0xa8; k += 4)
-               e695[k] = __raw_readb(0xe6950000 + k);
+               e695[k] = __raw_readb(E695_BASE + k);
 
        for (k = 0x180; k <= 0x1a8; k += 4)
-               e695[k] = __raw_readb(0xe6950000 + k);
+               e695[k] = __raw_readb(E695_BASE + k);
 }
 
 void sh7372_intca_resume(void)
@@ -655,20 +658,20 @@ void sh7372_intca_resume(void)
        int k;
 
        for (k = 0x00; k <= 0x38; k += 4)
-               __raw_writew(e694[k], 0xe6940000 + k);
+               __raw_writew(e694[k], E694_BASE + k);
 
        for (k = 0x80; k <= 0xb4; k += 4)
-               __raw_writeb(e694[k], 0xe6940000 + k);
+               __raw_writeb(e694[k], E694_BASE + k);
 
        for (k = 0x180; k <= 0x1b4; k += 4)
-               __raw_writeb(e694[k], 0xe6940000 + k);
+               __raw_writeb(e694[k], E694_BASE + k);
 
        for (k = 0x00; k <= 0x50; k += 4)
-               __raw_writew(e695[k], 0xe6950000 + k);
+               __raw_writew(e695[k], E695_BASE + k);
 
        for (k = 0x80; k <= 0xa8; k += 4)
-               __raw_writeb(e695[k], 0xe6950000 + k);
+               __raw_writeb(e695[k], E695_BASE + k);
 
        for (k = 0x180; k <= 0x1a8; k += 4)
-               __raw_writeb(e695[k], 0xe6950000 + k);
+               __raw_writeb(e695[k], E695_BASE + k);
 }
index 588555a..f0c5e51 100644 (file)
@@ -366,10 +366,12 @@ static irqreturn_t sh73a0_irq_pin_demux(int irq, void *dev_id)
 
 static struct irqaction sh73a0_irq_pin_cascade[32];
 
-#define PINTER0 0xe69000a0
-#define PINTER1 0xe69000a4
-#define PINTRR0 0xe69000d0
-#define PINTRR1 0xe69000d4
+#define PINTER0_PHYS 0xe69000a0
+#define PINTER1_PHYS 0xe69000a4
+#define PINTER0_VIRT IOMEM(0xe69000a0)
+#define PINTER1_VIRT IOMEM(0xe69000a4)
+#define PINTRR0 IOMEM(0xe69000d0)
+#define PINTRR1 IOMEM(0xe69000d4)
 
 #define PINT0A_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq))
 #define PINT0B_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 8))
@@ -377,14 +379,14 @@ static struct irqaction sh73a0_irq_pin_cascade[32];
 #define PINT0D_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 24))
 #define PINT1E_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT1_IRQ(irq))
 
-INTC_PINT(intc_pint0, PINTER0, 0xe69000b0, "sh73a0-pint0",             \
+INTC_PINT(intc_pint0, PINTER0_PHYS, 0xe69000b0, "sh73a0-pint0",                \
   INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D),      \
   INTC_PINT_V(A, PINT0A_IRQ), INTC_PINT_V(B, PINT0B_IRQ),              \
   INTC_PINT_V(C, PINT0C_IRQ), INTC_PINT_V(D, PINT0D_IRQ),              \
   INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D),      \
   INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D));
 
-INTC_PINT(intc_pint1, PINTER1, 0xe69000c0, "sh73a0-pint1",             \
+INTC_PINT(intc_pint1, PINTER1_PHYS, 0xe69000c0, "sh73a0-pint1",                \
   INTC_PINT_E(E), INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, \
   INTC_PINT_V(E, PINT1E_IRQ), INTC_PINT_V_NONE,                                \
   INTC_PINT_V_NONE, INTC_PINT_V_NONE,                                  \
@@ -394,7 +396,7 @@ INTC_PINT(intc_pint1, PINTER1, 0xe69000c0, "sh73a0-pint1",          \
 static struct irqaction sh73a0_pint0_cascade;
 static struct irqaction sh73a0_pint1_cascade;
 
-static void pint_demux(unsigned long rr, unsigned long er, int base_irq)
+static void pint_demux(void __iomem *rr, void __iomem *er, int base_irq)
 {
        unsigned long value =  ioread32(rr) & ioread32(er);
        int k;
@@ -409,13 +411,13 @@ static void pint_demux(unsigned long rr, unsigned long er, int base_irq)
 
 static irqreturn_t sh73a0_pint0_demux(int irq, void *dev_id)
 {
-       pint_demux(PINTRR0, PINTER0, SH73A0_PINT0_IRQ(0));
+       pint_demux(PINTRR0, PINTER0_VIRT, SH73A0_PINT0_IRQ(0));
        return IRQ_HANDLED;
 }
 
 static irqreturn_t sh73a0_pint1_demux(int irq, void *dev_id)
 {
-       pint_demux(PINTRR1, PINTER1, SH73A0_PINT1_IRQ(0));
+       pint_demux(PINTRR1, PINTER1_VIRT, SH73A0_PINT1_IRQ(0));
        return IRQ_HANDLED;
 }
 
index a856254..32e1772 100644 (file)
@@ -20,9 +20,9 @@
 #include <mach/pm-rmobile.h>
 
 /* SYSC */
-#define SPDCR          0xe6180008
-#define SWUCR          0xe6180014
-#define PSTR           0xe6180080
+#define SPDCR          IOMEM(0xe6180008)
+#define SWUCR          IOMEM(0xe6180014)
+#define PSTR           IOMEM(0xe6180080)
 
 #define PSTR_RETRIES   100
 #define PSTR_DELAY_US  10
index 7920370..1621218 100644 (file)
 #include <mach/pm-rmobile.h>
 
 /* DBG */
-#define DBGREG1 0xe6100020
-#define DBGREG9 0xe6100040
+#define DBGREG1 IOMEM(0xe6100020)
+#define DBGREG9 IOMEM(0xe6100040)
 
 /* CPGA */
-#define SYSTBCR 0xe6150024
-#define MSTPSR0 0xe6150030
-#define MSTPSR1 0xe6150038
-#define MSTPSR2 0xe6150040
-#define MSTPSR3 0xe6150048
-#define MSTPSR4 0xe615004c
-#define PLLC01STPCR 0xe61500c8
+#define SYSTBCR IOMEM(0xe6150024)
+#define MSTPSR0 IOMEM(0xe6150030)
+#define MSTPSR1 IOMEM(0xe6150038)
+#define MSTPSR2 IOMEM(0xe6150040)
+#define MSTPSR3 IOMEM(0xe6150048)
+#define MSTPSR4 IOMEM(0xe615004c)
+#define PLLC01STPCR IOMEM(0xe61500c8)
 
 /* SYSC */
-#define SBAR 0xe6180020
-#define WUPRMSK 0xe6180028
-#define WUPSMSK 0xe618002c
-#define WUPSMSK2 0xe6180048
-#define WUPSFAC 0xe6180098
-#define IRQCR 0xe618022c
-#define IRQCR2 0xe6180238
-#define IRQCR3 0xe6180244
-#define IRQCR4 0xe6180248
-#define PDNSEL 0xe6180254
+#define SBAR IOMEM(0xe6180020)
+#define WUPRMSK IOMEM(0xe6180028)
+#define WUPSMSK IOMEM(0xe618002c)
+#define WUPSMSK2 IOMEM(0xe6180048)
+#define WUPSFAC IOMEM(0xe6180098)
+#define IRQCR IOMEM(0xe618022c)
+#define IRQCR2 IOMEM(0xe6180238)
+#define IRQCR3 IOMEM(0xe6180244)
+#define IRQCR4 IOMEM(0xe6180248)
+#define PDNSEL IOMEM(0xe6180254)
 
 /* INTC */
-#define ICR1A 0xe6900000
-#define ICR2A 0xe6900004
-#define ICR3A 0xe6900008
-#define ICR4A 0xe690000c
-#define INTMSK00A 0xe6900040
-#define INTMSK10A 0xe6900044
-#define INTMSK20A 0xe6900048
-#define INTMSK30A 0xe690004c
+#define ICR1A IOMEM(0xe6900000)
+#define ICR2A IOMEM(0xe6900004)
+#define ICR3A IOMEM(0xe6900008)
+#define ICR4A IOMEM(0xe690000c)
+#define INTMSK00A IOMEM(0xe6900040)
+#define INTMSK10A IOMEM(0xe6900044)
+#define INTMSK20A IOMEM(0xe6900048)
+#define INTMSK30A IOMEM(0xe690004c)
 
 /* MFIS */
+/* FIXME: pointing where? */
 #define SMFRAM 0xe6a70000
 
 /* AP-System Core */
-#define APARMBAREA 0xe6f10020
+#define APARMBAREA IOMEM(0xe6f10020)
 
 #ifdef CONFIG_PM
 
index 2e3074a..e647f54 100644 (file)
@@ -462,7 +462,7 @@ static void __init sh7367_earlytimer_init(void)
        shmobile_earlytimer_init();
 }
 
-#define SYMSTPCR2 0xe6158048
+#define SYMSTPCR2 IOMEM(0xe6158048)
 #define SYMSTPCR2_CMT1 (1 << 29)
 
 void __init sh7367_add_early_devices(void)
index 855b150..edcf98b 100644 (file)
@@ -484,7 +484,7 @@ static void __init sh7377_earlytimer_init(void)
        shmobile_earlytimer_init();
 }
 
-#define SMSTPCR3 0xe615013c
+#define SMSTPCR3 IOMEM(0xe615013c)
 #define SMSTPCR3_CMT1 (1 << 29)
 
 void __init sh7377_add_early_devices(void)
index d230af6..a13c97b 100644 (file)
@@ -759,7 +759,7 @@ static struct platform_device *sh73a0_late_devices[] __initdata = {
        &mpdma0_device,
 };
 
-#define SRCR2          0xe61580b0
+#define SRCR2          IOMEM(0xe61580b0)
 
 void __init sh73a0_add_standard_devices(void)
 {
index 65f27de..07d90ac 100644 (file)
 #include <asm/memory.h>
 
 #define PERIP_GRP2_BASE                                UL(0xB3000000)
-#define VA_PERIP_GRP2_BASE                     UL(0xFE000000)
+#define VA_PERIP_GRP2_BASE                     IOMEM(0xFE000000)
 #define MCIF_SDHCI_BASE                                UL(0xB3000000)
 #define SYSRAM0_BASE                           UL(0xB3800000)
-#define VA_SYSRAM0_BASE                                UL(0xFE800000)
+#define VA_SYSRAM0_BASE                                IOMEM(0xFE800000)
 #define SYS_LOCATION                           (VA_SYSRAM0_BASE + 0x600)
 
 #define PERIP_GRP1_BASE                                UL(0xE0000000)
-#define VA_PERIP_GRP1_BASE                     UL(0xFD000000)
+#define VA_PERIP_GRP1_BASE                     IOMEM(0xFD000000)
 #define UART_BASE                              UL(0xE0000000)
-#define VA_UART_BASE                           UL(0xFD000000)
+#define VA_UART_BASE                           IOMEM(0xFD000000)
 #define SSP_BASE                               UL(0xE0100000)
 #define MISC_BASE                              UL(0xE0700000)
-#define VA_MISC_BASE                           IOMEM(UL(0xFD700000))
+#define VA_MISC_BASE                           IOMEM(0xFD700000)
 
 #define A9SM_AND_MPMC_BASE                     UL(0xEC000000)
-#define VA_A9SM_AND_MPMC_BASE                  UL(0xFC000000)
+#define VA_A9SM_AND_MPMC_BASE                  IOMEM(0xFC000000)
 
 /* A9SM peripheral offsets */
 #define A9SM_PERIP_BASE                                UL(0xEC800000)
-#define VA_A9SM_PERIP_BASE                     UL(0xFC800000)
+#define VA_A9SM_PERIP_BASE                     IOMEM(0xFC800000)
 #define VA_SCU_BASE                            (VA_A9SM_PERIP_BASE + 0x00)
 
 #define L2CC_BASE                              UL(0xED000000)
index cf936b1..e106488 100644 (file)
@@ -114,17 +114,17 @@ void __init spear13xx_l2x0_init(void)
  */
 struct map_desc spear13xx_io_desc[] __initdata = {
        {
-               .virtual        = VA_PERIP_GRP2_BASE,
+               .virtual        = (unsigned long)VA_PERIP_GRP2_BASE,
                .pfn            = __phys_to_pfn(PERIP_GRP2_BASE),
                .length         = SZ_16M,
                .type           = MT_DEVICE
        }, {
-               .virtual        = VA_PERIP_GRP1_BASE,
+               .virtual        = (unsigned long)VA_PERIP_GRP1_BASE,
                .pfn            = __phys_to_pfn(PERIP_GRP1_BASE),
                .length         = SZ_16M,
                .type           = MT_DEVICE
        }, {
-               .virtual        = VA_A9SM_AND_MPMC_BASE,
+               .virtual        = (unsigned long)VA_A9SM_AND_MPMC_BASE,
                .pfn            = __phys_to_pfn(A9SM_AND_MPMC_BASE),
                .length         = SZ_16M,
                .type           = MT_DEVICE
index 9077aaa..5f3c03b 100644 (file)
@@ -34,7 +34,6 @@ config ARCH_TEGRA_3x_SOC
        select USB_ARCH_HAS_EHCI if USB_SUPPORT
        select USB_ULPI if USB
        select USB_ULPI_VIEWPORT if USB_SUPPORT
-       select USE_OF
        select ARM_ERRATA_743622
        select ARM_ERRATA_751472
        select ARM_ERRATA_754322
@@ -60,25 +59,6 @@ config TEGRA_AHB
 
 comment "Tegra board type"
 
-config MACH_HARMONY
-       bool "Harmony board"
-       depends on ARCH_TEGRA_2x_SOC
-       help
-         Support for nVidia Harmony development platform
-
-config MACH_PAZ00
-       bool "Paz00 board"
-       depends on ARCH_TEGRA_2x_SOC
-       help
-         Support for the Toshiba AC100/Dynabook AZ netbook
-
-config MACH_TRIMSLICE
-       bool "TrimSlice board"
-       depends on ARCH_TEGRA_2x_SOC
-       select TEGRA_PCI
-       help
-         Support for CompuLab TrimSlice platform
-
 choice
         prompt "Default low-level debug console UART"
         default TEGRA_DEBUG_UART_NONE
@@ -130,13 +110,6 @@ config TEGRA_DEBUG_UART_AUTO_SCRATCH
 
 endchoice
 
-config TEGRA_SYSTEM_DMA
-       bool "Enable system DMA driver for NVIDIA Tegra SoCs"
-       default y
-       help
-         Adds system DMA functionality for NVIDIA Tegra SoCs, used by
-         several Tegra device drivers
-
 config TEGRA_EMC_SCALING_ENABLE
        bool "Enable scaling the memory frequency"
 
index 0e82b7f..191d973 100644 (file)
@@ -18,20 +18,12 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC)             += tegra30_clocks.o
 obj-$(CONFIG_SMP)                      += platsmp.o headsmp.o
 obj-$(CONFIG_SMP)                       += reset.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
-obj-$(CONFIG_TEGRA_SYSTEM_DMA)         += dma.o
 obj-$(CONFIG_CPU_FREQ)                  += cpu-tegra.o
 obj-$(CONFIG_TEGRA_PCI)                        += pcie.o
 
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)                += board-dt-tegra20.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)                += board-dt-tegra30.o
 
-obj-$(CONFIG_MACH_HARMONY)              += board-harmony.o
-obj-$(CONFIG_MACH_HARMONY)              += board-harmony-pinmux.o
-obj-$(CONFIG_MACH_HARMONY)              += board-harmony-pcie.o
-obj-$(CONFIG_MACH_HARMONY)              += board-harmony-power.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)                += board-harmony-pcie.o
 
-obj-$(CONFIG_MACH_PAZ00)               += board-paz00.o
-obj-$(CONFIG_MACH_PAZ00)               += board-paz00-pinmux.o
-
-obj-$(CONFIG_MACH_TRIMSLICE)            += board-trimslice.o
-obj-$(CONFIG_MACH_TRIMSLICE)            += board-trimslice-pinmux.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)                += board-paz00.o
index dc0fe38..b5015d0 100644 (file)
@@ -28,7 +28,7 @@
 
 #include "apbio.h"
 
-#if defined(CONFIG_TEGRA_SYSTEM_DMA) || defined(CONFIG_TEGRA20_APB_DMA)
+#if defined(CONFIG_TEGRA20_APB_DMA)
 static DEFINE_MUTEX(tegra_apb_dma_lock);
 static u32 *tegra_apb_bb;
 static dma_addr_t tegra_apb_bb_phys;
@@ -37,121 +37,6 @@ static DECLARE_COMPLETION(tegra_apb_wait);
 static u32 tegra_apb_readl_direct(unsigned long offset);
 static void tegra_apb_writel_direct(u32 value, unsigned long offset);
 
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
-static struct tegra_dma_channel *tegra_apb_dma;
-
-bool tegra_apb_init(void)
-{
-       struct tegra_dma_channel *ch;
-
-       mutex_lock(&tegra_apb_dma_lock);
-
-       /* Check to see if we raced to setup */
-       if (tegra_apb_dma)
-               goto out;
-
-       ch = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT |
-               TEGRA_DMA_SHARED);
-
-       if (!ch)
-               goto out_fail;
-
-       tegra_apb_bb = dma_alloc_coherent(NULL, sizeof(u32),
-               &tegra_apb_bb_phys, GFP_KERNEL);
-       if (!tegra_apb_bb) {
-               pr_err("%s: can not allocate bounce buffer\n", __func__);
-               tegra_dma_free_channel(ch);
-               goto out_fail;
-       }
-
-       tegra_apb_dma = ch;
-out:
-       mutex_unlock(&tegra_apb_dma_lock);
-       return true;
-
-out_fail:
-       mutex_unlock(&tegra_apb_dma_lock);
-       return false;
-}
-
-static void apb_dma_complete(struct tegra_dma_req *req)
-{
-       complete(&tegra_apb_wait);
-}
-
-static u32 tegra_apb_readl_using_dma(unsigned long offset)
-{
-       struct tegra_dma_req req;
-       int ret;
-
-       if (!tegra_apb_dma && !tegra_apb_init())
-               return tegra_apb_readl_direct(offset);
-
-       mutex_lock(&tegra_apb_dma_lock);
-       req.complete = apb_dma_complete;
-       req.to_memory = 1;
-       req.dest_addr = tegra_apb_bb_phys;
-       req.dest_bus_width = 32;
-       req.dest_wrap = 1;
-       req.source_addr = offset;
-       req.source_bus_width = 32;
-       req.source_wrap = 4;
-       req.req_sel = TEGRA_DMA_REQ_SEL_CNTR;
-       req.size = 4;
-
-       INIT_COMPLETION(tegra_apb_wait);
-
-       tegra_dma_enqueue_req(tegra_apb_dma, &req);
-
-       ret = wait_for_completion_timeout(&tegra_apb_wait,
-               msecs_to_jiffies(50));
-
-       if (WARN(ret == 0, "apb read dma timed out")) {
-               tegra_dma_dequeue_req(tegra_apb_dma, &req);
-               *(u32 *)tegra_apb_bb = 0;
-       }
-
-       mutex_unlock(&tegra_apb_dma_lock);
-       return *((u32 *)tegra_apb_bb);
-}
-
-static void tegra_apb_writel_using_dma(u32 value, unsigned long offset)
-{
-       struct tegra_dma_req req;
-       int ret;
-
-       if (!tegra_apb_dma && !tegra_apb_init()) {
-               tegra_apb_writel_direct(value, offset);
-               return;
-       }
-
-       mutex_lock(&tegra_apb_dma_lock);
-       *((u32 *)tegra_apb_bb) = value;
-       req.complete = apb_dma_complete;
-       req.to_memory = 0;
-       req.dest_addr = offset;
-       req.dest_wrap = 4;
-       req.dest_bus_width = 32;
-       req.source_addr = tegra_apb_bb_phys;
-       req.source_bus_width = 32;
-       req.source_wrap = 1;
-       req.req_sel = TEGRA_DMA_REQ_SEL_CNTR;
-       req.size = 4;
-
-       INIT_COMPLETION(tegra_apb_wait);
-
-       tegra_dma_enqueue_req(tegra_apb_dma, &req);
-
-       ret = wait_for_completion_timeout(&tegra_apb_wait,
-               msecs_to_jiffies(50));
-
-       if (WARN(ret == 0, "apb write dma timed out"))
-               tegra_dma_dequeue_req(tegra_apb_dma, &req);
-
-       mutex_unlock(&tegra_apb_dma_lock);
-}
-
-#else
 static struct dma_chan *tegra_apb_dma_chan;
 static struct dma_slave_config dma_sconfig;
 
@@ -279,7 +164,6 @@ static void tegra_apb_writel_using_dma(u32 value, unsigned long offset)
                pr_err("error in writing offset 0x%08lx using dma\n", offset);
        mutex_unlock(&tegra_apb_dma_lock);
 }
-#endif
 #else
 #define tegra_apb_readl_using_dma tegra_apb_readl_direct
 #define tegra_apb_writel_using_dma tegra_apb_writel_direct
@@ -293,12 +177,12 @@ static apbio_write_fptr apbio_write;
 
 static u32 tegra_apb_readl_direct(unsigned long offset)
 {
-       return readl(IO_TO_VIRT(offset));
+       return readl(IO_ADDRESS(offset));
 }
 
 static void tegra_apb_writel_direct(u32 value, unsigned long offset)
 {
-       writel(value, IO_TO_VIRT(offset));
+       writel(value, IO_ADDRESS(offset));
 }
 
 void tegra_apb_io_init(void)
index c099963..37007d6 100644 (file)
@@ -42,7 +42,6 @@
 #include <mach/irqs.h>
 
 #include "board.h"
-#include "board-harmony.h"
 #include "clock.h"
 #include "devices.h"
 
@@ -95,54 +94,40 @@ static void __init tegra_dt_init(void)
                                tegra20_auxdata_lookup, NULL);
 }
 
-#ifdef CONFIG_MACH_TRIMSLICE
 static void __init trimslice_init(void)
 {
+#ifdef CONFIG_TEGRA_PCI
        int ret;
 
        ret = tegra_pcie_init(true, true);
        if (ret)
                pr_err("tegra_pci_init() failed: %d\n", ret);
-}
 #endif
+}
 
-#ifdef CONFIG_MACH_HARMONY
 static void __init harmony_init(void)
 {
+#ifdef CONFIG_TEGRA_PCI
        int ret;
 
-       ret = harmony_regulator_init();
-       if (ret) {
-               pr_err("harmony_regulator_init() failed: %d\n", ret);
-               return;
-       }
-
        ret = harmony_pcie_init();
        if (ret)
                pr_err("harmony_pcie_init() failed: %d\n", ret);
-}
 #endif
+}
 
-#ifdef CONFIG_MACH_PAZ00
 static void __init paz00_init(void)
 {
        tegra_paz00_wifikill_init();
 }
-#endif
 
 static struct {
        char *machine;
        void (*init)(void);
 } board_init_funcs[] = {
-#ifdef CONFIG_MACH_TRIMSLICE
        { "compulab,trimslice", trimslice_init },
-#endif
-#ifdef CONFIG_MACH_HARMONY
        { "nvidia,harmony", harmony_init },
-#endif
-#ifdef CONFIG_MACH_PAZ00
        { "compal,paz00", paz00_init },
-#endif
 };
 
 static void __init tegra_dt_init_late(void)
index e8c3fda..3cdc1bb 100644 (file)
 #include <linux/kernel.h>
 #include <linux/gpio.h>
 #include <linux/err.h>
+#include <linux/of_gpio.h>
 #include <linux/regulator/consumer.h>
 
 #include <asm/mach-types.h>
 
 #include "board.h"
-#include "board-harmony.h"
 
 #ifdef CONFIG_TEGRA_PCI
 
 int __init harmony_pcie_init(void)
 {
+       struct device_node *np;
+       int en_vdd_1v05;
        struct regulator *regulator = NULL;
        int err;
 
-       err = gpio_request(TEGRA_GPIO_EN_VDD_1V05_GPIO, "EN_VDD_1V05");
-       if (err)
+       np = of_find_node_by_path("/regulators/regulator@3");
+       if (!np) {
+               pr_err("%s: of_find_node_by_path failed\n", __func__);
+               return -ENODEV;
+       }
+
+       en_vdd_1v05 = of_get_named_gpio(np, "gpio", 0);
+       if (en_vdd_1v05 < 0) {
+               pr_err("%s: of_get_named_gpio failed: %d\n", __func__,
+                      en_vdd_1v05);
+               return en_vdd_1v05;
+       }
+
+       err = gpio_request(en_vdd_1v05, "EN_VDD_1V05");
+       if (err) {
+               pr_err("%s: gpio_request failed: %d\n", __func__, err);
                return err;
+       }
 
-       gpio_direction_output(TEGRA_GPIO_EN_VDD_1V05_GPIO, 1);
+       gpio_direction_output(en_vdd_1v05, 1);
 
-       regulator = regulator_get(NULL, "pex_clk");
-       if (IS_ERR_OR_NULL(regulator))
+       regulator = regulator_get(NULL, "vdd_ldo0,vddio_pex_clk");
+       if (IS_ERR_OR_NULL(regulator)) {
+               pr_err("%s: regulator_get failed: %d\n", __func__,
+                      (int)PTR_ERR(regulator));
                goto err_reg;
+       }
 
        regulator_enable(regulator);
 
        err = tegra_pcie_init(true, true);
-       if (err)
+       if (err) {
+               pr_err("%s: tegra_pcie_init failed: %d\n", __func__, err);
                goto err_pcie;
+       }
 
        return 0;
 
@@ -54,20 +76,9 @@ err_pcie:
        regulator_disable(regulator);
        regulator_put(regulator);
 err_reg:
-       gpio_free(TEGRA_GPIO_EN_VDD_1V05_GPIO);
+       gpio_free(en_vdd_1v05);
 
        return err;
 }
 
-static int __init harmony_pcie_initcall(void)
-{
-       if (!machine_is_harmony())
-               return 0;
-
-       return harmony_pcie_init();
-}
-
-/* PCI should be initialized after I2C, mfd and regulators */
-subsys_initcall_sync(harmony_pcie_initcall);
-
 #endif
diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
deleted file mode 100644 (file)
index 83d420f..0000000
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-harmony-pinmux.c
- *
- * Copyright (C) 2010 Google, Inc.
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-
-#include "board-harmony.h"
-#include "board-pinmux.h"
-
-static struct pinctrl_map harmony_map[] = {
-       TEGRA_MAP_MUXCONF("ata",   "ide",           none, driven),
-       TEGRA_MAP_MUXCONF("atb",   "sdio4",         none, driven),
-       TEGRA_MAP_MUXCONF("atc",   "nand",          none, driven),
-       TEGRA_MAP_MUXCONF("atd",   "gmi",           none, driven),
-       TEGRA_MAP_MUXCONF("ate",   "gmi",           none, driven),
-       TEGRA_MAP_MUXCONF("cdev1", "plla_out",      none, driven),
-       TEGRA_MAP_MUXCONF("cdev2", "pllp_out4",     down, tristate),
-       TEGRA_MAP_MUXCONF("crtp",  "crt",           none, tristate),
-       TEGRA_MAP_MUXCONF("csus",  "vi_sensor_clk", down, tristate),
-       TEGRA_MAP_MUXCONF("dap1",  "dap1",          none, driven),
-       TEGRA_MAP_MUXCONF("dap2",  "dap2",          none, tristate),
-       TEGRA_MAP_MUXCONF("dap3",  "dap3",          none, tristate),
-       TEGRA_MAP_MUXCONF("dap4",  "dap4",          none, tristate),
-       TEGRA_MAP_MUXCONF("ddc",   "i2c2",          up,   driven),
-       TEGRA_MAP_MUXCONF("dta",   "sdio2",         up,   driven),
-       TEGRA_MAP_MUXCONF("dtb",   "rsvd1",         none, driven),
-       TEGRA_MAP_MUXCONF("dtc",   "rsvd1",         none, tristate),
-       TEGRA_MAP_MUXCONF("dtd",   "sdio2",         up,   driven),
-       TEGRA_MAP_MUXCONF("dte",   "rsvd1",         none, tristate),
-       TEGRA_MAP_MUXCONF("dtf",   "i2c3",          none, tristate),
-       TEGRA_MAP_MUXCONF("gma",   "sdio4",         none, driven),
-       TEGRA_MAP_MUXCONF("gmb",   "gmi",           none, driven),
-       TEGRA_MAP_MUXCONF("gmc",   "uartd",         none, driven),
-       TEGRA_MAP_MUXCONF("gmd",   "gmi",           none, driven),
-       TEGRA_MAP_MUXCONF("gme",   "sdio4",         none, driven),
-       TEGRA_MAP_MUXCONF("gpu",   "gmi",           none, tristate),
-       TEGRA_MAP_MUXCONF("gpu7",  "rtck",          none, driven),
-       TEGRA_MAP_MUXCONF("gpv",   "pcie",          none, driven),
-       TEGRA_MAP_MUXCONF("hdint", "hdmi",          na,   tristate),
-       TEGRA_MAP_MUXCONF("i2cp",  "i2cp",          none, driven),
-       TEGRA_MAP_MUXCONF("irrx",  "uarta",         up,   tristate),
-       TEGRA_MAP_MUXCONF("irtx",  "uarta",         up,   tristate),
-       TEGRA_MAP_MUXCONF("kbca",  "kbc",           up,   driven),
-       TEGRA_MAP_MUXCONF("kbcb",  "kbc",           up,   driven),
-       TEGRA_MAP_MUXCONF("kbcc",  "kbc",           up,   driven),
-       TEGRA_MAP_MUXCONF("kbcd",  "kbc",           up,   driven),
-       TEGRA_MAP_MUXCONF("kbce",  "kbc",           up,   driven),
-       TEGRA_MAP_MUXCONF("kbcf",  "kbc",           up,   driven),
-       TEGRA_MAP_MUXCONF("lcsn",  "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("ld0",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld1",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld10",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld11",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld12",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld13",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld14",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld15",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld16",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld17",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld2",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld3",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld4",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld5",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld6",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld7",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld8",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld9",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ldc",   "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("ldi",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("lhp0",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("lhp1",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("lhp2",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("lhs",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("lm0",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("lm1",   "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("lpp",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("lpw0",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("lpw1",  "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("lpw2",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("lsc0",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("lsc1",  "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("lsck",  "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("lsda",  "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("lsdi",  "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("lspi",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("lvp0",  "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("lvp1",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("lvs",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("owc",   "rsvd2",         na,   tristate),
-       TEGRA_MAP_MUXCONF("pmc",   "pwr_on",        na,   driven),
-       TEGRA_MAP_MUXCONF("pta",   "hdmi",          none, driven),
-       TEGRA_MAP_MUXCONF("rm",    "i2c1",          none, driven),
-       TEGRA_MAP_MUXCONF("sdb",   "pwm",           na,   tristate),
-       TEGRA_MAP_MUXCONF("sdc",   "pwm",           up,   driven),
-       TEGRA_MAP_MUXCONF("sdd",   "pwm",           up,   tristate),
-       TEGRA_MAP_MUXCONF("sdio1", "sdio1",         none, tristate),
-       TEGRA_MAP_MUXCONF("slxa",  "pcie",          none, driven),
-       TEGRA_MAP_MUXCONF("slxc",  "spdif",         none, tristate),
-       TEGRA_MAP_MUXCONF("slxd",  "spdif",         none, tristate),
-       TEGRA_MAP_MUXCONF("slxk",  "pcie",          none, driven),
-       TEGRA_MAP_MUXCONF("spdi",  "rsvd2",         none, tristate),
-       TEGRA_MAP_MUXCONF("spdo",  "rsvd2",         none, tristate),
-       TEGRA_MAP_MUXCONF("spia",  "gmi",           none, driven),
-       TEGRA_MAP_MUXCONF("spib",  "gmi",           none, driven),
-       TEGRA_MAP_MUXCONF("spic",  "gmi",           up,   tristate),
-       TEGRA_MAP_MUXCONF("spid",  "spi1",          down, tristate),
-       TEGRA_MAP_MUXCONF("spie",  "spi1",          up,   tristate),
-       TEGRA_MAP_MUXCONF("spif",  "spi1",          down, tristate),
-       TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      none, tristate),
-       TEGRA_MAP_MUXCONF("spih",  "spi2_alt",      up,   tristate),
-       TEGRA_MAP_MUXCONF("uaa",   "ulpi",          up,   tristate),
-       TEGRA_MAP_MUXCONF("uab",   "ulpi",          up,   tristate),
-       TEGRA_MAP_MUXCONF("uac",   "rsvd2",         none, tristate),
-       TEGRA_MAP_MUXCONF("uad",   "irda",          up,   tristate),
-       TEGRA_MAP_MUXCONF("uca",   "uartc",         up,   tristate),
-       TEGRA_MAP_MUXCONF("ucb",   "uartc",         up,   tristate),
-       TEGRA_MAP_MUXCONF("uda",   "ulpi",          none, tristate),
-       TEGRA_MAP_CONF("ck32",    none, na),
-       TEGRA_MAP_CONF("ddrc",    none, na),
-       TEGRA_MAP_CONF("pmca",    none, na),
-       TEGRA_MAP_CONF("pmcb",    none, na),
-       TEGRA_MAP_CONF("pmcc",    none, na),
-       TEGRA_MAP_CONF("pmcd",    none, na),
-       TEGRA_MAP_CONF("pmce",    none, na),
-       TEGRA_MAP_CONF("xm2c",    none, na),
-       TEGRA_MAP_CONF("xm2d",    none, na),
-       TEGRA_MAP_CONF("ls",      up,   na),
-       TEGRA_MAP_CONF("lc",      up,   na),
-       TEGRA_MAP_CONF("ld17_0",  down, na),
-       TEGRA_MAP_CONF("ld19_18", down, na),
-       TEGRA_MAP_CONF("ld21_20", down, na),
-       TEGRA_MAP_CONF("ld23_22", down, na),
-};
-
-static struct tegra_board_pinmux_conf conf = {
-       .maps = harmony_map,
-       .map_count = ARRAY_SIZE(harmony_map),
-};
-
-void harmony_pinmux_init(void)
-{
-       tegra_board_pinmux_init(&conf, NULL);
-}
diff --git a/arch/arm/mach-tegra/board-harmony-power.c b/arch/arm/mach-tegra/board-harmony-power.c
deleted file mode 100644 (file)
index 94486e7..0000000
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * Copyright (C) 2010 NVIDIA, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
- * 02111-1307, USA
- */
-#include <linux/i2c.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/mfd/tps6586x.h>
-#include <linux/of.h>
-#include <linux/of_i2c.h>
-
-#include <asm/mach-types.h>
-
-#include <mach/irqs.h>
-
-#include "board-harmony.h"
-
-static struct regulator_consumer_supply tps658621_ldo0_supply[] = {
-       REGULATOR_SUPPLY("pex_clk", NULL),
-};
-
-static struct regulator_init_data ldo0_data = {
-       .supply_regulator = "vdd_sm2",
-       .constraints = {
-               .name = "vdd_ldo0",
-               .min_uV = 3300 * 1000,
-               .max_uV = 3300 * 1000,
-               .valid_modes_mask = (REGULATOR_MODE_NORMAL |
-                                    REGULATOR_MODE_STANDBY),
-               .valid_ops_mask = (REGULATOR_CHANGE_MODE |
-                                  REGULATOR_CHANGE_STATUS |
-                                  REGULATOR_CHANGE_VOLTAGE),
-               .apply_uV = 1,
-       },
-       .num_consumer_supplies = ARRAY_SIZE(tps658621_ldo0_supply),
-       .consumer_supplies = tps658621_ldo0_supply,
-};
-
-#define HARMONY_REGULATOR_INIT(_id, _name, _supply, _minmv, _maxmv, _on)\
-       static struct regulator_init_data _id##_data = {                \
-               .supply_regulator = _supply,                            \
-               .constraints = {                                        \
-                       .name = _name,                                  \
-                       .min_uV = (_minmv)*1000,                        \
-                       .max_uV = (_maxmv)*1000,                        \
-                       .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
-                                            REGULATOR_MODE_STANDBY),   \
-                       .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
-                                          REGULATOR_CHANGE_STATUS |    \
-                                          REGULATOR_CHANGE_VOLTAGE),   \
-                       .always_on = _on,                               \
-               },                                                      \
-       }
-
-static struct regulator_init_data sys_data = {
-       .supply_regulator = "vdd_5v0",
-       .constraints = {
-               .name = "vdd_sys",
-       },
-};
-
-HARMONY_REGULATOR_INIT(sm0,  "vdd_sm0",  "vdd_sys", 725, 1500, 1);
-HARMONY_REGULATOR_INIT(sm1,  "vdd_sm1",  "vdd_sys", 725, 1500, 1);
-HARMONY_REGULATOR_INIT(sm2,  "vdd_sm2",  "vdd_sys", 3000, 4550, 1);
-HARMONY_REGULATOR_INIT(ldo1, "vdd_ldo1", "vdd_sm2", 725, 1500, 1);
-HARMONY_REGULATOR_INIT(ldo2, "vdd_ldo2", "vdd_sm2", 725, 1500, 0);
-HARMONY_REGULATOR_INIT(ldo3, "vdd_ldo3", "vdd_sm2", 1250, 3300, 1);
-HARMONY_REGULATOR_INIT(ldo4, "vdd_ldo4", "vdd_sm2", 1700, 2475, 1);
-HARMONY_REGULATOR_INIT(ldo5, "vdd_ldo5", "vdd_sys", 1250, 3300, 1);
-HARMONY_REGULATOR_INIT(ldo6, "vdd_ldo6", "vdd_sm2", 1250, 3300, 0);
-HARMONY_REGULATOR_INIT(ldo7, "vdd_ldo7", "vdd_sm2", 1250, 3300, 0);
-HARMONY_REGULATOR_INIT(ldo8, "vdd_ldo8", "vdd_sm2", 1250, 3300, 0);
-HARMONY_REGULATOR_INIT(ldo9, "vdd_ldo9", "vdd_sm2", 1250, 3300, 1);
-
-#define TPS_REG(_id, _data)                    \
-       {                                       \
-               .id = TPS6586X_ID_##_id,        \
-               .name = "tps6586x-regulator",   \
-               .platform_data = _data,         \
-       }
-
-static struct tps6586x_subdev_info tps_devs[] = {
-       TPS_REG(SYS, &sys_data),
-       TPS_REG(SM_0, &sm0_data),
-       TPS_REG(SM_1, &sm1_data),
-       TPS_REG(SM_2, &sm2_data),
-       TPS_REG(LDO_0, &ldo0_data),
-       TPS_REG(LDO_1, &ldo1_data),
-       TPS_REG(LDO_2, &ldo2_data),
-       TPS_REG(LDO_3, &ldo3_data),
-       TPS_REG(LDO_4, &ldo4_data),
-       TPS_REG(LDO_5, &ldo5_data),
-       TPS_REG(LDO_6, &ldo6_data),
-       TPS_REG(LDO_7, &ldo7_data),
-       TPS_REG(LDO_8, &ldo8_data),
-       TPS_REG(LDO_9, &ldo9_data),
-};
-
-static struct tps6586x_platform_data tps_platform = {
-       .irq_base       = TEGRA_NR_IRQS,
-       .num_subdevs    = ARRAY_SIZE(tps_devs),
-       .subdevs        = tps_devs,
-       .gpio_base      = HARMONY_GPIO_TPS6586X(0),
-};
-
-static struct i2c_board_info __initdata harmony_regulators[] = {
-       {
-               I2C_BOARD_INFO("tps6586x", 0x34),
-               .irq            = INT_EXTERNAL_PMU,
-               .platform_data  = &tps_platform,
-       },
-};
-
-int __init harmony_regulator_init(void)
-{
-       regulator_register_always_on(0, "vdd_5v0",
-               NULL, 0, 5000000);
-
-       if (machine_is_harmony()) {
-               i2c_register_board_info(3, harmony_regulators, 1);
-       } else { /* Harmony, booted using device tree */
-               struct device_node *np;
-               struct i2c_adapter *adapter;
-
-               np = of_find_node_by_path("/i2c@7000d000");
-               if (np == NULL) {
-                       pr_err("Could not find device_node for DVC I2C\n");
-                       return -ENODEV;
-               }
-
-               adapter = of_find_i2c_adapter_by_node(np);
-               if (!adapter) {
-                       pr_err("Could not find i2c_adapter for DVC I2C\n");
-                       return -ENODEV;
-               }
-
-               i2c_new_device(adapter, harmony_regulators);
-       }
-
-       return 0;
-}
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
deleted file mode 100644 (file)
index e65e837..0000000
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-harmony.c
- *
- * Copyright (C) 2010 Google, Inc.
- * Copyright (C) 2011 NVIDIA, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/of_serial.h>
-#include <linux/clk.h>
-#include <linux/dma-mapping.h>
-#include <linux/pda_power.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/i2c.h>
-
-#include <sound/wm8903.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/hardware/gic.h>
-#include <asm/setup.h>
-
-#include <mach/tegra_wm8903_pdata.h>
-#include <mach/iomap.h>
-#include <mach/irqs.h>
-#include <mach/sdhci.h>
-
-#include "board.h"
-#include "board-harmony.h"
-#include "clock.h"
-#include "devices.h"
-#include "gpio-names.h"
-
-static struct plat_serial8250_port debug_uart_platform_data[] = {
-       {
-               .membase        = IO_ADDRESS(TEGRA_UARTD_BASE),
-               .mapbase        = TEGRA_UARTD_BASE,
-               .irq            = INT_UARTD,
-               .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
-               .type           = PORT_TEGRA,
-               .handle_break   = tegra_serial_handle_break,
-               .iotype         = UPIO_MEM,
-               .regshift       = 2,
-               .uartclk        = 216000000,
-       }, {
-               .flags          = 0
-       }
-};
-
-static struct platform_device debug_uart = {
-       .name = "serial8250",
-       .id = PLAT8250_DEV_PLATFORM,
-       .dev = {
-               .platform_data = debug_uart_platform_data,
-       },
-};
-
-static struct tegra_wm8903_platform_data harmony_audio_pdata = {
-       .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
-       .gpio_hp_det            = TEGRA_GPIO_HP_DET,
-       .gpio_hp_mute           = -1,
-       .gpio_int_mic_en        = TEGRA_GPIO_INT_MIC_EN,
-       .gpio_ext_mic_en        = TEGRA_GPIO_EXT_MIC_EN,
-};
-
-static struct platform_device harmony_audio_device = {
-       .name   = "tegra-snd-wm8903",
-       .id     = 0,
-       .dev    = {
-               .platform_data  = &harmony_audio_pdata,
-       },
-};
-
-static struct wm8903_platform_data harmony_wm8903_pdata = {
-       .irq_active_low = 0,
-       .micdet_cfg = 0,
-       .micdet_delay = 100,
-       .gpio_base = HARMONY_GPIO_WM8903(0),
-       .gpio_cfg = {
-               0,
-               0,
-               WM8903_GPIO_CONFIG_ZERO,
-               0,
-               0,
-       },
-};
-
-static struct i2c_board_info __initdata wm8903_board_info = {
-       I2C_BOARD_INFO("wm8903", 0x1a),
-       .platform_data = &harmony_wm8903_pdata,
-};
-
-static void __init harmony_i2c_init(void)
-{
-       platform_device_register(&tegra_i2c_device1);
-       platform_device_register(&tegra_i2c_device2);
-       platform_device_register(&tegra_i2c_device3);
-       platform_device_register(&tegra_i2c_device4);
-
-       wm8903_board_info.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
-       i2c_register_board_info(0, &wm8903_board_info, 1);
-}
-
-static struct platform_device *harmony_devices[] __initdata = {
-       &debug_uart,
-       &tegra_sdhci_device1,
-       &tegra_sdhci_device2,
-       &tegra_sdhci_device4,
-       &tegra_ehci3_device,
-       &tegra_i2s_device1,
-       &tegra_das_device,
-       &harmony_audio_device,
-};
-
-static void __init tegra_harmony_fixup(struct tag *tags, char **cmdline,
-       struct meminfo *mi)
-{
-       mi->nr_banks = 2;
-       mi->bank[0].start = PHYS_OFFSET;
-       mi->bank[0].size = 448 * SZ_1M;
-       mi->bank[1].start = SZ_512M;
-       mi->bank[1].size = SZ_512M;
-}
-
-static __initdata struct tegra_clk_init_table harmony_clk_init_table[] = {
-       /* name         parent          rate            enabled */
-       { "uartd",      "pll_p",        216000000,      true },
-       { "pll_a",      "pll_p_out1",   56448000,       true },
-       { "pll_a_out0", "pll_a",        11289600,       true },
-       { "cdev1",      NULL,           0,              true },
-       { "i2s1",       "pll_a_out0",   11289600,       false},
-       { "usb3",       "clk_m",        12000000,       true },
-       { NULL,         NULL,           0,              0},
-};
-
-
-static struct tegra_sdhci_platform_data sdhci_pdata1 = {
-       .cd_gpio        = -1,
-       .wp_gpio        = -1,
-       .power_gpio     = -1,
-};
-
-static struct tegra_sdhci_platform_data sdhci_pdata2 = {
-       .cd_gpio        = TEGRA_GPIO_SD2_CD,
-       .wp_gpio        = TEGRA_GPIO_SD2_WP,
-       .power_gpio     = TEGRA_GPIO_SD2_POWER,
-};
-
-static struct tegra_sdhci_platform_data sdhci_pdata4 = {
-       .cd_gpio        = TEGRA_GPIO_SD4_CD,
-       .wp_gpio        = TEGRA_GPIO_SD4_WP,
-       .power_gpio     = TEGRA_GPIO_SD4_POWER,
-       .is_8bit        = 1,
-};
-
-static void __init tegra_harmony_init(void)
-{
-       tegra_clk_init_from_table(harmony_clk_init_table);
-
-       harmony_pinmux_init();
-
-       tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1;
-       tegra_sdhci_device2.dev.platform_data = &sdhci_pdata2;
-       tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
-
-       platform_add_devices(harmony_devices, ARRAY_SIZE(harmony_devices));
-       harmony_i2c_init();
-       harmony_regulator_init();
-}
-
-MACHINE_START(HARMONY, "harmony")
-       .atag_offset    = 0x100,
-       .fixup          = tegra_harmony_fixup,
-       .map_io         = tegra_map_common_io,
-       .init_early     = tegra20_init_early,
-       .init_irq       = tegra_init_irq,
-       .handle_irq     = gic_handle_irq,
-       .timer          = &tegra_timer,
-       .init_machine   = tegra_harmony_init,
-       .init_late      = tegra_init_late,
-       .restart        = tegra_assert_system_reset,
-MACHINE_END
diff --git a/arch/arm/mach-tegra/board-harmony.h b/arch/arm/mach-tegra/board-harmony.h
deleted file mode 100644 (file)
index 139d96c..0000000
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-harmony.h
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _MACH_TEGRA_BOARD_HARMONY_H
-#define _MACH_TEGRA_BOARD_HARMONY_H
-
-#include <mach/gpio-tegra.h>
-
-#define HARMONY_GPIO_TPS6586X(_x_)     (TEGRA_NR_GPIOS + (_x_))
-#define HARMONY_GPIO_WM8903(_x_)       (HARMONY_GPIO_TPS6586X(4) + (_x_))
-
-#define TEGRA_GPIO_SD2_CD              TEGRA_GPIO_PI5
-#define TEGRA_GPIO_SD2_WP              TEGRA_GPIO_PH1
-#define TEGRA_GPIO_SD2_POWER           TEGRA_GPIO_PT3
-#define TEGRA_GPIO_SD4_CD              TEGRA_GPIO_PH2
-#define TEGRA_GPIO_SD4_WP              TEGRA_GPIO_PH3
-#define TEGRA_GPIO_SD4_POWER           TEGRA_GPIO_PI6
-#define TEGRA_GPIO_CDC_IRQ             TEGRA_GPIO_PX3
-#define TEGRA_GPIO_SPKR_EN             HARMONY_GPIO_WM8903(2)
-#define TEGRA_GPIO_HP_DET              TEGRA_GPIO_PW2
-#define TEGRA_GPIO_INT_MIC_EN          TEGRA_GPIO_PX0
-#define TEGRA_GPIO_EXT_MIC_EN          TEGRA_GPIO_PX1
-#define TEGRA_GPIO_EN_VDD_1V05_GPIO    HARMONY_GPIO_TPS6586X(2)
-
-void harmony_pinmux_init(void);
-int harmony_regulator_init(void);
-
-#endif
diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c
deleted file mode 100644 (file)
index 6f1111b..0000000
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-paz00-pinmux.c
- *
- * Copyright (C) 2010 Marc Dietrich <marvin24@gmx.de>
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-
-#include "board-paz00.h"
-#include "board-pinmux.h"
-
-static struct pinctrl_map paz00_map[] = {
-       TEGRA_MAP_MUXCONF("ata",   "gmi",           none, driven),
-       TEGRA_MAP_MUXCONF("atb",   "sdio4",         none, driven),
-       TEGRA_MAP_MUXCONF("atc",   "gmi",           none, driven),
-       TEGRA_MAP_MUXCONF("atd",   "gmi",           none, driven),
-       TEGRA_MAP_MUXCONF("ate",   "gmi",           none, driven),
-       TEGRA_MAP_MUXCONF("cdev1", "plla_out",      none, driven),
-       TEGRA_MAP_MUXCONF("cdev2", "pllp_out4",     down, driven),
-       TEGRA_MAP_MUXCONF("crtp",  "crt",           none, tristate),
-       TEGRA_MAP_MUXCONF("csus",  "pllc_out1",     down, tristate),
-       TEGRA_MAP_MUXCONF("dap1",  "dap1",          none, driven),
-       TEGRA_MAP_MUXCONF("dap2",  "gmi",           none, driven),
-       TEGRA_MAP_MUXCONF("dap3",  "dap3",          none, tristate),
-       TEGRA_MAP_MUXCONF("dap4",  "dap4",          none, tristate),
-       TEGRA_MAP_MUXCONF("ddc",   "i2c2",          up,   driven),
-       TEGRA_MAP_MUXCONF("dta",   "rsvd1",         up,   tristate),
-       TEGRA_MAP_MUXCONF("dtb",   "rsvd1",         none, tristate),
-       TEGRA_MAP_MUXCONF("dtc",   "rsvd1",         none, tristate),
-       TEGRA_MAP_MUXCONF("dtd",   "rsvd1",         up,   tristate),
-       TEGRA_MAP_MUXCONF("dte",   "rsvd1",         none, tristate),
-       TEGRA_MAP_MUXCONF("dtf",   "i2c3",          none, driven),
-       TEGRA_MAP_MUXCONF("gma",   "sdio4",         none, driven),
-       TEGRA_MAP_MUXCONF("gmb",   "gmi",           none, driven),
-       TEGRA_MAP_MUXCONF("gmc",   "gmi",           none, driven),
-       TEGRA_MAP_MUXCONF("gmd",   "gmi",           none, driven),
-       TEGRA_MAP_MUXCONF("gme",   "sdio4",         none, driven),
-       TEGRA_MAP_MUXCONF("gpu",   "pwm",           none, driven),
-       TEGRA_MAP_MUXCONF("gpu7",  "rtck",          none, driven),
-       TEGRA_MAP_MUXCONF("gpv",   "pcie",          none, driven),
-       TEGRA_MAP_MUXCONF("hdint", "hdmi",          na,   driven),
-       TEGRA_MAP_MUXCONF("i2cp",  "i2cp",          none, driven),
-       TEGRA_MAP_MUXCONF("irrx",  "uarta",         up,   driven),
-       TEGRA_MAP_MUXCONF("irtx",  "uarta",         up,   driven),
-       TEGRA_MAP_MUXCONF("kbca",  "kbc",           up,   driven),
-       TEGRA_MAP_MUXCONF("kbcb",  "sdio2",         up,   driven),
-       TEGRA_MAP_MUXCONF("kbcc",  "kbc",           up,   driven),
-       TEGRA_MAP_MUXCONF("kbcd",  "sdio2",         up,   driven),
-       TEGRA_MAP_MUXCONF("kbce",  "kbc",           up,   driven),
-       TEGRA_MAP_MUXCONF("kbcf",  "kbc",           up,   driven),
-       TEGRA_MAP_MUXCONF("lcsn",  "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("ld0",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld1",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld10",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld11",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld12",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld13",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld14",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld15",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld16",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld17",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld2",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld3",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld4",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld5",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld6",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld7",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld8",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld9",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ldc",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ldi",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("lhp0",  "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("lhp1",  "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("lhp2",  "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("lhs",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("lm0",   "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("lm1",   "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("lpp",   "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("lpw0",  "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("lpw1",  "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("lpw2",  "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("lsc0",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("lsc1",  "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("lsck",  "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("lsda",  "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("lsdi",  "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("lspi",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("lvp0",  "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("lvp1",  "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("lvs",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("owc",   "owr",           up,   tristate),
-       TEGRA_MAP_MUXCONF("pmc",   "pwr_on",        na,   driven),
-       TEGRA_MAP_MUXCONF("pta",   "hdmi",          none, driven),
-       TEGRA_MAP_MUXCONF("rm",    "i2c1",          none, driven),
-       TEGRA_MAP_MUXCONF("sdb",   "pwm",           na,   tristate),
-       TEGRA_MAP_MUXCONF("sdc",   "twc",           up,   tristate),
-       TEGRA_MAP_MUXCONF("sdd",   "pwm",           up,   tristate),
-       TEGRA_MAP_MUXCONF("sdio1", "sdio1",         none, driven),
-       TEGRA_MAP_MUXCONF("slxa",  "pcie",          none, tristate),
-       TEGRA_MAP_MUXCONF("slxc",  "spi4",          none, tristate),
-       TEGRA_MAP_MUXCONF("slxd",  "spi4",          none, tristate),
-       TEGRA_MAP_MUXCONF("slxk",  "pcie",          none, driven),
-       TEGRA_MAP_MUXCONF("spdi",  "rsvd2",         none, tristate),
-       TEGRA_MAP_MUXCONF("spdo",  "rsvd2",         none, driven),
-       TEGRA_MAP_MUXCONF("spia",  "gmi",           down, tristate),
-       TEGRA_MAP_MUXCONF("spib",  "gmi",           down, tristate),
-       TEGRA_MAP_MUXCONF("spic",  "gmi",           up,   driven),
-       TEGRA_MAP_MUXCONF("spid",  "gmi",           down, tristate),
-       TEGRA_MAP_MUXCONF("spie",  "gmi",           up,   tristate),
-       TEGRA_MAP_MUXCONF("spif",  "rsvd4",         down, tristate),
-       TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      up,   driven),
-       TEGRA_MAP_MUXCONF("spih",  "spi2_alt",      up,   tristate),
-       TEGRA_MAP_MUXCONF("uaa",   "ulpi",          up,   driven),
-       TEGRA_MAP_MUXCONF("uab",   "ulpi",          up,   driven),
-       TEGRA_MAP_MUXCONF("uac",   "rsvd4",         none, driven),
-       TEGRA_MAP_MUXCONF("uad",   "spdif",         up,   tristate),
-       TEGRA_MAP_MUXCONF("uca",   "uartc",         up,   tristate),
-       TEGRA_MAP_MUXCONF("ucb",   "uartc",         up,   tristate),
-       TEGRA_MAP_MUXCONF("uda",   "ulpi",          none, driven),
-       TEGRA_MAP_CONF("ck32",    none, na),
-       TEGRA_MAP_CONF("ddrc",    none, na),
-       TEGRA_MAP_CONF("pmca",    none, na),
-       TEGRA_MAP_CONF("pmcb",    none, na),
-       TEGRA_MAP_CONF("pmcc",    none, na),
-       TEGRA_MAP_CONF("pmcd",    none, na),
-       TEGRA_MAP_CONF("pmce",    none, na),
-       TEGRA_MAP_CONF("xm2c",    none, na),
-       TEGRA_MAP_CONF("xm2d",    none, na),
-       TEGRA_MAP_CONF("ls",      up,   na),
-       TEGRA_MAP_CONF("lc",      up,   na),
-       TEGRA_MAP_CONF("ld17_0",  down, na),
-       TEGRA_MAP_CONF("ld19_18", down, na),
-       TEGRA_MAP_CONF("ld21_20", down, na),
-       TEGRA_MAP_CONF("ld23_22", down, na),
-};
-
-static struct tegra_board_pinmux_conf conf = {
-       .maps = paz00_map,
-       .map_count = ARRAY_SIZE(paz00_map),
-};
-
-void paz00_pinmux_init(void)
-{
-       tegra_board_pinmux_init(&conf, NULL);
-}
index 4b64af5..5930551 100644 (file)
  *
  */
 
-#include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/of_serial.h>
-#include <linux/clk.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio_keys.h>
-#include <linux/pda_power.h>
-#include <linux/io.h>
-#include <linux/input.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
 #include <linux/rfkill-gpio.h>
 
-#include <asm/hardware/gic.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/setup.h>
-
-#include <mach/iomap.h>
-#include <mach/irqs.h>
-#include <mach/sdhci.h>
-
-#include "board.h"
 #include "board-paz00.h"
-#include "clock.h"
-#include "devices.h"
-#include "gpio-names.h"
-
-static struct plat_serial8250_port debug_uart_platform_data[] = {
-       {
-               /* serial port on JP1 */
-               .membase        = IO_ADDRESS(TEGRA_UARTA_BASE),
-               .mapbase        = TEGRA_UARTA_BASE,
-               .irq            = INT_UARTA,
-               .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
-               .type           = PORT_TEGRA,
-               .handle_break   = tegra_serial_handle_break,
-               .iotype         = UPIO_MEM,
-               .regshift       = 2,
-               .uartclk        = 216000000,
-       }, {
-               /* serial port on mini-pcie */
-               .membase        = IO_ADDRESS(TEGRA_UARTC_BASE),
-               .mapbase        = TEGRA_UARTC_BASE,
-               .irq            = INT_UARTC,
-               .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
-               .type           = PORT_TEGRA,
-               .handle_break   = tegra_serial_handle_break,
-               .iotype         = UPIO_MEM,
-               .regshift       = 2,
-               .uartclk        = 216000000,
-       }, {
-               .flags          = 0
-       }
-};
-
-static struct platform_device debug_uart = {
-       .name = "serial8250",
-       .id = PLAT8250_DEV_PLATFORM,
-       .dev = {
-               .platform_data = debug_uart_platform_data,
-       },
-};
 
 static struct rfkill_gpio_platform_data wifi_rfkill_platform_data = {
        .name           = "wifi_rfkill",
@@ -99,137 +37,7 @@ static struct platform_device wifi_rfkill_device = {
        },
 };
 
-static struct gpio_led gpio_leds[] = {
-       {
-               .name                   = "wifi-led",
-               .default_trigger        = "rfkill0",
-               .gpio                   = TEGRA_WIFI_LED,
-       },
-};
-
-static struct gpio_led_platform_data gpio_led_info = {
-       .leds           = gpio_leds,
-       .num_leds       = ARRAY_SIZE(gpio_leds),
-};
-
-static struct platform_device leds_gpio = {
-       .name   = "leds-gpio",
-       .id     = -1,
-       .dev    = {
-               .platform_data = &gpio_led_info,
-        },
-};
-
-static struct gpio_keys_button paz00_gpio_keys_buttons[] = {
-       {
-               .code           = KEY_POWER,
-               .gpio           = TEGRA_GPIO_POWERKEY,
-               .active_low     = 1,
-               .desc           = "Power",
-               .type           = EV_KEY,
-               .wakeup         = 1,
-       },
-};
-
-static struct gpio_keys_platform_data paz00_gpio_keys = {
-       .buttons        = paz00_gpio_keys_buttons,
-       .nbuttons       = ARRAY_SIZE(paz00_gpio_keys_buttons),
-};
-
-static struct platform_device gpio_keys_device = {
-       .name   = "gpio-keys",
-       .id     = -1,
-       .dev    = {
-               .platform_data = &paz00_gpio_keys,
-       },
-};
-
-static struct platform_device *paz00_devices[] __initdata = {
-       &debug_uart,
-       &tegra_sdhci_device4,
-       &tegra_sdhci_device1,
-       &leds_gpio,
-       &gpio_keys_device,
-};
-
-static void paz00_i2c_init(void)
-{
-       platform_device_register(&tegra_i2c_device1);
-       platform_device_register(&tegra_i2c_device2);
-       platform_device_register(&tegra_i2c_device4);
-}
-
-static void paz00_usb_init(void)
-{
-       tegra_ehci2_ulpi_phy_config.reset_gpio = TEGRA_ULPI_RST;
-
-       platform_device_register(&tegra_ehci2_device);
-       platform_device_register(&tegra_ehci3_device);
-}
-
-static void __init tegra_paz00_fixup(struct tag *tags, char **cmdline,
-       struct meminfo *mi)
-{
-       mi->nr_banks = 1;
-       mi->bank[0].start = PHYS_OFFSET;
-       mi->bank[0].size = 448 * SZ_1M;
-}
-
-static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = {
-       /* name         parent          rate            enabled */
-       { "uarta",      "pll_p",        216000000,      true },
-       { "uartc",      "pll_p",        216000000,      true },
-
-       { "usbd",       "clk_m",        12000000,       false },
-       { "usb2",       "clk_m",        12000000,       false },
-       { "usb3",       "clk_m",        12000000,       false },
-
-       { NULL,         NULL,           0,              0},
-};
-
-static struct tegra_sdhci_platform_data sdhci_pdata1 = {
-       .cd_gpio        = TEGRA_GPIO_SD1_CD,
-       .wp_gpio        = TEGRA_GPIO_SD1_WP,
-       .power_gpio     = TEGRA_GPIO_SD1_POWER,
-};
-
-static struct tegra_sdhci_platform_data sdhci_pdata4 = {
-       .cd_gpio        = -1,
-       .wp_gpio        = -1,
-       .power_gpio     = -1,
-       .is_8bit        = 1,
-};
-
 void __init tegra_paz00_wifikill_init(void)
 {
        platform_device_register(&wifi_rfkill_device);
 }
-
-static void __init tegra_paz00_init(void)
-{
-       tegra_clk_init_from_table(paz00_clk_init_table);
-
-       paz00_pinmux_init();
-
-       tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1;
-       tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
-
-       platform_add_devices(paz00_devices, ARRAY_SIZE(paz00_devices));
-       tegra_paz00_wifikill_init();
-
-       paz00_i2c_init();
-       paz00_usb_init();
-}
-
-MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ")
-       .atag_offset    = 0x100,
-       .fixup          = tegra_paz00_fixup,
-       .map_io         = tegra_map_common_io,
-       .init_early     = tegra20_init_early,
-       .init_irq       = tegra_init_irq,
-       .handle_irq     = gic_handle_irq,
-       .timer          = &tegra_timer,
-       .init_machine   = tegra_paz00_init,
-       .init_late      = tegra_init_late,
-       .restart        = tegra_assert_system_reset,
-MACHINE_END
index 3c9f8da..25c08ec 100644 (file)
 #ifndef _MACH_TEGRA_BOARD_PAZ00_H
 #define _MACH_TEGRA_BOARD_PAZ00_H
 
-#include <mach/gpio-tegra.h>
+#include "gpio-names.h"
 
-/* SDCARD */
-#define TEGRA_GPIO_SD1_CD              TEGRA_GPIO_PV5
-#define TEGRA_GPIO_SD1_WP              TEGRA_GPIO_PH1
-#define TEGRA_GPIO_SD1_POWER           TEGRA_GPIO_PV1
-
-/* ULPI */
-#define TEGRA_ULPI_RST                 TEGRA_GPIO_PV0
-
-/* WIFI */
 #define TEGRA_WIFI_PWRN                        TEGRA_GPIO_PK5
 #define TEGRA_WIFI_RST                 TEGRA_GPIO_PD1
-#define TEGRA_WIFI_LED                 TEGRA_GPIO_PD0
-
-/* WakeUp */
-#define TEGRA_GPIO_POWERKEY    TEGRA_GPIO_PJ7
-
-void paz00_pinmux_init(void);
 
 #endif
diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c
deleted file mode 100644 (file)
index 7b39511..0000000
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-trimslice-pinmux.c
- *
- * Copyright (C) 2011 CompuLab, Ltd.
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/kernel.h>
-
-#include "board-trimslice.h"
-#include "board-pinmux.h"
-
-static struct pinctrl_map trimslice_map[] = {
-       TEGRA_MAP_MUXCONF("ata",   "ide",           none, tristate),
-       TEGRA_MAP_MUXCONF("atb",   "sdio4",         none, driven),
-       TEGRA_MAP_MUXCONF("atc",   "nand",          none, tristate),
-       TEGRA_MAP_MUXCONF("atd",   "gmi",           none, tristate),
-       TEGRA_MAP_MUXCONF("ate",   "gmi",           none, tristate),
-       TEGRA_MAP_MUXCONF("cdev1", "plla_out",      none, driven),
-       TEGRA_MAP_MUXCONF("cdev2", "pllp_out4",     down, tristate),
-       TEGRA_MAP_MUXCONF("crtp",  "crt",           none, tristate),
-       TEGRA_MAP_MUXCONF("csus",  "vi_sensor_clk", down, tristate),
-       TEGRA_MAP_MUXCONF("dap1",  "dap1",          none, driven),
-       TEGRA_MAP_MUXCONF("dap2",  "dap2",          none, tristate),
-       TEGRA_MAP_MUXCONF("dap3",  "dap3",          none, tristate),
-       TEGRA_MAP_MUXCONF("dap4",  "dap4",          none, tristate),
-       TEGRA_MAP_MUXCONF("ddc",   "i2c2",          up,   driven),
-       TEGRA_MAP_MUXCONF("dta",   "vi",            none, tristate),
-       TEGRA_MAP_MUXCONF("dtb",   "vi",            none, tristate),
-       TEGRA_MAP_MUXCONF("dtc",   "vi",            none, tristate),
-       TEGRA_MAP_MUXCONF("dtd",   "vi",            none, tristate),
-       TEGRA_MAP_MUXCONF("dte",   "vi",            none, tristate),
-       TEGRA_MAP_MUXCONF("dtf",   "i2c3",          up,   driven),
-       TEGRA_MAP_MUXCONF("gma",   "sdio4",         none, driven),
-       TEGRA_MAP_MUXCONF("gmb",   "nand",          none, tristate),
-       TEGRA_MAP_MUXCONF("gmc",   "sflash",        none, driven),
-       TEGRA_MAP_MUXCONF("gmd",   "sflash",        none, driven),
-       TEGRA_MAP_MUXCONF("gme",   "gmi",           none, tristate),
-       TEGRA_MAP_MUXCONF("gpu",   "uarta",         none, driven),
-       TEGRA_MAP_MUXCONF("gpu7",  "rtck",          none, driven),
-       TEGRA_MAP_MUXCONF("gpv",   "pcie",          none, driven),
-       TEGRA_MAP_MUXCONF("hdint", "hdmi",          na,   tristate),
-       TEGRA_MAP_MUXCONF("i2cp",  "i2cp",          none, tristate),
-       TEGRA_MAP_MUXCONF("irrx",  "uartb",         up,   tristate),
-       TEGRA_MAP_MUXCONF("irtx",  "uartb",         up,   tristate),
-       TEGRA_MAP_MUXCONF("kbca",  "kbc",           up,   tristate),
-       TEGRA_MAP_MUXCONF("kbcb",  "kbc",           up,   tristate),
-       TEGRA_MAP_MUXCONF("kbcc",  "kbc",           up,   tristate),
-       TEGRA_MAP_MUXCONF("kbcd",  "kbc",           up,   tristate),
-       TEGRA_MAP_MUXCONF("kbce",  "kbc",           up,   tristate),
-       TEGRA_MAP_MUXCONF("kbcf",  "kbc",           up,   tristate),
-       TEGRA_MAP_MUXCONF("lcsn",  "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("ld0",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld1",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld10",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld11",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld12",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld13",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld14",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld15",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld16",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld17",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld2",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld3",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld4",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld5",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld6",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld7",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld8",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ld9",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("ldc",   "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("ldi",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("lhp0",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("lhp1",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("lhp2",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("lhs",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("lm0",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("lm1",   "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("lpp",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("lpw0",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("lpw1",  "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("lpw2",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("lsc0",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("lsc1",  "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("lsck",  "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("lsda",  "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("lsdi",  "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("lspi",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("lvp0",  "displaya",      na,   tristate),
-       TEGRA_MAP_MUXCONF("lvp1",  "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("lvs",   "displaya",      na,   driven),
-       TEGRA_MAP_MUXCONF("owc",   "rsvd2",         up,   tristate),
-       TEGRA_MAP_MUXCONF("pmc",   "pwr_on",        na,   tristate),
-       TEGRA_MAP_MUXCONF("pta",   "gmi",           none, tristate),
-       TEGRA_MAP_MUXCONF("rm",    "i2c1",          up,   driven),
-       TEGRA_MAP_MUXCONF("sdb",   "pwm",           na,   driven),
-       TEGRA_MAP_MUXCONF("sdc",   "pwm",           up,   driven),
-       TEGRA_MAP_MUXCONF("sdd",   "pwm",           up,   driven),
-       TEGRA_MAP_MUXCONF("sdio1", "sdio1",         none, driven),
-       TEGRA_MAP_MUXCONF("slxa",  "pcie",          none, driven),
-       TEGRA_MAP_MUXCONF("slxc",  "sdio3",         none, tristate),
-       TEGRA_MAP_MUXCONF("slxd",  "sdio3",         none, tristate),
-       TEGRA_MAP_MUXCONF("slxk",  "pcie",          none, driven),
-       TEGRA_MAP_MUXCONF("spdi",  "spdif",         none, tristate),
-       TEGRA_MAP_MUXCONF("spdo",  "spdif",         none, tristate),
-       TEGRA_MAP_MUXCONF("spia",  "spi2",          down, tristate),
-       TEGRA_MAP_MUXCONF("spib",  "spi2",          down, tristate),
-       TEGRA_MAP_MUXCONF("spic",  "spi2",          up,   tristate),
-       TEGRA_MAP_MUXCONF("spid",  "spi1",          down, tristate),
-       TEGRA_MAP_MUXCONF("spie",  "spi1",          up,   tristate),
-       TEGRA_MAP_MUXCONF("spif",  "spi1",          down, tristate),
-       TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      up,   tristate),
-       TEGRA_MAP_MUXCONF("spih",  "spi2_alt",      up,   tristate),
-       TEGRA_MAP_MUXCONF("uaa",   "ulpi",          up,   tristate),
-       TEGRA_MAP_MUXCONF("uab",   "ulpi",          up,   tristate),
-       TEGRA_MAP_MUXCONF("uac",   "rsvd2",         none, driven),
-       TEGRA_MAP_MUXCONF("uad",   "irda",          up,   tristate),
-       TEGRA_MAP_MUXCONF("uca",   "uartc",         up,   tristate),
-       TEGRA_MAP_MUXCONF("ucb",   "uartc",         up,   tristate),
-       TEGRA_MAP_MUXCONF("uda",   "ulpi",          none, tristate),
-       TEGRA_MAP_CONF("ck32",    none, na),
-       TEGRA_MAP_CONF("ddrc",    none, na),
-       TEGRA_MAP_CONF("pmca",    none, na),
-       TEGRA_MAP_CONF("pmcb",    none, na),
-       TEGRA_MAP_CONF("pmcc",    none, na),
-       TEGRA_MAP_CONF("pmcd",    none, na),
-       TEGRA_MAP_CONF("pmce",    none, na),
-       TEGRA_MAP_CONF("xm2c",    none, na),
-       TEGRA_MAP_CONF("xm2d",    none, na),
-       TEGRA_MAP_CONF("ls",      up,   na),
-       TEGRA_MAP_CONF("lc",      up,   na),
-       TEGRA_MAP_CONF("ld17_0",  down, na),
-       TEGRA_MAP_CONF("ld19_18", down, na),
-       TEGRA_MAP_CONF("ld21_20", down, na),
-       TEGRA_MAP_CONF("ld23_22", down, na),
-};
-
-static struct tegra_board_pinmux_conf conf = {
-       .maps = trimslice_map,
-       .map_count = ARRAY_SIZE(trimslice_map),
-};
-
-void trimslice_pinmux_init(void)
-{
-       tegra_board_pinmux_init(&conf, NULL);
-}
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
deleted file mode 100644 (file)
index 776aa95..0000000
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-trimslice.c
- *
- * Copyright (C) 2011 CompuLab, Ltd.
- * Author: Mike Rapoport <mike@compulab.co.il>
- *
- * Based on board-harmony.c
- * Copyright (C) 2010 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/of_serial.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/platform_data/tegra_usb.h>
-
-#include <asm/hardware/gic.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/setup.h>
-
-#include <mach/iomap.h>
-#include <mach/sdhci.h>
-
-#include "board.h"
-#include "clock.h"
-#include "devices.h"
-#include "gpio-names.h"
-
-#include "board-trimslice.h"
-
-static struct plat_serial8250_port debug_uart_platform_data[] = {
-       {
-               .membase        = IO_ADDRESS(TEGRA_UARTA_BASE),
-               .mapbase        = TEGRA_UARTA_BASE,
-               .irq            = INT_UARTA,
-               .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
-               .type           = PORT_TEGRA,
-               .handle_break   = tegra_serial_handle_break,
-               .iotype         = UPIO_MEM,
-               .regshift       = 2,
-               .uartclk        = 216000000,
-       }, {
-               .flags          = 0
-       }
-};
-
-static struct platform_device debug_uart = {
-       .name   = "serial8250",
-       .id     = PLAT8250_DEV_PLATFORM,
-       .dev    = {
-               .platform_data  = debug_uart_platform_data,
-       },
-};
-static struct tegra_sdhci_platform_data sdhci_pdata1 = {
-       .cd_gpio        = -1,
-       .wp_gpio        = -1,
-       .power_gpio     = -1,
-};
-
-static struct tegra_sdhci_platform_data sdhci_pdata4 = {
-       .cd_gpio        = TRIMSLICE_GPIO_SD4_CD,
-       .wp_gpio        = TRIMSLICE_GPIO_SD4_WP,
-       .power_gpio     = -1,
-};
-
-static struct platform_device trimslice_audio_device = {
-       .name   = "tegra-snd-trimslice",
-       .id     = 0,
-};
-
-static struct platform_device *trimslice_devices[] __initdata = {
-       &debug_uart,
-       &tegra_sdhci_device1,
-       &tegra_sdhci_device4,
-       &tegra_i2s_device1,
-       &tegra_das_device,
-       &trimslice_audio_device,
-};
-
-static struct i2c_board_info trimslice_i2c3_board_info[] = {
-       {
-               I2C_BOARD_INFO("tlv320aic23", 0x1a),
-       },
-       {
-               I2C_BOARD_INFO("em3027", 0x56),
-       },
-};
-
-static void trimslice_i2c_init(void)
-{
-       platform_device_register(&tegra_i2c_device1);
-       platform_device_register(&tegra_i2c_device2);
-       platform_device_register(&tegra_i2c_device3);
-
-       i2c_register_board_info(2, trimslice_i2c3_board_info,
-                               ARRAY_SIZE(trimslice_i2c3_board_info));
-}
-
-static void trimslice_usb_init(void)
-{
-       struct tegra_ehci_platform_data *pdata;
-
-       pdata = tegra_ehci1_device.dev.platform_data;
-       pdata->vbus_gpio = TRIMSLICE_GPIO_USB1_MODE;
-
-       tegra_ehci2_ulpi_phy_config.reset_gpio = TEGRA_GPIO_PV0;
-
-       platform_device_register(&tegra_ehci3_device);
-       platform_device_register(&tegra_ehci2_device);
-       platform_device_register(&tegra_ehci1_device);
-}
-
-static void __init tegra_trimslice_fixup(struct tag *tags, char **cmdline,
-       struct meminfo *mi)
-{
-       mi->nr_banks = 2;
-       mi->bank[0].start = PHYS_OFFSET;
-       mi->bank[0].size = 448 * SZ_1M;
-       mi->bank[1].start = SZ_512M;
-       mi->bank[1].size = SZ_512M;
-}
-
-static __initdata struct tegra_clk_init_table trimslice_clk_init_table[] = {
-       /* name         parent          rate            enabled */
-       { "uarta",      "pll_p",        216000000,      true },
-       { "pll_a",      "pll_p_out1",   56448000,       true },
-       { "pll_a_out0", "pll_a",        11289600,       true },
-       { "cdev1",      NULL,           0,              true },
-       { "i2s1",       "pll_a_out0",   11289600,       false},
-       { NULL,         NULL,           0,              0},
-};
-
-static int __init tegra_trimslice_pci_init(void)
-{
-       if (!machine_is_trimslice())
-               return 0;
-
-       return tegra_pcie_init(true, true);
-}
-subsys_initcall(tegra_trimslice_pci_init);
-
-static void __init tegra_trimslice_init(void)
-{
-       tegra_clk_init_from_table(trimslice_clk_init_table);
-
-       trimslice_pinmux_init();
-
-       tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1;
-       tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
-
-       platform_add_devices(trimslice_devices, ARRAY_SIZE(trimslice_devices));
-
-       trimslice_i2c_init();
-       trimslice_usb_init();
-}
-
-MACHINE_START(TRIMSLICE, "trimslice")
-       .atag_offset    = 0x100,
-       .fixup          = tegra_trimslice_fixup,
-       .map_io         = tegra_map_common_io,
-       .init_early     = tegra20_init_early,
-       .init_irq       = tegra_init_irq,
-       .handle_irq     = gic_handle_irq,
-       .timer          = &tegra_timer,
-       .init_machine   = tegra_trimslice_init,
-       .init_late      = tegra_init_late,
-       .restart        = tegra_assert_system_reset,
-MACHINE_END
diff --git a/arch/arm/mach-tegra/board-trimslice.h b/arch/arm/mach-tegra/board-trimslice.h
deleted file mode 100644 (file)
index 50f128d..0000000
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-trimslice.h
- *
- * Copyright (C) 2011 CompuLab, Ltd.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _MACH_TEGRA_BOARD_TRIMSLICE_H
-#define _MACH_TEGRA_BOARD_TRIMSLICE_H
-
-#include <mach/gpio-tegra.h>
-
-#define TRIMSLICE_GPIO_SD4_CD  TEGRA_GPIO_PP1  /* mmc4 cd */
-#define TRIMSLICE_GPIO_SD4_WP  TEGRA_GPIO_PP2  /* mmc4 wp */
-
-#define TRIMSLICE_GPIO_USB1_MODE       TEGRA_GPIO_PV2 /* USB1 mode */
-#define TRIMSLICE_GPIO_USB2_RST                TEGRA_GPIO_PV0 /* USB2 PHY reset */
-
-void trimslice_pinmux_init(void);
-
-#endif
index d8ab762..63cc280 100644 (file)
@@ -23,7 +23,6 @@
 #include <linux/fsl_devices.h>
 #include <linux/serial_8250.h>
 #include <linux/i2c-tegra.h>
-#include <asm/pmu.h>
 #include <mach/irqs.h>
 #include <mach/iomap.h>
 #include <mach/dma.h>
@@ -516,7 +515,7 @@ static struct resource tegra_pmu_resources[] = {
 
 struct platform_device tegra_pmu_device = {
        .name           = "arm-pmu",
-       .id             = ARM_PMU_DEVICE_CPU,
+       .id             = -1,
        .num_resources  = ARRAY_SIZE(tegra_pmu_resources),
        .resource       = tegra_pmu_resources,
 };
diff --git a/arch/arm/mach-tegra/dma.c b/arch/arm/mach-tegra/dma.c
deleted file mode 100644 (file)
index 29c5114..0000000
+++ /dev/null
@@ -1,823 +0,0 @@
-/*
- * arch/arm/mach-tegra/dma.c
- *
- * System DMA driver for NVIDIA Tegra SoCs
- *
- * Copyright (c) 2008-2009, NVIDIA Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- */
-
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/module.h>
-#include <linux/spinlock.h>
-#include <linux/err.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <mach/dma.h>
-#include <mach/irqs.h>
-#include <mach/iomap.h>
-#include <mach/suspend.h>
-
-#include "apbio.h"
-
-#define APB_DMA_GEN                            0x000
-#define GEN_ENABLE                             (1<<31)
-
-#define APB_DMA_CNTRL                          0x010
-
-#define APB_DMA_IRQ_MASK                       0x01c
-
-#define APB_DMA_IRQ_MASK_SET                   0x020
-
-#define APB_DMA_CHAN_CSR                       0x000
-#define CSR_ENB                                        (1<<31)
-#define CSR_IE_EOC                             (1<<30)
-#define CSR_HOLD                               (1<<29)
-#define CSR_DIR                                        (1<<28)
-#define CSR_ONCE                               (1<<27)
-#define CSR_FLOW                               (1<<21)
-#define CSR_REQ_SEL_SHIFT                      16
-#define CSR_WCOUNT_SHIFT                       2
-#define CSR_WCOUNT_MASK                                0xFFFC
-
-#define APB_DMA_CHAN_STA                               0x004
-#define STA_BUSY                               (1<<31)
-#define STA_ISE_EOC                            (1<<30)
-#define STA_HALT                               (1<<29)
-#define STA_PING_PONG                          (1<<28)
-#define STA_COUNT_SHIFT                                2
-#define STA_COUNT_MASK                         0xFFFC
-
-#define APB_DMA_CHAN_AHB_PTR                           0x010
-
-#define APB_DMA_CHAN_AHB_SEQ                           0x014
-#define AHB_SEQ_INTR_ENB                       (1<<31)
-#define AHB_SEQ_BUS_WIDTH_SHIFT                        28
-#define AHB_SEQ_BUS_WIDTH_MASK                 (0x7<<AHB_SEQ_BUS_WIDTH_SHIFT)
-#define AHB_SEQ_BUS_WIDTH_8                    (0<<AHB_SEQ_BUS_WIDTH_SHIFT)
-#define AHB_SEQ_BUS_WIDTH_16                   (1<<AHB_SEQ_BUS_WIDTH_SHIFT)
-#define AHB_SEQ_BUS_WIDTH_32                   (2<<AHB_SEQ_BUS_WIDTH_SHIFT)
-#define AHB_SEQ_BUS_WIDTH_64                   (3<<AHB_SEQ_BUS_WIDTH_SHIFT)
-#define AHB_SEQ_BUS_WIDTH_128                  (4<<AHB_SEQ_BUS_WIDTH_SHIFT)
-#define AHB_SEQ_DATA_SWAP                      (1<<27)
-#define AHB_SEQ_BURST_MASK                     (0x7<<24)
-#define AHB_SEQ_BURST_1                                (4<<24)
-#define AHB_SEQ_BURST_4                                (5<<24)
-#define AHB_SEQ_BURST_8                                (6<<24)
-#define AHB_SEQ_DBL_BUF                                (1<<19)
-#define AHB_SEQ_WRAP_SHIFT                     16
-#define AHB_SEQ_WRAP_MASK                      (0x7<<AHB_SEQ_WRAP_SHIFT)
-
-#define APB_DMA_CHAN_APB_PTR                           0x018
-
-#define APB_DMA_CHAN_APB_SEQ                           0x01c
-#define APB_SEQ_BUS_WIDTH_SHIFT                        28
-#define APB_SEQ_BUS_WIDTH_MASK                 (0x7<<APB_SEQ_BUS_WIDTH_SHIFT)
-#define APB_SEQ_BUS_WIDTH_8                    (0<<APB_SEQ_BUS_WIDTH_SHIFT)
-#define APB_SEQ_BUS_WIDTH_16                   (1<<APB_SEQ_BUS_WIDTH_SHIFT)
-#define APB_SEQ_BUS_WIDTH_32                   (2<<APB_SEQ_BUS_WIDTH_SHIFT)
-#define APB_SEQ_BUS_WIDTH_64                   (3<<APB_SEQ_BUS_WIDTH_SHIFT)
-#define APB_SEQ_BUS_WIDTH_128                  (4<<APB_SEQ_BUS_WIDTH_SHIFT)
-#define APB_SEQ_DATA_SWAP                      (1<<27)
-#define APB_SEQ_WRAP_SHIFT                     16
-#define APB_SEQ_WRAP_MASK                      (0x7<<APB_SEQ_WRAP_SHIFT)
-
-#define TEGRA_SYSTEM_DMA_CH_NR                 16
-#define TEGRA_SYSTEM_DMA_AVP_CH_NUM            4
-#define TEGRA_SYSTEM_DMA_CH_MIN                        0
-#define TEGRA_SYSTEM_DMA_CH_MAX        \
-       (TEGRA_SYSTEM_DMA_CH_NR - TEGRA_SYSTEM_DMA_AVP_CH_NUM - 1)
-
-#define NV_DMA_MAX_TRASFER_SIZE 0x10000
-
-static const unsigned int ahb_addr_wrap_table[8] = {
-       0, 32, 64, 128, 256, 512, 1024, 2048
-};
-
-static const unsigned int apb_addr_wrap_table[8] = {
-       0, 1, 2, 4, 8, 16, 32, 64
-};
-
-static const unsigned int bus_width_table[5] = {
-       8, 16, 32, 64, 128
-};
-
-#define TEGRA_DMA_NAME_SIZE 16
-struct tegra_dma_channel {
-       struct list_head        list;
-       int                     id;
-       spinlock_t              lock;
-       char                    name[TEGRA_DMA_NAME_SIZE];
-       void  __iomem           *addr;
-       int                     mode;
-       int                     irq;
-       int                     req_transfer_count;
-};
-
-#define  NV_DMA_MAX_CHANNELS  32
-
-static bool tegra_dma_initialized;
-static DEFINE_MUTEX(tegra_dma_lock);
-static DEFINE_SPINLOCK(enable_lock);
-
-static DECLARE_BITMAP(channel_usage, NV_DMA_MAX_CHANNELS);
-static struct tegra_dma_channel dma_channels[NV_DMA_MAX_CHANNELS];
-
-static void tegra_dma_update_hw(struct tegra_dma_channel *ch,
-       struct tegra_dma_req *req);
-static void tegra_dma_update_hw_partial(struct tegra_dma_channel *ch,
-       struct tegra_dma_req *req);
-static void tegra_dma_stop(struct tegra_dma_channel *ch);
-
-void tegra_dma_flush(struct tegra_dma_channel *ch)
-{
-}
-EXPORT_SYMBOL(tegra_dma_flush);
-
-void tegra_dma_dequeue(struct tegra_dma_channel *ch)
-{
-       struct tegra_dma_req *req;
-
-       if (tegra_dma_is_empty(ch))
-               return;
-
-       req = list_entry(ch->list.next, typeof(*req), node);
-
-       tegra_dma_dequeue_req(ch, req);
-       return;
-}
-
-static void tegra_dma_stop(struct tegra_dma_channel *ch)
-{
-       u32 csr;
-       u32 status;
-
-       csr = readl(ch->addr + APB_DMA_CHAN_CSR);
-       csr &= ~CSR_IE_EOC;
-       writel(csr, ch->addr + APB_DMA_CHAN_CSR);
-
-       csr &= ~CSR_ENB;
-       writel(csr, ch->addr + APB_DMA_CHAN_CSR);
-
-       status = readl(ch->addr + APB_DMA_CHAN_STA);
-       if (status & STA_ISE_EOC)
-               writel(status, ch->addr + APB_DMA_CHAN_STA);
-}
-
-static int tegra_dma_cancel(struct tegra_dma_channel *ch)
-{
-       unsigned long irq_flags;
-
-       spin_lock_irqsave(&ch->lock, irq_flags);
-       while (!list_empty(&ch->list))
-               list_del(ch->list.next);
-
-       tegra_dma_stop(ch);
-
-       spin_unlock_irqrestore(&ch->lock, irq_flags);
-       return 0;
-}
-
-static unsigned int get_channel_status(struct tegra_dma_channel *ch,
-                       struct tegra_dma_req *req, bool is_stop_dma)
-{
-       void __iomem *addr = IO_ADDRESS(TEGRA_APB_DMA_BASE);
-       unsigned int status;
-
-       if (is_stop_dma) {
-               /*
-                * STOP the DMA and get the transfer count.
-                * Getting the transfer count is tricky.
-                *  - Globally disable DMA on all channels
-                *  - Read the channel's status register to know the number
-                *    of pending bytes to be transfered.
-                *  - Stop the dma channel
-                *  - Globally re-enable DMA to resume other transfers
-                */
-               spin_lock(&enable_lock);
-               writel(0, addr + APB_DMA_GEN);
-               udelay(20);
-               status = readl(ch->addr + APB_DMA_CHAN_STA);
-               tegra_dma_stop(ch);
-               writel(GEN_ENABLE, addr + APB_DMA_GEN);
-               spin_unlock(&enable_lock);
-               if (status & STA_ISE_EOC) {
-                       pr_err("Got Dma Int here clearing");
-                       writel(status, ch->addr + APB_DMA_CHAN_STA);
-               }
-               req->status = TEGRA_DMA_REQ_ERROR_ABORTED;
-       } else {
-               status = readl(ch->addr + APB_DMA_CHAN_STA);
-       }
-       return status;
-}
-
-/* should be called with the channel lock held */
-static unsigned int dma_active_count(struct tegra_dma_channel *ch,
-       struct tegra_dma_req *req, unsigned int status)
-{
-       unsigned int to_transfer;
-       unsigned int req_transfer_count;
-       unsigned int bytes_transferred;
-
-       to_transfer = ((status & STA_COUNT_MASK) >> STA_COUNT_SHIFT) + 1;
-       req_transfer_count = ch->req_transfer_count + 1;
-       bytes_transferred = req_transfer_count;
-       if (status & STA_BUSY)
-               bytes_transferred -= to_transfer;
-       /*
-        * In continuous transfer mode, DMA only tracks the count of the
-        * half DMA buffer. So, if the DMA already finished half the DMA
-        * then add the half buffer to the completed count.
-        */
-       if (ch->mode & TEGRA_DMA_MODE_CONTINOUS) {
-               if (req->buffer_status == TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL)
-                       bytes_transferred += req_transfer_count;
-               if (status & STA_ISE_EOC)
-                       bytes_transferred += req_transfer_count;
-       }
-       bytes_transferred *= 4;
-       return bytes_transferred;
-}
-
-int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
-       struct tegra_dma_req *_req)
-{
-       unsigned int status;
-       struct tegra_dma_req *req = NULL;
-       int found = 0;
-       unsigned long irq_flags;
-       int stop = 0;
-
-       spin_lock_irqsave(&ch->lock, irq_flags);
-
-       if (list_entry(ch->list.next, struct tegra_dma_req, node) == _req)
-               stop = 1;
-
-       list_for_each_entry(req, &ch->list, node) {
-               if (req == _req) {
-                       list_del(&req->node);
-                       found = 1;
-                       break;
-               }
-       }
-       if (!found) {
-               spin_unlock_irqrestore(&ch->lock, irq_flags);
-               return 0;
-       }
-
-       if (!stop)
-               goto skip_stop_dma;
-
-       status = get_channel_status(ch, req, true);
-       req->bytes_transferred = dma_active_count(ch, req, status);
-
-       if (!list_empty(&ch->list)) {
-               /* if the list is not empty, queue the next request */
-               struct tegra_dma_req *next_req;
-               next_req = list_entry(ch->list.next,
-                       typeof(*next_req), node);
-               tegra_dma_update_hw(ch, next_req);
-       }
-
-skip_stop_dma:
-       req->status = -TEGRA_DMA_REQ_ERROR_ABORTED;
-
-       spin_unlock_irqrestore(&ch->lock, irq_flags);
-
-       /* Callback should be called without any lock */
-       req->complete(req);
-       return 0;
-}
-EXPORT_SYMBOL(tegra_dma_dequeue_req);
-
-bool tegra_dma_is_empty(struct tegra_dma_channel *ch)
-{
-       unsigned long irq_flags;
-       bool is_empty;
-
-       spin_lock_irqsave(&ch->lock, irq_flags);
-       if (list_empty(&ch->list))
-               is_empty = true;
-       else
-               is_empty = false;
-       spin_unlock_irqrestore(&ch->lock, irq_flags);
-       return is_empty;
-}
-EXPORT_SYMBOL(tegra_dma_is_empty);
-
-bool tegra_dma_is_req_inflight(struct tegra_dma_channel *ch,
-       struct tegra_dma_req *_req)
-{
-       unsigned long irq_flags;
-       struct tegra_dma_req *req;
-
-       spin_lock_irqsave(&ch->lock, irq_flags);
-       list_for_each_entry(req, &ch->list, node) {
-               if (req == _req) {
-                       spin_unlock_irqrestore(&ch->lock, irq_flags);
-                       return true;
-               }
-       }
-       spin_unlock_irqrestore(&ch->lock, irq_flags);
-       return false;
-}
-EXPORT_SYMBOL(tegra_dma_is_req_inflight);
-
-int tegra_dma_enqueue_req(struct tegra_dma_channel *ch,
-       struct tegra_dma_req *req)
-{
-       unsigned long irq_flags;
-       struct tegra_dma_req *_req;
-       int start_dma = 0;
-
-       if (req->size > NV_DMA_MAX_TRASFER_SIZE ||
-               req->source_addr & 0x3 || req->dest_addr & 0x3) {
-               pr_err("Invalid DMA request for channel %d\n", ch->id);
-               return -EINVAL;
-       }
-
-       spin_lock_irqsave(&ch->lock, irq_flags);
-
-       list_for_each_entry(_req, &ch->list, node) {
-               if (req == _req) {
-                   spin_unlock_irqrestore(&ch->lock, irq_flags);
-                   return -EEXIST;
-               }
-       }
-
-       req->bytes_transferred = 0;
-       req->status = 0;
-       req->buffer_status = 0;
-       if (list_empty(&ch->list))
-               start_dma = 1;
-
-       list_add_tail(&req->node, &ch->list);
-
-       if (start_dma)
-               tegra_dma_update_hw(ch, req);
-
-       spin_unlock_irqrestore(&ch->lock, irq_flags);
-
-       return 0;
-}
-EXPORT_SYMBOL(tegra_dma_enqueue_req);
-
-struct tegra_dma_channel *tegra_dma_allocate_channel(int mode)
-{
-       int channel;
-       struct tegra_dma_channel *ch = NULL;
-
-       if (!tegra_dma_initialized)
-               return NULL;
-
-       mutex_lock(&tegra_dma_lock);
-
-       /* first channel is the shared channel */
-       if (mode & TEGRA_DMA_SHARED) {
-               channel = TEGRA_SYSTEM_DMA_CH_MIN;
-       } else {
-               channel = find_first_zero_bit(channel_usage,
-                       ARRAY_SIZE(dma_channels));
-               if (channel >= ARRAY_SIZE(dma_channels))
-                       goto out;
-       }
-       __set_bit(channel, channel_usage);
-       ch = &dma_channels[channel];
-       ch->mode = mode;
-
-out:
-       mutex_unlock(&tegra_dma_lock);
-       return ch;
-}
-EXPORT_SYMBOL(tegra_dma_allocate_channel);
-
-void tegra_dma_free_channel(struct tegra_dma_channel *ch)
-{
-       if (ch->mode & TEGRA_DMA_SHARED)
-               return;
-       tegra_dma_cancel(ch);
-       mutex_lock(&tegra_dma_lock);
-       __clear_bit(ch->id, channel_usage);
-       mutex_unlock(&tegra_dma_lock);
-}
-EXPORT_SYMBOL(tegra_dma_free_channel);
-
-static void tegra_dma_update_hw_partial(struct tegra_dma_channel *ch,
-       struct tegra_dma_req *req)
-{
-       u32 apb_ptr;
-       u32 ahb_ptr;
-
-       if (req->to_memory) {
-               apb_ptr = req->source_addr;
-               ahb_ptr = req->dest_addr;
-       } else {
-               apb_ptr = req->dest_addr;
-               ahb_ptr = req->source_addr;
-       }
-       writel(apb_ptr, ch->addr + APB_DMA_CHAN_APB_PTR);
-       writel(ahb_ptr, ch->addr + APB_DMA_CHAN_AHB_PTR);
-
-       req->status = TEGRA_DMA_REQ_INFLIGHT;
-       return;
-}
-
-static void tegra_dma_update_hw(struct tegra_dma_channel *ch,
-       struct tegra_dma_req *req)
-{
-       int ahb_addr_wrap;
-       int apb_addr_wrap;
-       int ahb_bus_width;
-       int apb_bus_width;
-       int index;
-
-       u32 ahb_seq;
-       u32 apb_seq;
-       u32 ahb_ptr;
-       u32 apb_ptr;
-       u32 csr;
-
-       csr = CSR_IE_EOC | CSR_FLOW;
-       ahb_seq = AHB_SEQ_INTR_ENB | AHB_SEQ_BURST_1;
-       apb_seq = 0;
-
-       csr |= req->req_sel << CSR_REQ_SEL_SHIFT;
-
-       /* One shot mode is always single buffered,
-        * continuous mode is always double buffered
-        * */
-       if (ch->mode & TEGRA_DMA_MODE_ONESHOT) {
-               csr |= CSR_ONCE;
-               ch->req_transfer_count = (req->size >> 2) - 1;
-       } else {
-               ahb_seq |= AHB_SEQ_DBL_BUF;
-
-               /* In double buffered mode, we set the size to half the
-                * requested size and interrupt when half the buffer
-                * is full */
-               ch->req_transfer_count = (req->size >> 3) - 1;
-       }
-
-       csr |= ch->req_transfer_count << CSR_WCOUNT_SHIFT;
-
-       if (req->to_memory) {
-               apb_ptr = req->source_addr;
-               ahb_ptr = req->dest_addr;
-
-               apb_addr_wrap = req->source_wrap;
-               ahb_addr_wrap = req->dest_wrap;
-               apb_bus_width = req->source_bus_width;
-               ahb_bus_width = req->dest_bus_width;
-
-       } else {
-               csr |= CSR_DIR;
-               apb_ptr = req->dest_addr;
-               ahb_ptr = req->source_addr;
-
-               apb_addr_wrap = req->dest_wrap;
-               ahb_addr_wrap = req->source_wrap;
-               apb_bus_width = req->dest_bus_width;
-               ahb_bus_width = req->source_bus_width;
-       }
-
-       apb_addr_wrap >>= 2;
-       ahb_addr_wrap >>= 2;
-
-       /* set address wrap for APB size */
-       index = 0;
-       do  {
-               if (apb_addr_wrap_table[index] == apb_addr_wrap)
-                       break;
-               index++;
-       } while (index < ARRAY_SIZE(apb_addr_wrap_table));
-       BUG_ON(index == ARRAY_SIZE(apb_addr_wrap_table));
-       apb_seq |= index << APB_SEQ_WRAP_SHIFT;
-
-       /* set address wrap for AHB size */
-       index = 0;
-       do  {
-               if (ahb_addr_wrap_table[index] == ahb_addr_wrap)
-                       break;
-               index++;
-       } while (index < ARRAY_SIZE(ahb_addr_wrap_table));
-       BUG_ON(index == ARRAY_SIZE(ahb_addr_wrap_table));
-       ahb_seq |= index << AHB_SEQ_WRAP_SHIFT;
-
-       for (index = 0; index < ARRAY_SIZE(bus_width_table); index++) {
-               if (bus_width_table[index] == ahb_bus_width)
-                       break;
-       }
-       BUG_ON(index == ARRAY_SIZE(bus_width_table));
-       ahb_seq |= index << AHB_SEQ_BUS_WIDTH_SHIFT;
-
-       for (index = 0; index < ARRAY_SIZE(bus_width_table); index++) {
-               if (bus_width_table[index] == apb_bus_width)
-                       break;
-       }
-       BUG_ON(index == ARRAY_SIZE(bus_width_table));
-       apb_seq |= index << APB_SEQ_BUS_WIDTH_SHIFT;
-
-       writel(csr, ch->addr + APB_DMA_CHAN_CSR);
-       writel(apb_seq, ch->addr + APB_DMA_CHAN_APB_SEQ);
-       writel(apb_ptr, ch->addr + APB_DMA_CHAN_APB_PTR);
-       writel(ahb_seq, ch->addr + APB_DMA_CHAN_AHB_SEQ);
-       writel(ahb_ptr, ch->addr + APB_DMA_CHAN_AHB_PTR);
-
-       csr |= CSR_ENB;
-       writel(csr, ch->addr + APB_DMA_CHAN_CSR);
-
-       req->status = TEGRA_DMA_REQ_INFLIGHT;
-}
-
-static void handle_oneshot_dma(struct tegra_dma_channel *ch)
-{
-       struct tegra_dma_req *req;
-       unsigned long irq_flags;
-
-       spin_lock_irqsave(&ch->lock, irq_flags);
-       if (list_empty(&ch->list)) {
-               spin_unlock_irqrestore(&ch->lock, irq_flags);
-               return;
-       }
-
-       req = list_entry(ch->list.next, typeof(*req), node);
-       if (req) {
-               int bytes_transferred;
-
-               bytes_transferred = ch->req_transfer_count;
-               bytes_transferred += 1;
-               bytes_transferred <<= 2;
-
-               list_del(&req->node);
-               req->bytes_transferred = bytes_transferred;
-               req->status = TEGRA_DMA_REQ_SUCCESS;
-
-               spin_unlock_irqrestore(&ch->lock, irq_flags);
-               /* Callback should be called without any lock */
-               pr_debug("%s: transferred %d bytes\n", __func__,
-                       req->bytes_transferred);
-               req->complete(req);
-               spin_lock_irqsave(&ch->lock, irq_flags);
-       }
-
-       if (!list_empty(&ch->list)) {
-               req = list_entry(ch->list.next, typeof(*req), node);
-               /* the complete function we just called may have enqueued
-                  another req, in which case dma has already started */
-               if (req->status != TEGRA_DMA_REQ_INFLIGHT)
-                       tegra_dma_update_hw(ch, req);
-       }
-       spin_unlock_irqrestore(&ch->lock, irq_flags);
-}
-
-static void handle_continuous_dma(struct tegra_dma_channel *ch)
-{
-       struct tegra_dma_req *req;
-       unsigned long irq_flags;
-
-       spin_lock_irqsave(&ch->lock, irq_flags);
-       if (list_empty(&ch->list)) {
-               spin_unlock_irqrestore(&ch->lock, irq_flags);
-               return;
-       }
-
-       req = list_entry(ch->list.next, typeof(*req), node);
-       if (req) {
-               if (req->buffer_status == TEGRA_DMA_REQ_BUF_STATUS_EMPTY) {
-                       bool is_dma_ping_complete;
-                       is_dma_ping_complete = (readl(ch->addr + APB_DMA_CHAN_STA)
-                                               & STA_PING_PONG) ? true : false;
-                       if (req->to_memory)
-                               is_dma_ping_complete = !is_dma_ping_complete;
-                       /* Out of sync - Release current buffer */
-                       if (!is_dma_ping_complete) {
-                               int bytes_transferred;
-
-                               bytes_transferred = ch->req_transfer_count;
-                               bytes_transferred += 1;
-                               bytes_transferred <<= 3;
-                               req->buffer_status = TEGRA_DMA_REQ_BUF_STATUS_FULL;
-                               req->bytes_transferred = bytes_transferred;
-                               req->status = TEGRA_DMA_REQ_SUCCESS;
-                               tegra_dma_stop(ch);
-
-                               if (!list_is_last(&req->node, &ch->list)) {
-                                       struct tegra_dma_req *next_req;
-
-                                       next_req = list_entry(req->node.next,
-                                               typeof(*next_req), node);
-                                       tegra_dma_update_hw(ch, next_req);
-                               }
-
-                               list_del(&req->node);
-
-                               /* DMA lock is NOT held when callbak is called */
-                               spin_unlock_irqrestore(&ch->lock, irq_flags);
-                               req->complete(req);
-                               return;
-                       }
-                       /* Load the next request into the hardware, if available
-                        * */
-                       if (!list_is_last(&req->node, &ch->list)) {
-                               struct tegra_dma_req *next_req;
-
-                               next_req = list_entry(req->node.next,
-                                       typeof(*next_req), node);
-                               tegra_dma_update_hw_partial(ch, next_req);
-                       }
-                       req->buffer_status = TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL;
-                       req->status = TEGRA_DMA_REQ_SUCCESS;
-                       /* DMA lock is NOT held when callback is called */
-                       spin_unlock_irqrestore(&ch->lock, irq_flags);
-                       if (likely(req->threshold))
-                               req->threshold(req);
-                       return;
-
-               } else if (req->buffer_status ==
-                       TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL) {
-                       /* Callback when the buffer is completely full (i.e on
-                        * the second  interrupt */
-                       int bytes_transferred;
-
-                       bytes_transferred = ch->req_transfer_count;
-                       bytes_transferred += 1;
-                       bytes_transferred <<= 3;
-
-                       req->buffer_status = TEGRA_DMA_REQ_BUF_STATUS_FULL;
-                       req->bytes_transferred = bytes_transferred;
-                       req->status = TEGRA_DMA_REQ_SUCCESS;
-                       list_del(&req->node);
-
-                       /* DMA lock is NOT held when callbak is called */
-                       spin_unlock_irqrestore(&ch->lock, irq_flags);
-                       req->complete(req);
-                       return;
-
-               } else {
-                       BUG();
-               }
-       }
-       spin_unlock_irqrestore(&ch->lock, irq_flags);
-}
-
-static irqreturn_t dma_isr(int irq, void *data)
-{
-       struct tegra_dma_channel *ch = data;
-       unsigned long status;
-
-       status = readl(ch->addr + APB_DMA_CHAN_STA);
-       if (status & STA_ISE_EOC)
-               writel(status, ch->addr + APB_DMA_CHAN_STA);
-       else {
-               pr_warning("Got a spurious ISR for DMA channel %d\n", ch->id);
-               return IRQ_HANDLED;
-       }
-       return IRQ_WAKE_THREAD;
-}
-
-static irqreturn_t dma_thread_fn(int irq, void *data)
-{
-       struct tegra_dma_channel *ch = data;
-
-       if (ch->mode & TEGRA_DMA_MODE_ONESHOT)
-               handle_oneshot_dma(ch);
-       else
-               handle_continuous_dma(ch);
-
-
-       return IRQ_HANDLED;
-}
-
-int __init tegra_dma_init(void)
-{
-       int ret = 0;
-       int i;
-       unsigned int irq;
-       void __iomem *addr;
-       struct clk *c;
-
-       bitmap_fill(channel_usage, NV_DMA_MAX_CHANNELS);
-
-       c = clk_get_sys("tegra-apbdma", NULL);
-       if (IS_ERR(c)) {
-               pr_err("Unable to get clock for APB DMA\n");
-               ret = PTR_ERR(c);
-               goto fail;
-       }
-       ret = clk_prepare_enable(c);
-       if (ret != 0) {
-               pr_err("Unable to enable clock for APB DMA\n");
-               goto fail;
-       }
-
-       addr = IO_ADDRESS(TEGRA_APB_DMA_BASE);
-       writel(GEN_ENABLE, addr + APB_DMA_GEN);
-       writel(0, addr + APB_DMA_CNTRL);
-       writel(0xFFFFFFFFul >> (31 - TEGRA_SYSTEM_DMA_CH_MAX),
-              addr + APB_DMA_IRQ_MASK_SET);
-
-       for (i = TEGRA_SYSTEM_DMA_CH_MIN; i <= TEGRA_SYSTEM_DMA_CH_MAX; i++) {
-               struct tegra_dma_channel *ch = &dma_channels[i];
-
-               ch->id = i;
-               snprintf(ch->name, TEGRA_DMA_NAME_SIZE, "dma_channel_%d", i);
-
-               ch->addr = IO_ADDRESS(TEGRA_APB_DMA_CH0_BASE +
-                       TEGRA_APB_DMA_CH0_SIZE * i);
-
-               spin_lock_init(&ch->lock);
-               INIT_LIST_HEAD(&ch->list);
-
-               irq = INT_APB_DMA_CH0 + i;
-               ret = request_threaded_irq(irq, dma_isr, dma_thread_fn, 0,
-                       dma_channels[i].name, ch);
-               if (ret) {
-                       pr_err("Failed to register IRQ %d for DMA %d\n",
-                               irq, i);
-                       goto fail;
-               }
-               ch->irq = irq;
-
-               __clear_bit(i, channel_usage);
-       }
-       /* mark the shared channel allocated */
-       __set_bit(TEGRA_SYSTEM_DMA_CH_MIN, channel_usage);
-
-       tegra_dma_initialized = true;
-
-       return 0;
-fail:
-       writel(0, addr + APB_DMA_GEN);
-       for (i = TEGRA_SYSTEM_DMA_CH_MIN; i <= TEGRA_SYSTEM_DMA_CH_MAX; i++) {
-               struct tegra_dma_channel *ch = &dma_channels[i];
-               if (ch->irq)
-                       free_irq(ch->irq, ch);
-       }
-       return ret;
-}
-postcore_initcall(tegra_dma_init);
-
-#ifdef CONFIG_PM
-static u32 apb_dma[5*TEGRA_SYSTEM_DMA_CH_NR + 3];
-
-void tegra_dma_suspend(void)
-{
-       void __iomem *addr = IO_ADDRESS(TEGRA_APB_DMA_BASE);
-       u32 *ctx = apb_dma;
-       int i;
-
-       *ctx++ = readl(addr + APB_DMA_GEN);
-       *ctx++ = readl(addr + APB_DMA_CNTRL);
-       *ctx++ = readl(addr + APB_DMA_IRQ_MASK);
-
-       for (i = 0; i < TEGRA_SYSTEM_DMA_CH_NR; i++) {
-               addr = IO_ADDRESS(TEGRA_APB_DMA_CH0_BASE +
-                                 TEGRA_APB_DMA_CH0_SIZE * i);
-
-               *ctx++ = readl(addr + APB_DMA_CHAN_CSR);
-               *ctx++ = readl(addr + APB_DMA_CHAN_AHB_PTR);
-               *ctx++ = readl(addr + APB_DMA_CHAN_AHB_SEQ);
-               *ctx++ = readl(addr + APB_DMA_CHAN_APB_PTR);
-               *ctx++ = readl(addr + APB_DMA_CHAN_APB_SEQ);
-       }
-}
-
-void tegra_dma_resume(void)
-{
-       void __iomem *addr = IO_ADDRESS(TEGRA_APB_DMA_BASE);
-       u32 *ctx = apb_dma;
-       int i;
-
-       writel(*ctx++, addr + APB_DMA_GEN);
-       writel(*ctx++, addr + APB_DMA_CNTRL);
-       writel(*ctx++, addr + APB_DMA_IRQ_MASK);
-
-       for (i = 0; i < TEGRA_SYSTEM_DMA_CH_NR; i++) {
-               addr = IO_ADDRESS(TEGRA_APB_DMA_CH0_BASE +
-                                 TEGRA_APB_DMA_CH0_SIZE * i);
-
-               writel(*ctx++, addr + APB_DMA_CHAN_CSR);
-               writel(*ctx++, addr + APB_DMA_CHAN_AHB_PTR);
-               writel(*ctx++, addr + APB_DMA_CHAN_AHB_SEQ);
-               writel(*ctx++, addr + APB_DMA_CHAN_APB_PTR);
-               writel(*ctx++, addr + APB_DMA_CHAN_APB_SEQ);
-       }
-}
-
-#endif
index f946d12..0b7db17 100644 (file)
@@ -93,9 +93,9 @@ void tegra_init_fuse(void)
 {
        u32 id;
 
-       u32 reg = readl(IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
+       u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
        reg |= 1 << 28;
-       writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
+       writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
 
        reg = tegra_fuse_readl(FUSE_SKU_INFO);
        tegra_sku_id = reg & 0xFF;
index 9077092..3081cc6 100644 (file)
 #define TEGRA_DMA_REQ_SEL_OWR                  25
 #define TEGRA_DMA_REQ_SEL_INVALID              31
 
-struct tegra_dma_req;
-struct tegra_dma_channel;
-
-enum tegra_dma_mode {
-       TEGRA_DMA_SHARED = 1,
-       TEGRA_DMA_MODE_CONTINOUS = 2,
-       TEGRA_DMA_MODE_ONESHOT = 4,
-};
-
-enum tegra_dma_req_error {
-       TEGRA_DMA_REQ_SUCCESS = 0,
-       TEGRA_DMA_REQ_ERROR_ABORTED,
-       TEGRA_DMA_REQ_INFLIGHT,
-};
-
-enum tegra_dma_req_buff_status {
-       TEGRA_DMA_REQ_BUF_STATUS_EMPTY = 0,
-       TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL,
-       TEGRA_DMA_REQ_BUF_STATUS_FULL,
-};
-
-struct tegra_dma_req {
-       struct list_head node;
-       unsigned int modid;
-       int instance;
-
-       /* Called when the req is complete and from the DMA ISR context.
-        * When this is called the req structure is no longer queued by
-        * the DMA channel.
-        *
-        * State of the DMA depends on the number of req it has. If there are
-        * no DMA requests queued up, then it will STOP the DMA. It there are
-        * more requests in the DMA, then it will queue the next request.
-        */
-       void (*complete)(struct tegra_dma_req *req);
-
-       /*  This is a called from the DMA ISR context when the DMA is still in
-        *  progress and is actively filling same buffer.
-        *
-        *  In case of continuous mode receive, this threshold is 1/2 the buffer
-        *  size. In other cases, this will not even be called as there is no
-        *  hardware support for it.
-        *
-        * In the case of continuous mode receive, if there is next req already
-        * queued, DMA programs the HW to use that req when this req is
-        * completed. If there is no "next req" queued, then DMA ISR doesn't do
-        * anything before calling this callback.
-        *
-        *      This is mainly used by the cases, where the clients has queued
-        *      only one req and want to get some sort of DMA threshold
-        *      callback to program the next buffer.
-        *
-        */
-       void (*threshold)(struct tegra_dma_req *req);
-
-       /* 1 to copy to memory.
-        * 0 to copy from the memory to device FIFO */
-       int to_memory;
-
-       void *virt_addr;
-
-       unsigned long source_addr;
-       unsigned long dest_addr;
-       unsigned long dest_wrap;
-       unsigned long source_wrap;
-       unsigned long source_bus_width;
-       unsigned long dest_bus_width;
-       unsigned long req_sel;
-       unsigned int size;
-
-       /* Updated by the DMA driver on the conpletion of the request. */
-       int bytes_transferred;
-       int status;
-
-       /* DMA completion tracking information */
-       int buffer_status;
-
-       /* Client specific data */
-       void *dev;
-};
-
-int tegra_dma_enqueue_req(struct tegra_dma_channel *ch,
-       struct tegra_dma_req *req);
-int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
-       struct tegra_dma_req *req);
-void tegra_dma_dequeue(struct tegra_dma_channel *ch);
-void tegra_dma_flush(struct tegra_dma_channel *ch);
-
-bool tegra_dma_is_req_inflight(struct tegra_dma_channel *ch,
-       struct tegra_dma_req *req);
-bool tegra_dma_is_empty(struct tegra_dma_channel *ch);
-
-struct tegra_dma_channel *tegra_dma_allocate_channel(int mode);
-void tegra_dma_free_channel(struct tegra_dma_channel *ch);
-
-int __init tegra_dma_init(void);
-
 #endif
diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h
deleted file mode 100644 (file)
index fe700f9..0000000
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/io.h
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * Author:
- *     Colin Cross <ccross@google.com>
- *     Erik Gilling <konkers@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_TEGRA_IO_H
-#define __MACH_TEGRA_IO_H
-
-#define IO_SPACE_LIMIT 0xffff
-
-#ifndef __ASSEMBLER__
-
-#ifdef CONFIG_TEGRA_PCI
-extern void __iomem *tegra_pcie_io_base;
-
-static inline void __iomem *__io(unsigned long addr)
-{
-       return tegra_pcie_io_base + (addr & IO_SPACE_LIMIT);
-}
-#else
-static inline void __iomem *__io(unsigned long addr)
-{
-       return (void __iomem *)addr;
-}
-#endif
-
-#define __io(a)         __io(a)
-
-#endif
-
-#endif
index 7e76da7..fee3a94 100644 (file)
 #define IO_APB_VIRT    IOMEM(0xFE300000)
 #define IO_APB_SIZE    SZ_1M
 
+#define TEGRA_PCIE_BASE                0x80000000
+#define TEGRA_PCIE_IO_BASE     (TEGRA_PCIE_BASE + SZ_4M)
+
 #define IO_TO_VIRT_BETWEEN(p, st, sz)  ((p) >= (st) && (p) < ((st) + (sz)))
 #define IO_TO_VIRT_XLATE(p, pst, vst)  (((p) - (pst) + (vst)))
 
index c25a2a4..a8dba64 100644 (file)
@@ -171,8 +171,6 @@ static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
  * 0x90000000 - 0x9fffffff - non-prefetchable memory
  * 0xa0000000 - 0xbfffffff - prefetchable memory
  */
-#define TEGRA_PCIE_BASE                0x80000000
-
 #define PCIE_REGS_SZ           SZ_16K
 #define PCIE_CFG_OFF           PCIE_REGS_SZ
 #define PCIE_CFG_SZ            SZ_1M
@@ -180,8 +178,6 @@ static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
 #define PCIE_EXT_CFG_SZ                SZ_1M
 #define PCIE_IOMAP_SZ          (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ)
 
-#define MMIO_BASE              (TEGRA_PCIE_BASE + SZ_4M)
-#define MMIO_SIZE              SZ_64K
 #define MEM_BASE_0             (TEGRA_PCIE_BASE + SZ_256M)
 #define MEM_SIZE_0             SZ_128M
 #define MEM_BASE_1             (MEM_BASE_0 + MEM_SIZE_0)
@@ -204,10 +200,9 @@ struct tegra_pcie_port {
 
        bool                    link_up;
 
-       char                    io_space_name[16];
        char                    mem_space_name[16];
        char                    prefetch_space_name[20];
-       struct resource         res[3];
+       struct resource         res[2];
 };
 
 struct tegra_pcie_info {
@@ -223,17 +218,7 @@ struct tegra_pcie_info {
        struct clk              *pll_e;
 };
 
-static struct tegra_pcie_info tegra_pcie = {
-       .res_mmio = {
-               .name = "PCI IO",
-               .start = MMIO_BASE,
-               .end = MMIO_BASE + MMIO_SIZE - 1,
-               .flags = IORESOURCE_MEM,
-       },
-};
-
-void __iomem *tegra_pcie_io_base;
-EXPORT_SYMBOL(tegra_pcie_io_base);
+static struct tegra_pcie_info tegra_pcie;
 
 static inline void afi_writel(u32 value, unsigned long offset)
 {
@@ -381,24 +366,7 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
        pp = tegra_pcie.port + nr;
        pp->root_bus_nr = sys->busnr;
 
-       /*
-        * IORESOURCE_IO
-        */
-       snprintf(pp->io_space_name, sizeof(pp->io_space_name),
-                "PCIe %d I/O", pp->index);
-       pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
-       pp->res[0].name = pp->io_space_name;
-       if (pp->index == 0) {
-               pp->res[0].start = PCIBIOS_MIN_IO;
-               pp->res[0].end = pp->res[0].start + SZ_32K - 1;
-       } else {
-               pp->res[0].start = PCIBIOS_MIN_IO + SZ_32K;
-               pp->res[0].end = IO_SPACE_LIMIT;
-       }
-       pp->res[0].flags = IORESOURCE_IO;
-       if (request_resource(&ioport_resource, &pp->res[0]))
-               panic("Request PCIe IO resource failed\n");
-       pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
+       pci_ioremap_io(nr * SZ_64K, TEGRA_PCIE_IO_BASE);
 
        /*
         * IORESOURCE_MEM
@@ -406,18 +374,18 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
        snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
                 "PCIe %d MEM", pp->index);
        pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
-       pp->res[1].name = pp->mem_space_name;
+       pp->res[0].name = pp->mem_space_name;
        if (pp->index == 0) {
-               pp->res[1].start = MEM_BASE_0;
-               pp->res[1].end = pp->res[1].start + MEM_SIZE_0 - 1;
+               pp->res[0].start = MEM_BASE_0;
+               pp->res[0].end = pp->res[0].start + MEM_SIZE_0 - 1;
        } else {
-               pp->res[1].start = MEM_BASE_1;
-               pp->res[1].end = pp->res[1].start + MEM_SIZE_1 - 1;
+               pp->res[0].start = MEM_BASE_1;
+               pp->res[0].end = pp->res[0].start + MEM_SIZE_1 - 1;
        }
-       pp->res[1].flags = IORESOURCE_MEM;
-       if (request_resource(&iomem_resource, &pp->res[1]))
+       pp->res[0].flags = IORESOURCE_MEM;
+       if (request_resource(&iomem_resource, &pp->res[0]))
                panic("Request PCIe Memory resource failed\n");
-       pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
+       pci_add_resource_offset(&sys->resources, &pp->res[0], sys->mem_offset);
 
        /*
         * IORESOURCE_MEM | IORESOURCE_PREFETCH
@@ -425,18 +393,18 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
        snprintf(pp->prefetch_space_name, sizeof(pp->prefetch_space_name),
                 "PCIe %d PREFETCH MEM", pp->index);
        pp->prefetch_space_name[sizeof(pp->prefetch_space_name) - 1] = 0;
-       pp->res[2].name = pp->prefetch_space_name;
+       pp->res[1].name = pp->prefetch_space_name;
        if (pp->index == 0) {
-               pp->res[2].start = PREFETCH_MEM_BASE_0;
-               pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_0 - 1;
+               pp->res[1].start = PREFETCH_MEM_BASE_0;
+               pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_0 - 1;
        } else {
-               pp->res[2].start = PREFETCH_MEM_BASE_1;
-               pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_1 - 1;
+               pp->res[1].start = PREFETCH_MEM_BASE_1;
+               pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_1 - 1;
        }
-       pp->res[2].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-       if (request_resource(&iomem_resource, &pp->res[2]))
+       pp->res[1].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
+       if (request_resource(&iomem_resource, &pp->res[1]))
                panic("Request PCIe Prefetch Memory resource failed\n");
-       pci_add_resource_offset(&sys->resources, &pp->res[2], sys->mem_offset);
+       pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
 
        return 1;
 }
@@ -531,8 +499,8 @@ static void tegra_pcie_setup_translations(void)
 
        /* Bar 2: downstream IO bar */
        fpci_bar = ((__u32)0xfdfc << 16);
-       size = MMIO_SIZE;
-       axi_address = MMIO_BASE;
+       size = SZ_128K;
+       axi_address = TEGRA_PCIE_IO_BASE;
        afi_writel(axi_address, AFI_AXI_BAR2_START);
        afi_writel(size >> 12, AFI_AXI_BAR2_SZ);
        afi_writel(fpci_bar, AFI_FPCI_BAR2);
@@ -766,7 +734,6 @@ static void tegra_pcie_clocks_put(void)
 
 static int __init tegra_pcie_get_resources(void)
 {
-       struct resource *res_mmio = &tegra_pcie.res_mmio;
        int err;
 
        err = tegra_pcie_clocks_get();
@@ -788,34 +755,16 @@ static int __init tegra_pcie_get_resources(void)
                goto err_map_reg;
        }
 
-       err = request_resource(&iomem_resource, res_mmio);
-       if (err) {
-               pr_err("PCIE: Failed to request resources: %d\n", err);
-               goto err_req_io;
-       }
-
-       tegra_pcie_io_base = ioremap_nocache(res_mmio->start,
-                                            resource_size(res_mmio));
-       if (tegra_pcie_io_base == NULL) {
-               pr_err("PCIE: Failed to map IO\n");
-               err = -ENOMEM;
-               goto err_map_io;
-       }
-
        err = request_irq(INT_PCIE_INTR, tegra_pcie_isr,
                          IRQF_SHARED, "PCIE", &tegra_pcie);
        if (err) {
                pr_err("PCIE: Failed to register IRQ: %d\n", err);
-               goto err_irq;
+               goto err_req_io;
        }
        set_irq_flags(INT_PCIE_INTR, IRQF_VALID);
 
        return 0;
 
-err_irq:
-       iounmap(tegra_pcie_io_base);
-err_map_io:
-       release_resource(&tegra_pcie.res_mmio);
 err_req_io:
        iounmap(tegra_pcie.regs);
 err_map_reg:
index 54d8f34..f7e12ed 100644 (file)
@@ -1,6 +1,6 @@
 if ARCH_U300
 
-menu "ST-Ericsson AB U300/U330/U335/U365 Platform"
+menu "ST-Ericsson AB U300/U335 Platform"
 
 comment "ST-Ericsson Mobile Platform Products"
 
@@ -10,46 +10,7 @@ config MACH_U300
        select PINCTRL_U300
        select PINCTRL_COH901
 
-comment "ST-Ericsson U300/U330/U335/U365 Feature Selections"
-
-choice
-       prompt "U300/U330/U335/U365 system type"
-       default MACH_U300_BS2X
-       ---help---
-       You need to select the target system, i.e. the
-       U300/U330/U335/U365 board that you want to compile your kernel
-       for.
-
-config MACH_U300_BS2X
-       bool "S26/S26/B25/B26 Test Products"
-       depends on MACH_U300
-       help
-               Select this if you're developing on the
-               S26/S25 test products. (Also works on
-               B26/B25 big boards.)
-
-config MACH_U300_BS330
-       bool "S330/B330 Test Products"
-       depends on MACH_U300
-       help
-               Select this if you're developing on the
-               S330/B330 test products.
-
-config MACH_U300_BS335
-       bool "S335/B335 Test Products"
-       depends on MACH_U300
-       help
-               Select this if you're developing on the
-               S335/B335 test products.
-
-config MACH_U300_BS365
-       bool "S365/B365 Test Products"
-       depends on MACH_U300
-       help
-               Select this if you're developing on the
-               S365/B365 test products.
-
-endchoice
+comment "ST-Ericsson U300/U335 Feature Selections"
 
 config U300_DEBUG
        bool "Debug support for U300"
index 7e47d37..5a86c58 100644 (file)
@@ -7,7 +7,6 @@ obj-m           :=
 obj-n          :=
 obj-           :=
 
-obj-$(CONFIG_ARCH_U300)                  += u300.o
 obj-$(CONFIG_SPI_PL022)           += spi.o
 obj-$(CONFIG_MACH_U300_SPIDUMMY)  += dummyspichip.o
 obj-$(CONFIG_I2C_STU300)          += i2c.o
index 03acf18..ef6f602 100644 (file)
@@ -3,7 +3,7 @@
  * arch/arm/mach-u300/core.c
  *
  *
- * Copyright (C) 2007-2010 ST-Ericsson SA
+ * Copyright (C) 2007-2012 ST-Ericsson SA
  * License terms: GNU General Public License (GPL) version 2
  * Core platform support, IRQ handling and device definitions.
  * Author: Linus Walleij <linus.walleij@stericsson.com>
 #include <linux/pinctrl/pinconf-generic.h>
 #include <linux/dma-mapping.h>
 #include <linux/platform_data/clk-u300.h>
+#include <linux/platform_data/pinctrl-coh901.h>
 
 #include <asm/types.h>
 #include <asm/setup.h>
 #include <asm/memory.h>
 #include <asm/hardware/vic.h>
 #include <asm/mach/map.h>
-#include <asm/mach/irq.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
 
 #include <mach/coh901318.h>
 #include <mach/hardware.h>
 #include <mach/syscon.h>
-#include <mach/dma_channels.h>
-#include <mach/gpio-u300.h>
+#include <mach/irqs.h>
 
+#include "timer.h"
 #include "spi.h"
 #include "i2c.h"
 #include "u300-gpio.h"
+#include "dma_channels.h"
 
 /*
  * Static I/O mappings that are needed for booting the U300 platforms. The
@@ -76,7 +79,7 @@ static struct map_desc u300_io_desc[] __initdata = {
        },
 };
 
-void __init u300_map_io(void)
+static void __init u300_map_io(void)
 {
        iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
        /* We enable a real big DMA buffer if need be. */
@@ -101,7 +104,6 @@ static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE,
        { IRQ_U300_UART0 }, &uart0_plat_data);
 
 /* The U335 have an additional UART1 on the APP CPU */
-#ifdef CONFIG_MACH_U300_BS335
 static struct amba_pl011_data uart1_plat_data = {
 #ifdef CONFIG_COH901318
        .dma_filter = coh901318_filter_id,
@@ -113,7 +115,6 @@ static struct amba_pl011_data uart1_plat_data = {
 /* Fast device at 0x7000 offset */
 static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE,
        { IRQ_U300_UART1 }, &uart1_plat_data);
-#endif
 
 /* AHB device at 0x4000 offset */
 static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL);
@@ -152,9 +153,7 @@ static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE,
  */
 static struct amba_device *amba_devs[] __initdata = {
        &uart0_device,
-#ifdef CONFIG_MACH_U300_BS335
        &uart1_device,
-#endif
        &pl022_device,
        &pl172_device,
        &mmcsd_device,
@@ -188,7 +187,6 @@ static struct resource gpio_resources[] = {
                .end   = IRQ_U300_GPIO_PORT2,
                .flags = IORESOURCE_IRQ,
        },
-#if defined(CONFIG_MACH_U300_BS365) || defined(CONFIG_MACH_U300_BS335)
        {
                .name  = "gpio3",
                .start = IRQ_U300_GPIO_PORT3,
@@ -201,8 +199,6 @@ static struct resource gpio_resources[] = {
                .end   = IRQ_U300_GPIO_PORT4,
                .flags = IORESOURCE_IRQ,
        },
-#endif
-#ifdef CONFIG_MACH_U300_BS335
        {
                .name  = "gpio5",
                .start = IRQ_U300_GPIO_PORT5,
@@ -215,7 +211,6 @@ static struct resource gpio_resources[] = {
                .end   = IRQ_U300_GPIO_PORT6,
                .flags = IORESOURCE_IRQ,
        },
-#endif /* CONFIG_MACH_U300_BS335 */
 };
 
 static struct resource keypad_resources[] = {
@@ -323,7 +318,6 @@ static struct resource dma_resource[] = {
        }
 };
 
-#ifdef CONFIG_MACH_U300_BS335
 /* points out all dma slave channels.
  * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
  * Select all channels from A to B, end of list is marked with -1,-1
@@ -336,14 +330,6 @@ static int dma_slave_channels[] = {
 static int dma_memcpy_channels[] = {
        U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
 
-#else /* CONFIG_MACH_U300_BS335 */
-
-static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1};
-static int dma_memcpy_channels[] = {
-       U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1};
-
-#endif
-
 /** register dma for memory access
  *
  * active  1 means dma intends to access memory
@@ -1395,7 +1381,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                .param.ctrl_lli = flags_memcpy_lli,
                .param.ctrl_lli_last = flags_memcpy_lli_last,
        },
-#ifdef CONFIG_MACH_U300_BS335
        {
                .number = U300_DMA_UART1_TX,
                .name = "UART1 TX",
@@ -1406,28 +1391,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                .name = "UART1 RX",
                .priority_high = 0,
        }
-#else
-       {
-               .number = U300_DMA_GENERAL_PURPOSE_9,
-               .name = "GENERAL 09",
-               .priority_high = 0,
-
-               .param.config = flags_memcpy_config,
-               .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-               .param.ctrl_lli = flags_memcpy_lli,
-               .param.ctrl_lli_last = flags_memcpy_lli_last,
-       },
-       {
-               .number = U300_DMA_GENERAL_PURPOSE_10,
-               .name = "GENERAL 10",
-               .priority_high = 0,
-
-               .param.config = flags_memcpy_config,
-               .param.ctrl_lli_chained = flags_memcpy_lli_chained,
-               .param.ctrl_lli = flags_memcpy_lli,
-               .param.ctrl_lli_last = flags_memcpy_lli_last,
-       }
-#endif
 };
 
 
@@ -1480,18 +1443,7 @@ static struct platform_device pinctrl_device = {
  * GPIO block, with different number of ports.
  */
 static struct u300_gpio_platform u300_gpio_plat = {
-#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
-       .variant = U300_GPIO_COH901335,
-       .ports = 3,
-#endif
-#ifdef CONFIG_MACH_U300_BS335
-       .variant = U300_GPIO_COH901571_3_BS335,
        .ports = 7,
-#endif
-#ifdef CONFIG_MACH_U300_BS365
-       .variant = U300_GPIO_COH901571_3_BS365,
-       .ports = 5,
-#endif
        .gpio_base = 0,
        .gpio_irq_base = IRQ_U300_GPIO_BASE,
        .pinctrl_device = &pinctrl_device,
@@ -1651,7 +1603,7 @@ static struct platform_device *platform_devs[] __initdata = {
  * together so some interrupts are connected to the first one and some
  * to the second one.
  */
-void __init u300_init_irq(void)
+static void __init u300_init_irq(void)
 {
        u32 mask[2] = {0, 0};
        struct clk *clk;
@@ -1756,29 +1708,11 @@ static void __init u300_init_check_chip(void)
        printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
               "(chip ID 0x%04x)\n", chipname, val);
 
-#ifdef CONFIG_MACH_U300_BS330
-       if ((val & 0xFF00U) != 0xd800) {
-               printk(KERN_ERR "Platform configured for BS330 " \
-                      "with DB3200 but %s detected, expect problems!",
-                      chipname);
-       }
-#endif
-#ifdef CONFIG_MACH_U300_BS335
        if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
                printk(KERN_ERR "Platform configured for BS335 " \
                       " with DB3350 but %s detected, expect problems!",
                       chipname);
        }
-#endif
-#ifdef CONFIG_MACH_U300_BS365
-       if ((val & 0xFF00U) != 0xe800) {
-               printk(KERN_ERR "Platform configured for BS365 " \
-                      "with DB3210 but %s detected, expect problems!",
-                      chipname);
-       }
-#endif
-
-
 }
 
 /*
@@ -1811,7 +1745,7 @@ static void __init u300_assign_physmem(void)
        }
 }
 
-void __init u300_init_devices(void)
+static void __init u300_init_machine(void)
 {
        int i;
        u16 val;
@@ -1852,7 +1786,7 @@ void __init u300_init_devices(void)
 /* Forward declare this function from the watchdog */
 void coh901327_watchdog_reset(void);
 
-void u300_restart(char mode, const char *cmd)
+static void u300_restart(char mode, const char *cmd)
 {
        switch (mode) {
        case 's':
@@ -1868,3 +1802,15 @@ void u300_restart(char mode, const char *cmd)
        /* Wait for system do die/reset. */
        while (1);
 }
+
+MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board")
+       /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
+       .atag_offset    = 0x100,
+       .map_io         = u300_map_io,
+       .nr_irqs        = NR_IRQS_U300,
+       .init_irq       = u300_init_irq,
+       .handle_irq     = vic_handle_irq,
+       .timer          = &u300_timer,
+       .init_machine   = u300_init_machine,
+       .restart        = u300_restart,
+MACHINE_END
similarity index 88%
rename from arch/arm/mach-u300/include/mach/dma_channels.h
rename to arch/arm/mach-u300/dma_channels.h
index b239149..4e8a88f 100644 (file)
@@ -3,7 +3,7 @@
  * arch/arm/mach-u300/include/mach/dma_channels.h
  *
  *
- * Copyright (C) 2007-2009 ST-Ericsson
+ * Copyright (C) 2007-2012 ST-Ericsson
  * License terms: GNU General Public License (GPL) version 2
  * Map file for the U300 dma driver.
  * Author: Per Friden <per.friden@stericsson.com>
 #define U300_DMA_GENERAL_PURPOSE_6    35
 #define U300_DMA_GENERAL_PURPOSE_7    36
 #define U300_DMA_GENERAL_PURPOSE_8    37
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_DMA_UART1_TX             38
 #define U300_DMA_UART1_RX             39
-#else
-#define U300_DMA_GENERAL_PURPOSE_9    38
-#define U300_DMA_GENERAL_PURPOSE_10   39
-#endif
 
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_DMA_DEVICE_CHANNELS      32
-#else
-#define U300_DMA_DEVICE_CHANNELS      30
-#endif
 #define U300_DMA_CHANNELS             40
 
 
index cb04bd6..0d4620e 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-u300/i2c.c
  *
- * Copyright (C) 2009 ST-Ericsson AB
+ * Copyright (C) 2009-2012 ST-Ericsson AB
  * License terms: GNU General Public License (GPL) version 2
  *
  * Register board i2c devices
@@ -261,7 +261,6 @@ static struct i2c_board_info __initdata bus0_i2c_board_info[] = {
 };
 
 static struct i2c_board_info __initdata bus1_i2c_board_info[] = {
-#ifdef CONFIG_MACH_U300_BS335
        {
                .type = "fwcam",
                .addr = 0x10,
@@ -270,9 +269,6 @@ static struct i2c_board_info __initdata bus1_i2c_board_info[] = {
                .type = "fwcam",
                .addr = 0x5d,
        },
-#else
-       { },
-#endif
 };
 
 void __init u300_i2c_register_board_devices(void)
diff --git a/arch/arm/mach-u300/include/mach/clkdev.h b/arch/arm/mach-u300/include/mach/clkdev.h
deleted file mode 100644 (file)
index 92e3cc8..0000000
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MACH_CLKDEV_H
-#define __MACH_CLKDEV_H
-
-int __clk_get(struct clk *clk);
-void __clk_put(struct clk *clk);
-
-#endif
index ec09c1e..e27425a 100644 (file)
@@ -3,7 +3,7 @@
  * arch/arm/mach-u300/include/mach/irqs.h
  *
  *
- * Copyright (C) 2006-2009 ST-Ericsson AB
+ * Copyright (C) 2006-2012 ST-Ericsson AB
  * License terms: GNU General Public License (GPL) version 2
  * IRQ channel definitions for the U300 platforms.
  * Author: Linus Walleij <linus.walleij@stericsson.com>
 #define IRQ_U300_XGAM_GAMCON           14
 #define IRQ_U300_XGAM_CDI              15
 #define IRQ_U300_XGAM_CDICON           16
-#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
-/* MMIACC not used on the DB3210 or DB3350 chips */
-#define IRQ_U300_XGAM_MMIACC           17
-#endif
 #define IRQ_U300_XGAM_PDI              18
 #define IRQ_U300_XGAM_PDICON           19
 #define IRQ_U300_XGAM_GAMEACC          20
@@ -55,8 +51,6 @@
 #define IRQ_U300_GPIO_PORT1            34
 #define IRQ_U300_GPIO_PORT2            35
 
-#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \
-    defined(CONFIG_MACH_U300_BS335)
 /* These are for DB3150, DB3200 and DB3350 */
 #define IRQ_U300_WDOG                  36
 #define IRQ_U300_EVHIST                        37
 #define IRQ_U300_RTC                   43
 #define IRQ_U300_NFIF                  44
 #define IRQ_U300_NFIF2                 45
-#endif
-
-/* DB3150 and DB3200 have only 45 IRQs */
-#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
-#define U300_VIC_IRQS_END              46
-#endif
 
 /* The DB3350-specific interrupt lines */
-#ifdef CONFIG_MACH_U300_BS335
 #define IRQ_U300_ISP_F0                        46
 #define IRQ_U300_ISP_F1                        47
 #define IRQ_U300_ISP_F2                        48
 #define IRQ_U300_GPIO_PORT5            55
 #define IRQ_U300_GPIO_PORT6            56
 #define U300_VIC_IRQS_END              57
-#endif
-
-/* The DB3210-specific interrupt lines */
-#ifdef CONFIG_MACH_U300_BS365
-#define IRQ_U300_GPIO_PORT3            36
-#define IRQ_U300_GPIO_PORT4            37
-#define IRQ_U300_WDOG                  38
-#define IRQ_U300_EVHIST                        39
-#define IRQ_U300_MSPRO                 40
-#define IRQ_U300_MMCSD_MCIINTR0                41
-#define IRQ_U300_MMCSD_MCIINTR1                42
-#define IRQ_U300_I2C0                  43
-#define IRQ_U300_I2C1                  44
-#define IRQ_U300_RTC                   45
-#define IRQ_U300_NFIF                  46
-#define IRQ_U300_NFIF2                 47
-#define IRQ_U300_SYSCON_PLL_LOCK       48
-#define U300_VIC_IRQS_END              49
-#endif
 
 /* Maximum 8*7 GPIO lines */
 #ifdef CONFIG_PINCTRL_COH901
 #define IRQ_U300_GPIO_END              (U300_VIC_IRQS_END)
 #endif
 
-#define NR_IRQS                                (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START)
+#define NR_IRQS_U300                   (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START)
 
 #endif
diff --git a/arch/arm/mach-u300/include/mach/platform.h b/arch/arm/mach-u300/include/mach/platform.h
deleted file mode 100644 (file)
index 096333f..0000000
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/platform.h
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Basic platform init and mapping functions.
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-
-#ifndef __ASSEMBLY__
-
-void u300_map_io(void);
-void u300_init_irq(void);
-void u300_init_devices(void);
-void u300_restart(char, const char *);
-extern struct sys_timer u300_timer;
-
-#endif
index 6e84f07..10bdd0b 100644 (file)
@@ -3,7 +3,7 @@
  * arch/arm/mach-u300/include/mach/syscon.h
  *
  *
- * Copyright (C) 2008 ST-Ericsson AB
+ * Copyright (C) 2008-2012 ST-Ericsson AB
  *
  * Author: Rickard Andersson <rickard.andersson@stericsson.com>
  */
@@ -36,9 +36,7 @@
 #define U300_SYSCON_CSR_PLL13_LOCK_IND                         (0x0001)
 /* Reset lines for SLOW devices 16bit (R/W) */
 #define U300_SYSCON_RSR                                                (0x0014)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_RSR_PPM_RESET_EN                           (0x0200)
-#endif
 #define U300_SYSCON_RSR_ACC_TMR_RESET_EN                       (0x0100)
 #define U300_SYSCON_RSR_APP_TMR_RESET_EN                       (0x0080)
 #define U300_SYSCON_RSR_RTC_RESET_EN                           (0x0040)
@@ -50,9 +48,7 @@
 #define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN                   (0x0001)
 /* Reset lines for FAST devices 16bit (R/W) */
 #define U300_SYSCON_RFR                                                (0x0018)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_RFR_UART1_RESET_ENABLE                     (0x0080)
-#endif
 #define U300_SYSCON_RFR_SPI_RESET_ENABLE                       (0x0040)
 #define U300_SYSCON_RFR_MMC_RESET_ENABLE                       (0x0020)
 #define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE                  (0x0010)
 #define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE               (0x0001)
 /* Reset lines for the rest of the peripherals 16bit (R/W) */
 #define U300_SYSCON_RRR                                                (0x001c)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_RRR_CDS_RESET_EN                           (0x4000)
 #define U300_SYSCON_RRR_ISP_RESET_EN                           (0x2000)
-#endif
 #define U300_SYSCON_RRR_INTCON_RESET_EN                                (0x1000)
 #define U300_SYSCON_RRR_MSPRO_RESET_EN                         (0x0800)
 #define U300_SYSCON_RRR_XGAM_RESET_EN                          (0x0100)
@@ -79,9 +73,7 @@
 #define U300_SYSCON_RRR_AAIF_RESET_EN                          (0x0001)
 /* Clock enable for SLOW peripherals 16bit (R/W) */
 #define U300_SYSCON_CESR                                       (0x0020)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CESR_PPM_CLK_EN                            (0x0200)
-#endif
 #define U300_SYSCON_CESR_ACC_TMR_CLK_EN                                (0x0100)
 #define U300_SYSCON_CESR_APP_TMR_CLK_EN                                (0x0080)
 #define U300_SYSCON_CESR_KEYPAD_CLK_EN                         (0x0040)
 #define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN                    (0x0001)
 /* Clock enable for FAST peripherals 16bit (R/W) */
 #define U300_SYSCON_CEFR                                       (0x0024)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CEFR_UART1_CLK_EN                          (0x0200)
-#endif
 #define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN                      (0x0100)
 #define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN                      (0x0080)
 #define U300_SYSCON_CEFR_SPI_CLK_EN                            (0x0040)
 #define U300_SYSCON_CEFR_MMC_CLK_EN                            (0x0020)
-#define U300_SYSCON_CEFR_I2S1_CLK_EN                           (0x0010)
-#define U300_SYSCON_CEFR_I2S0_CLK_EN                           (0x0008)
-#define U300_SYSCON_CEFR_I2C1_CLK_EN                           (0x0004)
-#define U300_SYSCON_CEFR_I2C0_CLK_EN                           (0x0002)
+#define U300_SYSCON_CEFR_I2S1_CLK_EN                           (0x0010)
+#define U300_SYSCON_CEFR_I2S0_CLK_EN                           (0x0008)
+#define U300_SYSCON_CEFR_I2C1_CLK_EN                           (0x0004)
+#define U300_SYSCON_CEFR_I2C0_CLK_EN                           (0x0002)
 #define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN                    (0x0001)
 /* Clock enable for the rest of the peripherals 16bit (R/W) */
 #define U300_SYSCON_CERR                                       (0x0028)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CERR_CDS_CLK_EN                            (0x2000)
 #define U300_SYSCON_CERR_ISP_CLK_EN                            (0x1000)
-#endif
 #define U300_SYSCON_CERR_MSPRO_CLK_EN                          (0x0800)
 #define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN              (0x0400)
 #define U300_SYSCON_CERR_SEMI_CLK_EN                           (0x0200)
 #define U300_SYSCON_CERR_AAIF_CLK_EN                           (0x0001)
 /* Single block clock enable 16bit (-/W) */
 #define U300_SYSCON_SBCER                                      (0x002c)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_SBCER_PPM_CLK_EN                           (0x0009)
-#endif
 #define U300_SYSCON_SBCER_ACC_TMR_CLK_EN                       (0x0008)
 #define U300_SYSCON_SBCER_APP_TMR_CLK_EN                       (0x0007)
 #define U300_SYSCON_SBCER_KEYPAD_CLK_EN                                (0x0006)
 #define U300_SYSCON_SBCER_BTR_CLK_EN                           (0x0002)
 #define U300_SYSCON_SBCER_UART_CLK_EN                          (0x0001)
 #define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN                   (0x0000)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_SBCER_UART1_CLK_EN                         (0x0019)
-#endif
 #define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN                     (0x0018)
 #define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN                     (0x0017)
 #define U300_SYSCON_SBCER_SPI_CLK_EN                           (0x0016)
 #define U300_SYSCON_SBCER_I2C1_CLK_EN                          (0x0012)
 #define U300_SYSCON_SBCER_I2C0_CLK_EN                          (0x0011)
 #define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN                   (0x0010)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_SBCER_CDS_CLK_EN                           (0x002D)
 #define U300_SYSCON_SBCER_ISP_CLK_EN                           (0x002C)
-#endif
 #define U300_SYSCON_SBCER_MSPRO_CLK_EN                         (0x002B)
 #define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN             (0x002A)
 #define U300_SYSCON_SBCER_SEMI_CLK_EN                          (0x0029)
 /* Same values as above for SBCER */
 /* Clock force SLOW peripherals 16bit (R/W) */
 #define U300_SYSCON_CFSR                                       (0x003c)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN                      (0x0200)
-#endif
 #define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN                  (0x0100)
 #define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN                  (0x0080)
 #define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN                   (0x0020)
 /* Values not defined. Define if you want to use them. */
 /* Clock force the rest of the peripherals 16bit (R/W) */
 #define U300_SYSCON_CFRR                                       (0x44)
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN                      (0x2000)
 #define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN                      (0x1000)
-#endif
 #define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN                    (0x0800)
 #define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN                (0x0400)
 #define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN                     (0x0200)
index 65f87c5..1e49d90 100644 (file)
@@ -28,7 +28,6 @@
 #define PLAT_NAND_CLE                  (1 << 16)
 #define PLAT_NAND_ALE                  (1 << 17)
 
-
 /* AHB Peripherals */
 #define U300_AHB_PER_PHYS_BASE         0xa0000000
 #define U300_AHB_PER_VIRT_BASE         0xff010000
 #define U300_BOOTROM_VIRT_BASE         0xffff0000
 
 /* SEMI config base */
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_SEMI_CONFIG_BASE          0x2FFE0000
-#else
-#define U300_SEMI_CONFIG_BASE          0x30000000
-#endif
 
 /*
  * AHB peripherals
 /* SPI controller */
 #define U300_SPI_BASE                  (U300_FAST_PER_PHYS_BASE+0x6000)
 
-#ifdef CONFIG_MACH_U300_BS335
 /* Fast UART1 on U335 only */
 #define U300_UART1_BASE                        (U300_SLOW_PER_PHYS_BASE+0x7000)
-#endif
 
 /*
  * SLOW peripherals
  * REST peripherals
  */
 
-/* ISP (image signal processor) is only available in U335 */
-#ifdef CONFIG_MACH_U300_BS335
+/* ISP (image signal processor) */
 #define U300_ISP_BASE                  (0xA0008000)
-#endif
 
 /* DMA Controller base */
 #define U300_DMAC_BASE                 (0xC0020000)
 #define U300_APEX_BASE                 (0xc0030000)
 
 /* Video Encoder Base */
-#ifdef CONFIG_MACH_U300_BS335
 #define U300_VIDEOENC_BASE             (0xc0080000)
-#else
-#define U300_VIDEOENC_BASE             (0xc0040000)
-#endif
 
 /* XGAM Base */
 #define U300_XGAM_BASE                 (0xd0000000)
 
-/*
- * Virtual accessor macros for static devices
- */
-
 #endif
index a1affac..02e6659 100644 (file)
@@ -12,7 +12,7 @@
 #include <linux/amba/pl022.h>
 #include <linux/err.h>
 #include <mach/coh901318.h>
-#include <mach/dma_channels.h>
+#include "dma_channels.h"
 
 /*
  * The following is for the actual devices on the SSP/SPI bus
index 56ac06d..1da10e2 100644 (file)
 #include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/err.h>
+#include <linux/irq.h>
 
 #include <mach/hardware.h>
+#include <mach/irqs.h>
 
 /* Generic stuff */
 #include <asm/sched_clock.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <asm/mach/irq.h>
+
+#include "timer.h"
 
 /*
  * APP side special timer registers
diff --git a/arch/arm/mach-u300/timer.h b/arch/arm/mach-u300/timer.h
new file mode 100644 (file)
index 0000000..b5e9791
--- /dev/null
@@ -0,0 +1 @@
+extern struct sys_timer u300_timer;
index 847dc25..83f5077 100644 (file)
@@ -1,50 +1,11 @@
 /*
- * Individual pin assignments for the B26/S26. Notice that the
- * actual usage of these pins depends on the PAD MUX settings, that
- * is why the same number can potentially appear several times.
- * In the reference design each pin is only used for one purpose.
- * These were determined by inspecting the B26/S26 schematic:
- * 2/1911-ROA 128 1603
- */
-#ifdef CONFIG_MACH_U300_BS2X
-#define U300_GPIO_PIN_UART_RX          0
-#define U300_GPIO_PIN_UART_TX          1
-#define U300_GPIO_PIN_GPIO02           2  /* Unrouted */
-#define U300_GPIO_PIN_GPIO03           3  /* Unrouted */
-#define U300_GPIO_PIN_CAM_SLEEP                4
-#define U300_GPIO_PIN_CAM_REG_EN       5
-#define U300_GPIO_PIN_GPIO06           6  /* Unrouted */
-#define U300_GPIO_PIN_GPIO07           7  /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO08           8  /* Service point SP2321 */
-#define U300_GPIO_PIN_GPIO09           9  /* Service point SP2322 */
-#define U300_GPIO_PIN_PHFSENSE         10 /* Headphone jack sensing */
-#define U300_GPIO_PIN_MMC_CLKRET       11 /* Clock return from MMC/SD card */
-#define U300_GPIO_PIN_MMC_CD           12 /* MMC Card insertion detection */
-#define U300_GPIO_PIN_FLIPSENSE                13 /* Mechanical flip sensing */
-#define U300_GPIO_PIN_GPIO14           14 /* DSP JTAG Port RTCK */
-#define U300_GPIO_PIN_GPIO15           15 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO16           16 /* Unrouted */
-#define U300_GPIO_PIN_GPIO17           17 /* Unrouted */
-#define U300_GPIO_PIN_GPIO18           18 /* Unrouted */
-#define U300_GPIO_PIN_GPIO19           19 /* Unrouted */
-#define U300_GPIO_PIN_GPIO20           20 /* Unrouted */
-#define U300_GPIO_PIN_GPIO21           21 /* Unrouted */
-#define U300_GPIO_PIN_GPIO22           22 /* Unrouted */
-#define U300_GPIO_PIN_GPIO23           23 /* Unrouted */
-#endif
-
-/*
- * Individual pin assignments for the B330/S330 and B365/S365.
+ * Individual pin assignments for the B335/S335.
  * Notice that the actual usage of these pins depends on the
  * PAD MUX settings, that is why the same number can potentially
  * appear several times. In the reference design each pin is only
  * used for one purpose. These were determined by inspecting the
  * S365 schematic.
  */
-#if defined(CONFIG_MACH_U300_BS330) || defined(CONFIG_MACH_U300_BS365) || \
-    defined(CONFIG_MACH_U300_BS335)
 #define U300_GPIO_PIN_UART_RX          0
 #define U300_GPIO_PIN_UART_TX          1
 #define U300_GPIO_PIN_UART_CTS         2
@@ -90,8 +51,6 @@
 #define U300_GPIO_PIN_GPIO38           38 /* Unrouted */
 #define U300_GPIO_PIN_GPIO39           39 /* Unrouted */
 
-#ifdef CONFIG_MACH_U300_BS335
-
 #define U300_GPIO_PIN_GPIO40           40 /* Unrouted */
 #define U300_GPIO_PIN_GPIO41           41 /* Unrouted */
 #define U300_GPIO_PIN_GPIO42           42 /* Unrouted */
 #define U300_GPIO_PIN_GPIO53           53 /* Unrouted */
 #define U300_GPIO_PIN_GPIO54           54 /* Unrouted */
 #define U300_GPIO_PIN_GPIO55           55 /* Unrouted */
-#endif
-
-#endif
diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c
deleted file mode 100644 (file)
index f30c69d..0000000
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/u300.c
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Platform machine definition.
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/memblock.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
-#include <asm/hardware/vic.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/memory.h>
-
-static void __init u300_init_machine(void)
-{
-       u300_init_devices();
-}
-
-#ifdef CONFIG_MACH_U300_BS2X
-#define MACH_U300_STRING "Ericsson AB U300 S25/S26/B25/B26 Prototype Board"
-#endif
-
-#ifdef CONFIG_MACH_U300_BS330
-#define MACH_U300_STRING "Ericsson AB U330 S330/B330 Prototype Board"
-#endif
-
-#ifdef CONFIG_MACH_U300_BS335
-#define MACH_U300_STRING "Ericsson AB U335 S335/B335 Prototype Board"
-#endif
-
-#ifdef CONFIG_MACH_U300_BS365
-#define MACH_U300_STRING "Ericsson AB U365 S365/B365 Prototype Board"
-#endif
-
-MACHINE_START(U300, MACH_U300_STRING)
-       /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
-       .atag_offset    = 0x100,
-       .map_io         = u300_map_io,
-       .init_irq       = u300_init_irq,
-       .handle_irq     = vic_handle_irq,
-       .timer          = &u300_timer,
-       .init_machine   = u300_init_machine,
-       .restart        = u300_restart,
-MACHINE_END
index 4e59746..7e6c384 100644 (file)
@@ -20,7 +20,6 @@
 
 #include <asm/pmu.h>
 #include <asm/mach/map.h>
-#include <asm/pmu.h>
 #include <plat/gpio-nomadik.h>
 #include <mach/hardware.h>
 #include <mach/setup.h>
@@ -123,7 +122,7 @@ struct arm_pmu_platdata db8500_pmu_platdata = {
 
 static struct platform_device db8500_pmu_device = {
        .name                   = "arm-pmu",
-       .id                     = ARM_PMU_DEVICE_CPU,
+       .id                     = -1,
        .num_resources          = ARRAY_SIZE(db8500_pmu_resources),
        .resource               = db8500_pmu_resources,
        .dev.platform_data      = &db8500_pmu_platdata,
index cd8ea35..ca7902c 100644 (file)
@@ -169,11 +169,6 @@ static struct map_desc versatile_io_desc[] __initdata = {
                .pfn            = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
                .length         = VERSATILE_PCI_CFG_BASE_SIZE,
                .type           = MT_DEVICE
-       }, {
-               .virtual        =  (unsigned long)VERSATILE_PCI_VIRT_MEM_BASE0,
-               .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
-               .length         = IO_SPACE_LIMIT,
-               .type           = MT_DEVICE
        },
 #endif
 };
index 408e58d..3e5d425 100644 (file)
@@ -29,7 +29,6 @@
  */
 #define VERSATILE_PCI_VIRT_BASE                (void __iomem *)0xe8000000ul
 #define VERSATILE_PCI_CFG_VIRT_BASE    (void __iomem *)0xe9000000ul
-#define VERSATILE_PCI_VIRT_MEM_BASE0   (void __iomem *)PCIO_BASE
 
 /* macro to get at MMIO space when running virtually */
 #define IO_ADDRESS(x)          (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
diff --git a/arch/arm/mach-versatile/include/mach/io.h b/arch/arm/mach-versatile/include/mach/io.h
deleted file mode 100644 (file)
index 0406513..0000000
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- *  arch/arm/mach-versatile/include/mach/io.h
- *
- *  Copyright (C) 2003 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define PCIO_BASE      0xeb000000ul
-
-#define __io(a)                ((a) + PCIO_BASE)
-
-#endif
index e95bf84..2f84f40 100644 (file)
@@ -169,13 +169,6 @@ static struct pci_ops pci_versatile_ops = {
        .write  = versatile_write_config,
 };
 
-static struct resource io_port = {
-       .name   = "PCI",
-       .start  = 0,
-       .end    = IO_SPACE_LIMIT,
-       .flags  = IORESOURCE_IO,
-};
-
 static struct resource io_mem = {
        .name   = "PCI I/O space",
        .start  = VERSATILE_PCI_MEM_BASE0,
@@ -207,12 +200,6 @@ static int __init pci_versatile_setup_resources(struct pci_sys_data *sys)
                       "memory region (%d)\n", ret);
                goto out;
        }
-       ret = request_resource(&ioport_resource, &io_port);
-       if (ret) {
-               printk(KERN_ERR "PCI: unable to allocate I/O "
-                      "port region (%d)\n", ret);
-               goto out;
-       }
        ret = request_resource(&iomem_resource, &non_mem);
        if (ret) {
                printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
@@ -227,11 +214,9 @@ static int __init pci_versatile_setup_resources(struct pci_sys_data *sys)
        }
 
        /*
-        * the IO resource for this bus
         * the mem resource for this bus
         * the prefetch mem resource for this bus
         */
-       pci_add_resource_offset(&sys->resources, &io_port, sys->io_offset);
        pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset);
        pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset);
 
@@ -260,9 +245,11 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
                goto out;
        }
 
+       ret = pci_ioremap_io(0, VERSATILE_PCI_MEM_BASE0);
+       if (ret)
+               goto out;
+
        if (nr == 0) {
-               sys->mem_offset = 0;
-               sys->io_offset = 0;
                ret = pci_versatile_setup_resources(sys);
                if (ret < 0) {
                        printk("pci_versatile_setup: resources... oops?\n");
@@ -319,7 +306,6 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
 
 void __init pci_versatile_preinit(void)
 {
-       pcibios_min_io = 0x44000000;
        pcibios_min_mem = 0x50000000;
 
        __raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0);
index 61c4924..e4073a6 100644 (file)
@@ -13,7 +13,6 @@
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
-#include <asm/pmu.h>
 #include <asm/smp_scu.h>
 #include <asm/smp_twd.h>
 
@@ -144,7 +143,7 @@ static struct resource pmu_resources[] = {
 
 static struct platform_device pmu_device = {
        .name           = "arm-pmu",
-       .id             = ARM_PMU_DEVICE_CPU,
+       .id             = -1,
        .num_resources  = ARRAY_SIZE(pmu_resources),
        .resource       = pmu_resources,
 };
index 566750f..9d869f9 100644 (file)
@@ -36,6 +36,7 @@
 #include <asm/system_info.h>
 
 #include <asm/mach/map.h>
+#include <asm/mach/pci.h>
 #include "mm.h"
 
 int ioremap_page(unsigned long virt, unsigned long phys,
@@ -383,3 +384,16 @@ void __arm_iounmap(volatile void __iomem *io_addr)
        arch_iounmap(io_addr);
 }
 EXPORT_SYMBOL(__arm_iounmap);
+
+#ifdef CONFIG_PCI
+int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr)
+{
+       BUG_ON(offset + SZ_64K > IO_SPACE_LIMIT);
+
+       return ioremap_page_range(PCI_IO_VIRT_BASE + offset,
+                                 PCI_IO_VIRT_BASE + offset + SZ_64K,
+                                 phys_addr,
+                                 __pgprot(get_mem_type(MT_DEVICE)->prot_pte));
+}
+EXPORT_SYMBOL_GPL(pci_ioremap_io);
+#endif
index c2fa21d..18144e6 100644 (file)
@@ -31,6 +31,7 @@
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/mach/pci.h>
 
 #include "mm.h"
 
@@ -216,7 +217,7 @@ static struct mem_type mem_types[] = {
                .prot_l1        = PMD_TYPE_TABLE,
                .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_WB,
                .domain         = DOMAIN_IO,
-       },      
+       },
        [MT_DEVICE_WC] = {      /* ioremap_wc */
                .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
                .prot_l1        = PMD_TYPE_TABLE,
@@ -777,14 +778,27 @@ void __init iotable_init(struct map_desc *io_desc, int nr)
                create_mapping(md);
                vm->addr = (void *)(md->virtual & PAGE_MASK);
                vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
-               vm->phys_addr = __pfn_to_phys(md->pfn); 
-               vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; 
+               vm->phys_addr = __pfn_to_phys(md->pfn);
+               vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
                vm->flags |= VM_ARM_MTYPE(md->type);
                vm->caller = iotable_init;
                vm_area_add_early(vm++);
        }
 }
 
+void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
+                                 void *caller)
+{
+       struct vm_struct *vm;
+
+       vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm));
+       vm->addr = (void *)addr;
+       vm->size = size;
+       vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
+       vm->caller = caller;
+       vm_area_add_early(vm);
+}
+
 #ifndef CONFIG_ARM_LPAE
 
 /*
@@ -802,14 +816,7 @@ void __init iotable_init(struct map_desc *io_desc, int nr)
 
 static void __init pmd_empty_section_gap(unsigned long addr)
 {
-       struct vm_struct *vm;
-
-       vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm));
-       vm->addr = (void *)addr;
-       vm->size = SECTION_SIZE;
-       vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
-       vm->caller = pmd_empty_section_gap;
-       vm_area_add_early(vm);
+       vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
 }
 
 static void __init fill_pmd_gaps(void)
@@ -858,6 +865,28 @@ static void __init fill_pmd_gaps(void)
 #define fill_pmd_gaps() do { } while (0)
 #endif
 
+#if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
+static void __init pci_reserve_io(void)
+{
+       struct vm_struct *vm;
+       unsigned long addr;
+
+       /* we're still single threaded hence no lock needed here */
+       for (vm = vmlist; vm; vm = vm->next) {
+               if (!(vm->flags & VM_ARM_STATIC_MAPPING))
+                       continue;
+               addr = (unsigned long)vm->addr;
+               addr &= ~(SZ_2M - 1);
+               if (addr == PCI_IO_VIRT_BASE)
+                       return;
+
+       }
+       vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
+}
+#else
+#define pci_reserve_io() do { } while (0)
+#endif
+
 static void * __initdata vmalloc_min =
        (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
 
@@ -1141,6 +1170,9 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
                mdesc->map_io();
        fill_pmd_gaps();
 
+       /* Reserve fixed i/o space in VMALLOC region */
+       pci_reserve_io();
+
        /*
         * Finally flush the caches and tlb to ensure that we're in a
         * consistent state wrt the writebuffer.  This also ensures that
index 8daae9b..362474b 100644 (file)
@@ -192,30 +192,24 @@ int iop3xx_pci_setup(int nr, struct pci_sys_data *sys)
        if (nr != 0)
                return 0;
 
-       res = kzalloc(2 * sizeof(struct resource), GFP_KERNEL);
+       res = kzalloc(sizeof(struct resource), GFP_KERNEL);
        if (!res)
                panic("PCI: unable to alloc resources");
 
-       res[0].start = IOP3XX_PCI_LOWER_IO_PA;
-       res[0].end   = IOP3XX_PCI_LOWER_IO_PA + IOP3XX_PCI_IO_WINDOW_SIZE - 1;
-       res[0].name  = "IOP3XX PCI I/O Space";
-       res[0].flags = IORESOURCE_IO;
-       request_resource(&ioport_resource, &res[0]);
-
-       res[1].start = IOP3XX_PCI_LOWER_MEM_PA;
-       res[1].end   = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1;
-       res[1].name  = "IOP3XX PCI Memory Space";
-       res[1].flags = IORESOURCE_MEM;
-       request_resource(&iomem_resource, &res[1]);
+       res->start = IOP3XX_PCI_LOWER_MEM_PA;
+       res->end   = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1;
+       res->name  = "IOP3XX PCI Memory Space";
+       res->flags = IORESOURCE_MEM;
+       request_resource(&iomem_resource, res);
 
        /*
         * Use whatever translation is already setup.
         */
        sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0;
-       sys->io_offset  = IOP3XX_PCI_LOWER_IO_PA - *IOP3XX_OIOWTVR;
 
-       pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
-       pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
+       pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
+
+       pci_ioremap_io(0, IOP3XX_PCI_LOWER_IO_PA);
 
        return 1;
 }
@@ -367,7 +361,6 @@ void __init iop3xx_pci_preinit_cond(void)
 
 void __init iop3xx_pci_preinit(void)
 {
-       pcibios_min_io = 0;
        pcibios_min_mem = 0;
 
        iop3xx_atu_disable();
index a2024b8..ad9f974 100644 (file)
@@ -9,7 +9,6 @@
  */
 
 #include <linux/platform_device.h>
-#include <asm/pmu.h>
 #include <mach/irqs.h>
 
 static struct resource pmu_resource = {
@@ -26,7 +25,7 @@ static struct resource pmu_resource = {
 
 static struct platform_device pmu_device = {
        .name           = "arm-pmu",
-       .id             = ARM_PMU_DEVICE_CPU,
+       .id             = -1,
        .resource       = &pmu_resource,
        .num_resources  = 1,
 };
index bade586..5b217f4 100644 (file)
@@ -25,11 +25,6 @@ static struct map_desc iop3xx_std_desc[] __initdata = {
                .pfn            = __phys_to_pfn(IOP3XX_PERIPHERAL_PHYS_BASE),
                .length         = IOP3XX_PERIPHERAL_SIZE,
                .type           = MT_UNCACHED,
-        }, {   /* PCI IO space */
-               .virtual        = IOP3XX_PCI_LOWER_IO_VA,
-               .pfn            = __phys_to_pfn(IOP3XX_PCI_LOWER_IO_PA),
-               .length         = IOP3XX_PCI_IO_WINDOW_SIZE,
-               .type           = MT_DEVICE,
         },
 };
 
index 6ac7200..149237e 100644 (file)
@@ -3,7 +3,7 @@
 #
 
 # Common support
-obj-y := clock.o time.o devices.o cpu.o system.o irq-common.o
+obj-y := time.o devices.o cpu.o system.o irq-common.o
 
 obj-$(CONFIG_MXC_TZIC) += tzic.o
 obj-$(CONFIG_MXC_AVIC) += avic.o
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
deleted file mode 100644 (file)
index 5079787..0000000
+++ /dev/null
@@ -1,257 +0,0 @@
-/*
- * Based on arch/arm/plat-omap/clock.c
- *
- * Copyright (C) 2004 - 2005 Nokia corporation
- * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
- * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
- * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-
-/* #define DEBUG */
-
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/module.h>
-#include <linux/mutex.h>
-#include <linux/platform_device.h>
-#include <linux/proc_fs.h>
-#include <linux/semaphore.h>
-#include <linux/string.h>
-
-#include <mach/clock.h>
-#include <mach/hardware.h>
-
-#ifndef CONFIG_COMMON_CLK
-static LIST_HEAD(clocks);
-static DEFINE_MUTEX(clocks_mutex);
-
-/*-------------------------------------------------------------------------
- * Standard clock functions defined in include/linux/clk.h
- *-------------------------------------------------------------------------*/
-
-static void __clk_disable(struct clk *clk)
-{
-       if (clk == NULL || IS_ERR(clk))
-               return;
-       WARN_ON(!clk->usecount);
-
-       if (!(--clk->usecount)) {
-               if (clk->disable)
-                       clk->disable(clk);
-               __clk_disable(clk->parent);
-               __clk_disable(clk->secondary);
-       }
-}
-
-static int __clk_enable(struct clk *clk)
-{
-       if (clk == NULL || IS_ERR(clk))
-               return -EINVAL;
-
-       if (clk->usecount++ == 0) {
-               __clk_enable(clk->parent);
-               __clk_enable(clk->secondary);
-
-               if (clk->enable)
-                       clk->enable(clk);
-       }
-       return 0;
-}
-
-/* This function increments the reference count on the clock and enables the
- * clock if not already enabled. The parent clock tree is recursively enabled
- */
-int clk_enable(struct clk *clk)
-{
-       int ret = 0;
-
-       if (clk == NULL || IS_ERR(clk))
-               return -EINVAL;
-
-       mutex_lock(&clocks_mutex);
-       ret = __clk_enable(clk);
-       mutex_unlock(&clocks_mutex);
-
-       return ret;
-}
-EXPORT_SYMBOL(clk_enable);
-
-/* This function decrements the reference count on the clock and disables
- * the clock when reference count is 0. The parent clock tree is
- * recursively disabled
- */
-void clk_disable(struct clk *clk)
-{
-       if (clk == NULL || IS_ERR(clk))
-               return;
-
-       mutex_lock(&clocks_mutex);
-       __clk_disable(clk);
-       mutex_unlock(&clocks_mutex);
-}
-EXPORT_SYMBOL(clk_disable);
-
-/* Retrieve the *current* clock rate. If the clock itself
- * does not provide a special calculation routine, ask
- * its parent and so on, until one is able to return
- * a valid clock rate
- */
-unsigned long clk_get_rate(struct clk *clk)
-{
-       if (clk == NULL || IS_ERR(clk))
-               return 0UL;
-
-       if (clk->get_rate)
-               return clk->get_rate(clk);
-
-       return clk_get_rate(clk->parent);
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-/* Round the requested clock rate to the nearest supported
- * rate that is less than or equal to the requested rate.
- * This is dependent on the clock's current parent.
- */
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-       if (clk == NULL || IS_ERR(clk) || !clk->round_rate)
-               return 0;
-
-       return clk->round_rate(clk, rate);
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-/* Set the clock to the requested clock rate. The rate must
- * match a supported rate exactly based on what clk_round_rate returns
- */
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-       int ret = -EINVAL;
-
-       if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0)
-               return ret;
-
-       mutex_lock(&clocks_mutex);
-       ret = clk->set_rate(clk, rate);
-       mutex_unlock(&clocks_mutex);
-
-       return ret;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-/* Set the clock's parent to another clock source */
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-       int ret = -EINVAL;
-       struct clk *old;
-
-       if (clk == NULL || IS_ERR(clk) || parent == NULL ||
-           IS_ERR(parent) || clk->set_parent == NULL)
-               return ret;
-
-       if (clk->usecount)
-               clk_enable(parent);
-
-       mutex_lock(&clocks_mutex);
-       ret = clk->set_parent(clk, parent);
-       if (ret == 0) {
-               old = clk->parent;
-               clk->parent = parent;
-       } else {
-               old = parent;
-       }
-       mutex_unlock(&clocks_mutex);
-
-       if (clk->usecount)
-               clk_disable(old);
-
-       return ret;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
-/* Retrieve the clock's parent clock source */
-struct clk *clk_get_parent(struct clk *clk)
-{
-       struct clk *ret = NULL;
-
-       if (clk == NULL || IS_ERR(clk))
-               return ret;
-
-       return clk->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
-
-#else
-
-/*
- * Lock to protect the clock module (ccm) registers. Used
- * on all i.MXs
- */
-DEFINE_SPINLOCK(imx_ccm_lock);
-
-#endif /* CONFIG_COMMON_CLK */
-
-/*
- * Get the resulting clock rate from a PLL register value and the input
- * frequency. PLLs with this register layout can at least be found on
- * MX1, MX21, MX27 and MX31
- *
- *                  mfi + mfn / (mfd + 1)
- *  f = 2 * f_ref * --------------------
- *                        pd + 1
- */
-unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq)
-{
-       long long ll;
-       int mfn_abs;
-       unsigned int mfi, mfn, mfd, pd;
-
-       mfi = (reg_val >> 10) & 0xf;
-       mfn = reg_val & 0x3ff;
-       mfd = (reg_val >> 16) & 0x3ff;
-       pd =  (reg_val >> 26) & 0xf;
-
-       mfi = mfi <= 5 ? 5 : mfi;
-
-       mfn_abs = mfn;
-
-       /* On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
-        * 2's complements number
-        */
-       if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
-               mfn_abs = 0x400 - mfn;
-
-       freq *= 2;
-       freq /= pd + 1;
-
-       ll = (unsigned long long)freq * mfn_abs;
-
-       do_div(ll, mfd + 1);
-
-       if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
-               ll = -ll;
-
-       ll = (freq * mfi) + ll;
-
-       return ll;
-}
index 73db34b..b5b6f80 100644 (file)
@@ -23,7 +23,6 @@
 #include <linux/err.h>
 #include <linux/slab.h>
 #include <mach/hardware.h>
-#include <mach/clock.h>
 
 #define CLK32_FREQ     32768
 #define NANOSECOND     (1000 * 1000 * 1000)
index 2020d84..d390f00 100644 (file)
@@ -87,7 +87,7 @@ const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = {
 #ifdef CONFIG_SOC_IMX35
 const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = {
 #define imx35_imx_uart_data_entry(_id, _hwid)                          \
-       imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_16K)
+       imx_imx_uart_1irq_data_entry(MX35, _id, _hwid, SZ_16K)
        imx35_imx_uart_data_entry(0, 1),
        imx35_imx_uart_data_entry(1, 2),
        imx35_imx_uart_data_entry(2, 3),
diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h
deleted file mode 100644 (file)
index bd940c7..0000000
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-
-#ifndef __ASM_ARCH_MXC_CLOCK_H__
-#define __ASM_ARCH_MXC_CLOCK_H__
-
-#ifndef __ASSEMBLY__
-#include <linux/list.h>
-
-#ifndef CONFIG_COMMON_CLK
-struct module;
-
-struct clk {
-       int id;
-       /* Source clock this clk depends on */
-       struct clk *parent;
-       /* Secondary clock to enable/disable with this clock */
-       struct clk *secondary;
-       /* Reference count of clock enable/disable */
-       __s8 usecount;
-       /* Register bit position for clock's enable/disable control. */
-       u8 enable_shift;
-       /* Register address for clock's enable/disable control. */
-       void __iomem *enable_reg;
-       u32 flags;
-       /* get the current clock rate (always a fresh value) */
-       unsigned long (*get_rate) (struct clk *);
-       /* Function ptr to set the clock to a new rate. The rate must match a
-          supported rate returned from round_rate. Leave blank if clock is not
-          programmable */
-       int (*set_rate) (struct clk *, unsigned long);
-       /* Function ptr to round the requested clock rate to the nearest
-          supported rate that is less than or equal to the requested rate. */
-       unsigned long (*round_rate) (struct clk *, unsigned long);
-       /* Function ptr to enable the clock. Leave blank if clock can not
-          be gated. */
-       int (*enable) (struct clk *);
-       /* Function ptr to disable the clock. Leave blank if clock can not
-          be gated. */
-       void (*disable) (struct clk *);
-       /* Function ptr to set the parent clock of the clock. */
-       int (*set_parent) (struct clk *, struct clk *);
-};
-
-int clk_register(struct clk *clk);
-void clk_unregister(struct clk *clk);
-#endif /* CONFIG_COMMON_CLK */
-
-extern spinlock_t imx_ccm_lock;
-
-unsigned long mxc_decode_pll(unsigned int pll, u32 f_ref);
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ASM_ARCH_MXC_CLOCK_H__ */
index 3c080a3..7ded6f1 100644 (file)
@@ -23,7 +23,6 @@
 #ifndef __MACH_MX2_CAM_H_
 #define __MACH_MX2_CAM_H_
 
-#define MX2_CAMERA_SWAP16              (1 << 0)
 #define MX2_CAMERA_EXT_VSYNC           (1 << 1)
 #define MX2_CAMERA_CCIR                        (1 << 2)
 #define MX2_CAMERA_CCIR_INTERLACE      (1 << 3)
@@ -31,7 +30,6 @@
 #define MX2_CAMERA_GATED_CLOCK         (1 << 5)
 #define MX2_CAMERA_INV_DATA            (1 << 6)
 #define MX2_CAMERA_PCLK_SAMPLE_RISING  (1 << 7)
-#define MX2_CAMERA_PACK_DIR_MSB                (1 << 8)
 
 /**
  * struct mx2_camera_platform_data - optional platform data for mx2_camera
index dbced61..ee9b1f9 100644 (file)
@@ -76,7 +76,7 @@
 #define MX31_RTIC_BASE_ADDR                    (MX31_AIPS2_BASE_ADDR + 0xec000)
 
 #define MX31_ROMP_BASE_ADDR            0x60000000
-#define MX31_ROMP_BASE_ADDR_VIRT       0xfc500000
+#define MX31_ROMP_BASE_ADDR_VIRT       IOMEM(0xfc500000)
 #define MX31_ROMP_SIZE                 SZ_1M
 
 #define MX31_AVIC_BASE_ADDR            0x68000000
 #define MX31_CS3_BASE_ADDR             0xb2000000
 
 #define MX31_CS4_BASE_ADDR             0xb4000000
-#define MX31_CS4_BASE_ADDR_VIRT                0xf6000000
+#define MX31_CS4_BASE_ADDR_VIRT                IOMEM(0xf6000000)
 #define MX31_CS4_SIZE                  SZ_32M
 
 #define MX31_CS5_BASE_ADDR             0xb6000000
-#define MX31_CS5_BASE_ADDR_VIRT                0xf8000000
+#define MX31_CS5_BASE_ADDR_VIRT                IOMEM(0xf8000000)
 #define MX31_CS5_SIZE                  SZ_32M
 
 #define MX31_X_MEMC_BASE_ADDR          0xb8000000
index 1996c3e..3da78cf 100644 (file)
@@ -21,7 +21,6 @@
 #include <linux/io.h>
 #include <linux/err.h>
 #include <linux/delay.h>
-#include <linux/module.h>
 
 #include <mach/hardware.h>
 #include <mach/common.h>
@@ -29,9 +28,6 @@
 #include <asm/proc-fns.h>
 #include <asm/mach-types.h>
 
-void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL;
-EXPORT_SYMBOL_GPL(imx_ioremap);
-
 static void __iomem *wdog_base;
 
 /*
index dd36eba..d15a4a6 100644 (file)
@@ -25,6 +25,7 @@ config ARCH_OMAP2PLUS
        bool "TI OMAP2/3/4"
        select CLKDEV_LOOKUP
        select GENERIC_IRQ_CHIP
+       select SPARSE_IRQ
        select OMAP_DM_TIMER
        select USE_OF
        select PROC_DEVICETREE if PROC_FS
index 961bf85..dacaee0 100644 (file)
@@ -3,8 +3,7 @@
 #
 
 # Common support
-obj-y := common.o sram.o clock.o devices.o dma.o mux.o \
-        fb.o counter_32k.o
+obj-y := common.o sram.o clock.o dma.o fb.o counter_32k.o
 obj-m :=
 obj-n :=
 obj-  :=
index 89a3723..111315a 100644 (file)
 #include <linux/dma-mapping.h>
 
 #include <plat/common.h>
-#include <plat/board.h>
 #include <plat/vram.h>
-#include <plat/dsp.h>
+#include <linux/platform_data/dsp-omap.h>
 #include <plat/dma.h>
 
 #include <plat/omap-secure.h>
 
-
-#define NO_LENGTH_CHECK 0xffffffff
-
-struct omap_board_config_kernel *omap_board_config __initdata;
-int omap_board_config_size;
-
-static const void *__init get_config(u16 tag, size_t len,
-               int skip, size_t *len_out)
-{
-       struct omap_board_config_kernel *kinfo = NULL;
-       int i;
-
-       /* Try to find the config from the board-specific structures
-        * in the kernel. */
-       for (i = 0; i < omap_board_config_size; i++) {
-               if (omap_board_config[i].tag == tag) {
-                       if (skip == 0) {
-                               kinfo = &omap_board_config[i];
-                               break;
-                       } else {
-                               skip--;
-                       }
-               }
-       }
-       if (kinfo == NULL)
-               return NULL;
-       return kinfo->data;
-}
-
-const void *__init __omap_get_config(u16 tag, size_t len, int nr)
-{
-        return get_config(tag, len, nr, NULL);
-}
-
-const void *__init omap_get_var_config(u16 tag, size_t *len)
-{
-        return get_config(tag, NO_LENGTH_CHECK, 0, len);
-}
-
 void __init omap_reserve(void)
 {
        omap_vram_reserve_sdram_memblock();
index dbf1e03..2e826f1 100644 (file)
 #include <asm/mach/time.h>
 #include <asm/sched_clock.h>
 
-#include <plat/hardware.h>
 #include <plat/common.h>
-#include <plat/board.h>
-
 #include <plat/clock.h>
 
 /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
index caa1f7b..c7a4c09 100644 (file)
@@ -17,9 +17,6 @@
 
 #include <mach/hardware.h>
 
-#include <plat/board.h>
-
-
 /* Many OMAP development platforms reuse the same "debug board"; these
  * platforms include H2, H3, H4, and Perseus2.
  */
index 39407cb..195aaae 100644 (file)
@@ -12,6 +12,7 @@
 #include <linux/platform_device.h>
 #include <linux/leds.h>
 #include <linux/io.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
deleted file mode 100644 (file)
index 1cba927..0000000
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * linux/arch/arm/plat-omap/devices.c
- *
- * Common platform device setup/initialization for OMAP1 and OMAP2
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#include <linux/gpio.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/memblock.h>
-
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/map.h>
-#include <asm/memblock.h>
-
-#include <plat/tc.h>
-#include <plat/board.h>
-#include <plat/mmc.h>
-#include <plat/menelaus.h>
-#include <plat/omap44xx.h>
-
-/*-------------------------------------------------------------------------*/
-
-#if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE)
-
-#ifdef CONFIG_ARCH_OMAP2
-#define        OMAP_RNG_BASE           0x480A0000
-#else
-#define        OMAP_RNG_BASE           0xfffe5000
-#endif
-
-static struct resource rng_resources[] = {
-       {
-               .start          = OMAP_RNG_BASE,
-               .end            = OMAP_RNG_BASE + 0x4f,
-               .flags          = IORESOURCE_MEM,
-       },
-};
-
-static struct platform_device omap_rng_device = {
-       .name           = "omap_rng",
-       .id             = -1,
-       .num_resources  = ARRAY_SIZE(rng_resources),
-       .resource       = rng_resources,
-};
-
-static void omap_init_rng(void)
-{
-       (void) platform_device_register(&omap_rng_device);
-}
-#else
-static inline void omap_init_rng(void) {}
-#endif
-
-/*
- * This gets called after board-specific INIT_MACHINE, and initializes most
- * on-chip peripherals accessible on this board (except for few like USB):
- *
- *  (a) Does any "standard config" pin muxing needed.  Board-specific
- *     code will have muxed GPIO pins and done "nonstandard" setup;
- *     that code could live in the boot loader.
- *  (b) Populating board-specific platform_data with the data drivers
- *     rely on to handle wiring variations.
- *  (c) Creating platform devices as meaningful on this board and
- *     with this kernel configuration.
- *
- * Claiming GPIOs, and setting their direction and initial values, is the
- * responsibility of the device drivers.  So is responding to probe().
- *
- * Board-specific knowledge like creating devices or pin setup is to be
- * kept out of drivers as much as possible.  In particular, pin setup
- * may be handled by the boot loader, and drivers should expect it will
- * normally have been done by the time they're probed.
- */
-static int __init omap_init_devices(void)
-{
-       /* please keep these calls, and their implementations above,
-        * in alphabetical order so they're easier to sort through.
-        */
-       omap_init_rng();
-       return 0;
-}
-arch_initcall(omap_init_devices);
index 7fe6267..c76ed8b 100644 (file)
@@ -36,9 +36,8 @@
 #include <linux/slab.h>
 #include <linux/delay.h>
 
-#include <mach/hardware.h>
+#include <plat/cpu.h>
 #include <plat/dma.h>
-
 #include <plat/tc.h>
 
 /*
@@ -969,8 +968,7 @@ void omap_stop_dma(int lch)
                        l = p->dma_read(CCR, lch);
                }
                if (i >= 100)
-                       printk(KERN_ERR "DMA drain did not complete on "
-                                       "lch %d\n", lch);
+                       pr_err("DMA drain did not complete on lch %d\n", lch);
                /* Restore OCP_SYSCONFIG */
                p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
        } else {
@@ -1154,8 +1152,7 @@ void omap_dma_link_lch(int lch_head, int lch_queue)
 
        if ((dma_chan[lch_head].dev_id == -1) ||
            (dma_chan[lch_queue].dev_id == -1)) {
-               printk(KERN_ERR "omap_dma: trying to link "
-                      "non requested channels\n");
+               pr_err("omap_dma: trying to link non requested channels\n");
                dump_stack();
        }
 
@@ -1181,15 +1178,13 @@ void omap_dma_unlink_lch(int lch_head, int lch_queue)
 
        if (dma_chan[lch_head].next_lch != lch_queue ||
            dma_chan[lch_head].next_lch == -1) {
-               printk(KERN_ERR "omap_dma: trying to unlink "
-                      "non linked channels\n");
+               pr_err("omap_dma: trying to unlink non linked channels\n");
                dump_stack();
        }
 
        if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
            (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
-               printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
-                      "before unlinking\n");
+               pr_err("omap_dma: You need to stop the DMA channels before unlinking\n");
                dump_stack();
        }
 
@@ -1831,16 +1826,15 @@ static int omap1_dma_handle_ch(int ch)
        if ((csr & 0x3f) == 0)
                return 0;
        if (unlikely(dma_chan[ch].dev_id == -1)) {
-               printk(KERN_WARNING "Spurious interrupt from DMA channel "
-                      "%d (CSR %04x)\n", ch, csr);
+               pr_warn("Spurious interrupt from DMA channel %d (CSR %04x)\n",
+                       ch, csr);
                return 0;
        }
        if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
-               printk(KERN_WARNING "DMA timeout with device %d\n",
-                      dma_chan[ch].dev_id);
+               pr_warn("DMA timeout with device %d\n", dma_chan[ch].dev_id);
        if (unlikely(csr & OMAP_DMA_DROP_IRQ))
-               printk(KERN_WARNING "DMA synchronization event drop occurred "
-                      "with device %d\n", dma_chan[ch].dev_id);
+               pr_warn("DMA synchronization event drop occurred with device %d\n",
+                       dma_chan[ch].dev_id);
        if (likely(csr & OMAP_DMA_BLOCK_IRQ))
                dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
        if (likely(dma_chan[ch].callback != NULL))
@@ -1880,21 +1874,19 @@ static int omap2_dma_handle_ch(int ch)
 
        if (!status) {
                if (printk_ratelimit())
-                       printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
-                               ch);
+                       pr_warn("Spurious DMA IRQ for lch %d\n", ch);
                p->dma_write(1 << ch, IRQSTATUS_L0, ch);
                return 0;
        }
        if (unlikely(dma_chan[ch].dev_id == -1)) {
                if (printk_ratelimit())
-                       printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
-                                       "channel %d\n", status, ch);
+                       pr_warn("IRQ %04x for non-allocated DMA channel %d\n",
+                               status, ch);
                return 0;
        }
        if (unlikely(status & OMAP_DMA_DROP_IRQ))
-               printk(KERN_INFO
-                      "DMA synchronization event drop occurred with device "
-                      "%d\n", dma_chan[ch].dev_id);
+               pr_info("DMA synchronization event drop occurred with device %d\n",
+                       dma_chan[ch].dev_id);
        if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
                printk(KERN_INFO "DMA transaction error with device %d\n",
                       dma_chan[ch].dev_id);
@@ -2014,8 +2006,9 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
 
        p = pdev->dev.platform_data;
        if (!p) {
-               dev_err(&pdev->dev, "%s: System DMA initialized without"
-                       "platform data\n", __func__);
+               dev_err(&pdev->dev,
+                       "%s: System DMA initialized without platform data\n",
+                       __func__);
                return -EINVAL;
        }
 
@@ -2090,8 +2083,8 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
                }
                ret = setup_irq(dma_irq, &omap24xx_dma_irq);
                if (ret) {
-                       dev_err(&pdev->dev, "set_up failed for IRQ %d"
-                               "for DMA (error %d)\n", dma_irq, ret);
+                       dev_err(&pdev->dev, "set_up failed for IRQ %d for DMA (error %d)\n",
+                               dma_irq, ret);
                        goto exit_dma_lch_fail;
                }
        }
@@ -2099,8 +2092,7 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
        /* reserve dma channels 0 and 1 in high security devices */
        if (cpu_is_omap34xx() &&
                (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
-               printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
-                               "HS ROM code\n");
+               pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n");
                dma_chan[0].dev_id = 0;
                dma_chan[1].dev_id = 1;
        }
@@ -2108,8 +2100,8 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
        return 0;
 
 exit_dma_irq_fail:
-       dev_err(&pdev->dev, "unable to request IRQ %d"
-                       "for DMA (error %d)\n", dma_irq, ret);
+       dev_err(&pdev->dev, "unable to request IRQ %d for DMA (error %d)\n",
+               dma_irq, ret);
        for (irq_rel = 0; irq_rel < ch; irq_rel++) {
                dma_irq = platform_get_irq(pdev, irq_rel);
                free_irq(dma_irq, (void *)(irq_rel + 1));
index dd6f92c..bcbb9d5 100644 (file)
@@ -33,8 +33,6 @@
 #include <mach/hardware.h>
 #include <asm/mach/map.h>
 
-#include <plat/board.h>
-
 #if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE)
 
 static bool omapfb_lcd_configured;
index db071bc..6013831 100644 (file)
 #include <linux/clk.h>
 
 #include <mach/irqs.h>
-#include <plat/mux.h>
 #include <plat/i2c.h>
 #include <plat/omap-pm.h>
 #include <plat/omap_device.h>
 
 #define OMAP_I2C_SIZE          0x3f
 #define OMAP1_I2C_BASE         0xfffb3800
+#define OMAP1_INT_I2C          (32 + 4)
 
 static const char name[] = "omap_i2c";
 
@@ -105,7 +105,7 @@ static inline int omap1_i2c_add_bus(int bus_id)
        res = pdev->resource;
        res[0].start = OMAP1_I2C_BASE;
        res[0].end = res[0].start + OMAP_I2C_SIZE;
-       res[1].start = INT_I2C;
+       res[1].start = OMAP1_INT_I2C;
        pdata = &i2c_pdata[bus_id - 1];
 
        /* all OMAP1 have IP version 1 register set */
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
deleted file mode 100644 (file)
index e62f20a..0000000
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- *  arch/arm/plat-omap/include/mach/board.h
- *
- *  Information structures for board-specific data
- *
- *  Copyright (C) 2004 Nokia Corporation
- *  Written by Juha Yrjölä <juha.yrjola@nokia.com>
- */
-
-#ifndef _OMAP_BOARD_H
-#define _OMAP_BOARD_H
-
-#include <linux/types.h>
-
-#include <plat/gpio-switch.h>
-
-/*
- * OMAP35x EVM revision
- * Run time detection of EVM revision is done by reading Ethernet
- * PHY ID -
- *     GEN_1   = 0x01150000
- *     GEN_2   = 0x92200000
- */
-enum {
-       OMAP3EVM_BOARD_GEN_1 = 0,       /* EVM Rev between  A - D */
-       OMAP3EVM_BOARD_GEN_2,           /* EVM Rev >= Rev E */
-};
-
-/* Different peripheral ids */
-#define OMAP_TAG_CLOCK         0x4f01
-#define OMAP_TAG_GPIO_SWITCH   0x4f06
-#define OMAP_TAG_STI_CONSOLE   0x4f09
-#define OMAP_TAG_CAMERA_SENSOR 0x4f0a
-
-#define OMAP_TAG_BOOT_REASON    0x4f80
-#define OMAP_TAG_FLASH_PART    0x4f81
-#define OMAP_TAG_VERSION_STR   0x4f82
-
-struct omap_clock_config {
-       /* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */
-       u8 system_clock_type;
-};
-
-struct omap_serial_console_config {
-       u8 console_uart;
-       u32 console_speed;
-};
-
-struct omap_sti_console_config {
-       unsigned enable:1;
-       u8 channel;
-};
-
-struct omap_camera_sensor_config {
-       u16 reset_gpio;
-       int (*power_on)(void * data);
-       int (*power_off)(void * data);
-};
-
-struct omap_lcd_config {
-       char panel_name[16];
-       char ctrl_name[16];
-       s16  nreset_gpio;
-       u8   data_lines;
-};
-
-struct device;
-struct fb_info;
-struct omap_backlight_config {
-       int default_intensity;
-       int (*set_power)(struct device *dev, int state);
-};
-
-struct omap_fbmem_config {
-       u32 start;
-       u32 size;
-};
-
-struct omap_pwm_led_platform_data {
-       const char *name;
-       int intensity_timer;
-       int blink_timer;
-       void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off);
-};
-
-struct omap_uart_config {
-       /* Bit field of UARTs present; bit 0 --> UART1 */
-       unsigned int enabled_uarts;
-};
-
-
-struct omap_flash_part_config {
-       char part_table[0];
-};
-
-struct omap_boot_reason_config {
-       char reason_str[12];
-};
-
-struct omap_version_config {
-       char component[12];
-       char version[12];
-};
-
-struct omap_board_config_entry {
-       u16 tag;
-       u16 len;
-       u8  data[0];
-};
-
-struct omap_board_config_kernel {
-       u16 tag;
-       const void *data;
-};
-
-extern const void *__init __omap_get_config(u16 tag, size_t len, int nr);
-
-#define omap_get_config(tag, type) \
-       ((const type *) __omap_get_config((tag), sizeof(type), 0))
-#define omap_get_nr_config(tag, type, nr) \
-       ((const type *) __omap_get_config((tag), sizeof(type), (nr)))
-
-extern const void *__init omap_get_var_config(u16 tag, size_t *len);
-
-extern struct omap_board_config_kernel *omap_board_config;
-extern int omap_board_config_size;
-
-
-/* for TI reference platforms sharing the same debug card */
-extern int debug_card_init(u32 addr, unsigned gpio);
-
-/* OMAP3EVM revision */
-#if defined(CONFIG_MACH_OMAP3EVM)
-u8 get_omap3_evm_rev(void);
-#else
-#define get_omap3_evm_rev() (-EINVAL)
-#endif
-#endif
index bb5d08a..67da857 100644 (file)
@@ -30,6 +30,8 @@
 #ifndef __ASM_ARCH_OMAP_CPU_H
 #define __ASM_ARCH_OMAP_CPU_H
 
+#ifndef __ASSEMBLY__
+
 #include <linux/bitops.h>
 #include <plat/multi.h>
 
@@ -493,4 +495,5 @@ OMAP4_HAS_FEATURE(mpu_1ghz, MPU_1GHZ)
 OMAP4_HAS_FEATURE(mpu_1_2ghz, MPU_1_2GHZ)
 OMAP4_HAS_FEATURE(mpu_1_5ghz, MPU_1_5GHZ)
 
+#endif /* __ASSEMBLY__ */
 #endif
index c5811d4..0a87b05 100644 (file)
@@ -31,6 +31,8 @@
 /* Move omap4 specific defines to dma-44xx.h */
 #include "dma-44xx.h"
 
+#define INT_DMA_LCD                    25
+
 /* DMA channels for omap1 */
 #define OMAP_DMA_NO_DEVICE             0
 #define OMAP_DMA_MCSI1_TX              1
diff --git a/arch/arm/plat-omap/include/plat/gpio-switch.h b/arch/arm/plat-omap/include/plat/gpio-switch.h
deleted file mode 100644 (file)
index 10da0e0..0000000
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * GPIO switch definitions
- *
- * Copyright (C) 2006 Nokia Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_OMAP_GPIO_SWITCH_H
-#define __ASM_ARCH_OMAP_GPIO_SWITCH_H
-
-#include <linux/types.h>
-
-/* Cover:
- *     high -> closed
- *     low  -> open
- * Connection:
- *     high -> connected
- *     low  -> disconnected
- * Activity:
- *     high -> active
- *     low  -> inactive
- *
- */
-#define OMAP_GPIO_SWITCH_TYPE_COVER            0x0000
-#define OMAP_GPIO_SWITCH_TYPE_CONNECTION       0x0001
-#define OMAP_GPIO_SWITCH_TYPE_ACTIVITY         0x0002
-#define OMAP_GPIO_SWITCH_FLAG_INVERTED         0x0001
-#define OMAP_GPIO_SWITCH_FLAG_OUTPUT           0x0002
-
-struct omap_gpio_switch {
-       const char *name;
-       s16 gpio;
-       unsigned flags:4;
-       unsigned type:4;
-
-       /* Time in ms to debounce when transitioning from
-        * inactive state to active state. */
-       u16 debounce_rising;
-       /* Same for transition from active to inactive state. */
-       u16 debounce_falling;
-
-       /* notify board-specific code about state changes */
-       void (* notify)(void *data, int state);
-       void *notify_data;
-};
-
-/* Call at init time only */
-extern void omap_register_gpio_switches(const struct omap_gpio_switch *tbl,
-                                       int count);
-
-#endif
index f37764a..2e6e259 100644 (file)
@@ -133,6 +133,25 @@ struct gpmc_timings {
        u16 wr_data_mux_bus;    /* WRDATAONADMUXBUS */
 };
 
+struct gpmc_nand_regs {
+       void __iomem    *gpmc_status;
+       void __iomem    *gpmc_nand_command;
+       void __iomem    *gpmc_nand_address;
+       void __iomem    *gpmc_nand_data;
+       void __iomem    *gpmc_prefetch_config1;
+       void __iomem    *gpmc_prefetch_config2;
+       void __iomem    *gpmc_prefetch_control;
+       void __iomem    *gpmc_prefetch_status;
+       void __iomem    *gpmc_ecc_config;
+       void __iomem    *gpmc_ecc_control;
+       void __iomem    *gpmc_ecc_size_config;
+       void __iomem    *gpmc_ecc1_result;
+       void __iomem    *gpmc_bch_result0;
+};
+
+extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
+extern int gpmc_get_client_irq(unsigned irq_config);
+
 extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
 extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps);
 extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
deleted file mode 100644 (file)
index ddbde38..0000000
+++ /dev/null
@@ -1,293 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/hardware.h
- *
- * Hardware definitions for TI OMAP processors and boards
- *
- * NOTE: Please put device driver specific defines into a separate header
- *      file for each driver.
- *
- * Copyright (C) 2001 RidgeRun, Inc.
- * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
- *
- * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
- *                          and Dirk Behme <dirk.behme@de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP_HARDWARE_H
-#define __ASM_ARCH_OMAP_HARDWARE_H
-
-#include <asm/sizes.h>
-#ifndef __ASSEMBLER__
-#include <asm/types.h>
-#include <plat/cpu.h>
-#endif
-#include <plat/serial.h>
-
-/*
- * ---------------------------------------------------------------------------
- * Common definitions for all OMAP processors
- * NOTE: Put all processor or board specific parts to the special header
- *      files.
- * ---------------------------------------------------------------------------
- */
-
-/*
- * ----------------------------------------------------------------------------
- * Timers
- * ----------------------------------------------------------------------------
- */
-#define OMAP_MPU_TIMER1_BASE   (0xfffec500)
-#define OMAP_MPU_TIMER2_BASE   (0xfffec600)
-#define OMAP_MPU_TIMER3_BASE   (0xfffec700)
-#define MPU_TIMER_FREE         (1 << 6)
-#define MPU_TIMER_CLOCK_ENABLE (1 << 5)
-#define MPU_TIMER_AR           (1 << 1)
-#define MPU_TIMER_ST           (1 << 0)
-
-/*
- * ----------------------------------------------------------------------------
- * Clocks
- * ----------------------------------------------------------------------------
- */
-#define CLKGEN_REG_BASE                (0xfffece00)
-#define ARM_CKCTL              (CLKGEN_REG_BASE + 0x0)
-#define ARM_IDLECT1            (CLKGEN_REG_BASE + 0x4)
-#define ARM_IDLECT2            (CLKGEN_REG_BASE + 0x8)
-#define ARM_EWUPCT             (CLKGEN_REG_BASE + 0xC)
-#define ARM_RSTCT1             (CLKGEN_REG_BASE + 0x10)
-#define ARM_RSTCT2             (CLKGEN_REG_BASE + 0x14)
-#define ARM_SYSST              (CLKGEN_REG_BASE + 0x18)
-#define ARM_IDLECT3            (CLKGEN_REG_BASE + 0x24)
-
-#define CK_RATEF               1
-#define CK_IDLEF               2
-#define CK_ENABLEF             4
-#define CK_SELECTF             8
-#define SETARM_IDLE_SHIFT
-
-/* DPLL control registers */
-#define DPLL_CTL               (0xfffecf00)
-
-/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
-#define DSP_CONFIG_REG_BASE     IOMEM(0xe1008000)
-#define DSP_CKCTL              (DSP_CONFIG_REG_BASE + 0x0)
-#define DSP_IDLECT1            (DSP_CONFIG_REG_BASE + 0x4)
-#define DSP_IDLECT2            (DSP_CONFIG_REG_BASE + 0x8)
-#define DSP_RSTCT2             (DSP_CONFIG_REG_BASE + 0x14)
-
-/*
- * ---------------------------------------------------------------------------
- * UPLD
- * ---------------------------------------------------------------------------
- */
-#define ULPD_REG_BASE          (0xfffe0800)
-#define ULPD_IT_STATUS         (ULPD_REG_BASE + 0x14)
-#define ULPD_SETUP_ANALOG_CELL_3       (ULPD_REG_BASE + 0x24)
-#define ULPD_CLOCK_CTRL                (ULPD_REG_BASE + 0x30)
-#      define DIS_USB_PVCI_CLK         (1 << 5)        /* no USB/FAC synch */
-#      define USB_MCLK_EN              (1 << 4)        /* enable W4_USB_CLKO */
-#define ULPD_SOFT_REQ          (ULPD_REG_BASE + 0x34)
-#      define SOFT_UDC_REQ             (1 << 4)
-#      define SOFT_USB_CLK_REQ         (1 << 3)
-#      define SOFT_DPLL_REQ            (1 << 0)
-#define ULPD_DPLL_CTRL         (ULPD_REG_BASE + 0x3c)
-#define ULPD_STATUS_REQ                (ULPD_REG_BASE + 0x40)
-#define ULPD_APLL_CTRL         (ULPD_REG_BASE + 0x4c)
-#define ULPD_POWER_CTRL                (ULPD_REG_BASE + 0x50)
-#define ULPD_SOFT_DISABLE_REQ_REG      (ULPD_REG_BASE + 0x68)
-#      define DIS_MMC2_DPLL_REQ        (1 << 11)
-#      define DIS_MMC1_DPLL_REQ        (1 << 10)
-#      define DIS_UART3_DPLL_REQ       (1 << 9)
-#      define DIS_UART2_DPLL_REQ       (1 << 8)
-#      define DIS_UART1_DPLL_REQ       (1 << 7)
-#      define DIS_USB_HOST_DPLL_REQ    (1 << 6)
-#define ULPD_SDW_CLK_DIV_CTRL_SEL      (ULPD_REG_BASE + 0x74)
-#define ULPD_CAM_CLK_CTRL      (ULPD_REG_BASE + 0x7c)
-
-/*
- * ---------------------------------------------------------------------------
- * Watchdog timer
- * ---------------------------------------------------------------------------
- */
-
-/* Watchdog timer within the OMAP3.2 gigacell */
-#define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
-#define OMAP_WDT_TIMER         (OMAP_MPU_WATCHDOG_BASE + 0x0)
-#define OMAP_WDT_LOAD_TIM      (OMAP_MPU_WATCHDOG_BASE + 0x4)
-#define OMAP_WDT_READ_TIM      (OMAP_MPU_WATCHDOG_BASE + 0x4)
-#define OMAP_WDT_TIMER_MODE    (OMAP_MPU_WATCHDOG_BASE + 0x8)
-
-/*
- * ---------------------------------------------------------------------------
- * Interrupts
- * ---------------------------------------------------------------------------
- */
-#ifdef CONFIG_ARCH_OMAP1
-
-/*
- * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
- * or something similar.. -- PFM.
- */
-
-#define OMAP_IH1_BASE          0xfffecb00
-#define OMAP_IH2_BASE          0xfffe0000
-
-#define OMAP_IH1_ITR           (OMAP_IH1_BASE + 0x00)
-#define OMAP_IH1_MIR           (OMAP_IH1_BASE + 0x04)
-#define OMAP_IH1_SIR_IRQ       (OMAP_IH1_BASE + 0x10)
-#define OMAP_IH1_SIR_FIQ       (OMAP_IH1_BASE + 0x14)
-#define OMAP_IH1_CONTROL       (OMAP_IH1_BASE + 0x18)
-#define OMAP_IH1_ILR0          (OMAP_IH1_BASE + 0x1c)
-#define OMAP_IH1_ISR           (OMAP_IH1_BASE + 0x9c)
-
-#define OMAP_IH2_ITR           (OMAP_IH2_BASE + 0x00)
-#define OMAP_IH2_MIR           (OMAP_IH2_BASE + 0x04)
-#define OMAP_IH2_SIR_IRQ       (OMAP_IH2_BASE + 0x10)
-#define OMAP_IH2_SIR_FIQ       (OMAP_IH2_BASE + 0x14)
-#define OMAP_IH2_CONTROL       (OMAP_IH2_BASE + 0x18)
-#define OMAP_IH2_ILR0          (OMAP_IH2_BASE + 0x1c)
-#define OMAP_IH2_ISR           (OMAP_IH2_BASE + 0x9c)
-
-#define IRQ_ITR_REG_OFFSET     0x00
-#define IRQ_MIR_REG_OFFSET     0x04
-#define IRQ_SIR_IRQ_REG_OFFSET 0x10
-#define IRQ_SIR_FIQ_REG_OFFSET 0x14
-#define IRQ_CONTROL_REG_OFFSET 0x18
-#define IRQ_ISR_REG_OFFSET     0x9c
-#define IRQ_ILR0_REG_OFFSET    0x1c
-#define IRQ_GMR_REG_OFFSET     0xa0
-
-#endif
-
-/*
- * ----------------------------------------------------------------------------
- * System control registers
- * ----------------------------------------------------------------------------
- */
-#define MOD_CONF_CTRL_0                0xfffe1080
-#define MOD_CONF_CTRL_1                0xfffe1110
-
-/*
- * ----------------------------------------------------------------------------
- * Pin multiplexing registers
- * ----------------------------------------------------------------------------
- */
-#define FUNC_MUX_CTRL_0                0xfffe1000
-#define FUNC_MUX_CTRL_1                0xfffe1004
-#define FUNC_MUX_CTRL_2                0xfffe1008
-#define COMP_MODE_CTRL_0       0xfffe100c
-#define FUNC_MUX_CTRL_3                0xfffe1010
-#define FUNC_MUX_CTRL_4                0xfffe1014
-#define FUNC_MUX_CTRL_5                0xfffe1018
-#define FUNC_MUX_CTRL_6                0xfffe101C
-#define FUNC_MUX_CTRL_7                0xfffe1020
-#define FUNC_MUX_CTRL_8                0xfffe1024
-#define FUNC_MUX_CTRL_9                0xfffe1028
-#define FUNC_MUX_CTRL_A                0xfffe102C
-#define FUNC_MUX_CTRL_B                0xfffe1030
-#define FUNC_MUX_CTRL_C                0xfffe1034
-#define FUNC_MUX_CTRL_D                0xfffe1038
-#define PULL_DWN_CTRL_0                0xfffe1040
-#define PULL_DWN_CTRL_1                0xfffe1044
-#define PULL_DWN_CTRL_2                0xfffe1048
-#define PULL_DWN_CTRL_3                0xfffe104c
-#define PULL_DWN_CTRL_4                0xfffe10ac
-
-/* OMAP-1610 specific multiplexing registers */
-#define FUNC_MUX_CTRL_E                0xfffe1090
-#define FUNC_MUX_CTRL_F                0xfffe1094
-#define FUNC_MUX_CTRL_10       0xfffe1098
-#define FUNC_MUX_CTRL_11       0xfffe109c
-#define FUNC_MUX_CTRL_12       0xfffe10a0
-#define PU_PD_SEL_0            0xfffe10b4
-#define PU_PD_SEL_1            0xfffe10b8
-#define PU_PD_SEL_2            0xfffe10bc
-#define PU_PD_SEL_3            0xfffe10c0
-#define PU_PD_SEL_4            0xfffe10c4
-
-/* Timer32K for 1610 and 1710*/
-#define OMAP_TIMER32K_BASE     0xFFFBC400
-
-/*
- * ---------------------------------------------------------------------------
- * TIPB bus interface
- * ---------------------------------------------------------------------------
- */
-#define TIPB_PUBLIC_CNTL_BASE          0xfffed300
-#define MPU_PUBLIC_TIPB_CNTL           (TIPB_PUBLIC_CNTL_BASE + 0x8)
-#define TIPB_PRIVATE_CNTL_BASE         0xfffeca00
-#define MPU_PRIVATE_TIPB_CNTL          (TIPB_PRIVATE_CNTL_BASE + 0x8)
-
-/*
- * ----------------------------------------------------------------------------
- * MPUI interface
- * ----------------------------------------------------------------------------
- */
-#define MPUI_BASE                      (0xfffec900)
-#define MPUI_CTRL                      (MPUI_BASE + 0x0)
-#define MPUI_DEBUG_ADDR                        (MPUI_BASE + 0x4)
-#define MPUI_DEBUG_DATA                        (MPUI_BASE + 0x8)
-#define MPUI_DEBUG_FLAG                        (MPUI_BASE + 0xc)
-#define MPUI_STATUS_REG                        (MPUI_BASE + 0x10)
-#define MPUI_DSP_STATUS                        (MPUI_BASE + 0x14)
-#define MPUI_DSP_BOOT_CONFIG           (MPUI_BASE + 0x18)
-#define MPUI_DSP_API_CONFIG            (MPUI_BASE + 0x1c)
-
-/*
- * ----------------------------------------------------------------------------
- * LED Pulse Generator
- * ----------------------------------------------------------------------------
- */
-#define OMAP_LPG1_BASE                 0xfffbd000
-#define OMAP_LPG2_BASE                 0xfffbd800
-#define OMAP_LPG1_LCR                  (OMAP_LPG1_BASE + 0x00)
-#define OMAP_LPG1_PMR                  (OMAP_LPG1_BASE + 0x04)
-#define OMAP_LPG2_LCR                  (OMAP_LPG2_BASE + 0x00)
-#define OMAP_LPG2_PMR                  (OMAP_LPG2_BASE + 0x04)
-
-/*
- * ----------------------------------------------------------------------------
- * Pulse-Width Light
- * ----------------------------------------------------------------------------
- */
-#define OMAP_PWL_BASE                  0xfffb5800
-#define OMAP_PWL_ENABLE                        (OMAP_PWL_BASE + 0x00)
-#define OMAP_PWL_CLK_ENABLE            (OMAP_PWL_BASE + 0x04)
-
-/*
- * ---------------------------------------------------------------------------
- * Processor specific defines
- * ---------------------------------------------------------------------------
- */
-
-#include <plat/omap7xx.h>
-#include <plat/omap1510.h>
-#include <plat/omap16xx.h>
-#include <plat/omap24xx.h>
-#include <plat/omap34xx.h>
-#include <plat/omap44xx.h>
-#include <plat/ti81xx.h>
-#include <plat/am33xx.h>
-#include <plat/omap54xx.h>
-
-#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/plat/irqs-44xx.h b/arch/arm/plat-omap/include/plat/irqs-44xx.h
deleted file mode 100644 (file)
index 518322c..0000000
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * OMAP4 Interrupt lines definitions
- *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
- *
- * Santosh Shilimkar (santosh.shilimkar@ti.com)
- * Benoit Cousson (b-cousson@ti.com)
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H
-#define __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H
-
-/* OMAP44XX IRQs numbers definitions */
-#define OMAP44XX_IRQ_LOCALTIMER                        29
-#define OMAP44XX_IRQ_LOCALWDT                  30
-
-#define OMAP44XX_IRQ_GIC_START                 32
-
-#define OMAP44XX_IRQ_PL310                     (0 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CTI0                      (1 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CTI1                      (2 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_ELM                       (4 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SYS_1N                    (7 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SECURITY_EVENTS           (8 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_L3_DBG                    (9 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_L3_APP                    (10 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_PRCM                      (11 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SDMA_0                    (12 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SDMA_1                    (13 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SDMA_2                    (14 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SDMA_3                    (15 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCBSP4                    (16 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCBSP1                    (17 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SR_MCU                    (18 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SR_CORE                   (19 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPMC                      (20 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GFX                       (21 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCBSP2                    (22 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCBSP3                    (23 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_ISS_5                     (24 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DSS_DISPC                 (25 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MAIL_U0                   (26 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_C2C_SSCM_0                        (27 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_TESLA_MMU                 (28 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO1                     (29 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO2                     (30 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO3                     (31 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO4                     (32 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO5                     (33 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO6                     (34 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_USIM                      (35 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_WDT3                      (36 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT1                      (37 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT2                      (38 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT3                      (39 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT4                      (40 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT5                      (41 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT6                      (42 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT7                      (43 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT8                      (44 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT9                      (45 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT10                     (46 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT11                     (47 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SPI4                      (48 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SHA1_S                    (49 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_FPKA_SINTREQUEST_S                (50 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SHA1_P                    (51 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_RNG                       (52 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DSS_DSI1                  (53 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_I2C1                      (56 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_I2C2                      (57 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HDQ                       (58 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MMC5                      (59 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_I2C3                      (61 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_I2C4                      (62 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_AES2_S                    (63 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_AES2_P                    (64 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SPI1                      (65 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SPI2                      (66 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HSI_P1                    (67 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HSI_P2                    (68 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_FDIF_3                    (69 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_UART4                     (70 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HSI_DMA                   (71 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_UART1                     (72 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_UART2                     (73 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_UART3                     (74 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_PBIAS                     (75 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_OHCI                      (76 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_EHCI                      (77 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_TLL                       (78 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_AES1_S                    (79 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_WDT2                      (80 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DES_S                     (81 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DES_P                     (82 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MMC1                      (83 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DSS_DSI2                  (84 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_AES1_P                    (85 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MMC2                      (86 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MPU_ICR                   (87 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_C2C_SSCM_1                        (88 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_FSUSB                     (89 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_FSUSB_SMI                 (90 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SPI3                      (91 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HS_USB_MC_N               (92 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HS_USB_DMA_N              (93 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MMC3                      (94 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT12                     (95 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MMC4                      (96 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SLIMBUS1                  (97 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SLIMBUS2                  (98 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_ABE                       (99 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DUCATI_MMU                        (100 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DSS_HDMI                  (101 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SR_IVA                    (102 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_1    (103 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_0    (104 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_IVA_HD_POMBINTRPEND_0     (107 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCASP1_AR                 (108 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCASP1_AX                 (109 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_EMIF4_1                   (110 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_EMIF4_2                   (111 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCPDM                     (112 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DMM                       (113 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DMIC                      (114 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CDMA_0                    (115 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CDMA_1                    (116 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CDMA_2                    (117 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CDMA_3                    (118 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SYS_2N                    (119 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_KBD_CTL                   (120 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_UNIPRO1                   (124 + OMAP44XX_IRQ_GIC_START)
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
deleted file mode 100644 (file)
index 37bbbbb..0000000
+++ /dev/null
@@ -1,453 +0,0 @@
-/*
- *  arch/arm/plat-omap/include/mach/irqs.h
- *
- *  Copyright (C) Greg Lonnon 2001
- *  Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
- *
- * Copyright (C) 2009 Texas Instruments
- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
- *      are different.
- */
-
-#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
-#define __ASM_ARCH_OMAP15XX_IRQS_H
-
-/* All OMAP4 specific defines are moved to irqs-44xx.h */
-#include "irqs-44xx.h"
-
-/*
- * IRQ numbers for interrupt handler 1
- *
- * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
- *
- */
-#define INT_CAMERA             1
-#define INT_FIQ                        3
-#define INT_RTDX               6
-#define INT_DSP_MMU_ABORT      7
-#define INT_HOST               8
-#define INT_ABORT              9
-#define INT_BRIDGE_PRIV                13
-#define INT_GPIO_BANK1         14
-#define INT_UART3              15
-#define INT_TIMER3             16
-#define INT_DMA_CH0_6          19
-#define INT_DMA_CH1_7          20
-#define INT_DMA_CH2_8          21
-#define INT_DMA_CH3            22
-#define INT_DMA_CH4            23
-#define INT_DMA_CH5            24
-#define INT_DMA_LCD            25
-#define INT_TIMER1             26
-#define INT_WD_TIMER           27
-#define INT_BRIDGE_PUB         28
-#define INT_TIMER2             30
-#define INT_LCD_CTRL           31
-
-/*
- * OMAP-1510 specific IRQ numbers for interrupt handler 1
- */
-#define INT_1510_IH2_IRQ       0
-#define INT_1510_RES2          2
-#define INT_1510_SPI_TX                4
-#define INT_1510_SPI_RX                5
-#define INT_1510_DSP_MAILBOX1  10
-#define INT_1510_DSP_MAILBOX2  11
-#define INT_1510_RES12         12
-#define INT_1510_LB_MMU                17
-#define INT_1510_RES18         18
-#define INT_1510_LOCAL_BUS     29
-
-/*
- * OMAP-1610 specific IRQ numbers for interrupt handler 1
- */
-#define INT_1610_IH2_IRQ       INT_1510_IH2_IRQ
-#define INT_1610_IH2_FIQ       2
-#define INT_1610_McBSP2_TX     4
-#define INT_1610_McBSP2_RX     5
-#define INT_1610_DSP_MAILBOX1  10
-#define INT_1610_DSP_MAILBOX2  11
-#define INT_1610_LCD_LINE      12
-#define INT_1610_GPTIMER1      17
-#define INT_1610_GPTIMER2      18
-#define INT_1610_SSR_FIFO_0    29
-
-/*
- * OMAP-7xx specific IRQ numbers for interrupt handler 1
- */
-#define INT_7XX_IH2_FIQ                0
-#define INT_7XX_IH2_IRQ                1
-#define INT_7XX_USB_NON_ISO    2
-#define INT_7XX_USB_ISO                3
-#define INT_7XX_ICR            4
-#define INT_7XX_EAC            5
-#define INT_7XX_GPIO_BANK1     6
-#define INT_7XX_GPIO_BANK2     7
-#define INT_7XX_GPIO_BANK3     8
-#define INT_7XX_McBSP2TX       10
-#define INT_7XX_McBSP2RX       11
-#define INT_7XX_McBSP2RX_OVF   12
-#define INT_7XX_LCD_LINE       14
-#define INT_7XX_GSM_PROTECT    15
-#define INT_7XX_TIMER3         16
-#define INT_7XX_GPIO_BANK5     17
-#define INT_7XX_GPIO_BANK6     18
-#define INT_7XX_SPGIO_WR       29
-
-/*
- * IRQ numbers for interrupt handler 2
- *
- * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
- */
-#define IH2_BASE               32
-
-#define INT_KEYBOARD           (1 + IH2_BASE)
-#define INT_uWireTX            (2 + IH2_BASE)
-#define INT_uWireRX            (3 + IH2_BASE)
-#define INT_I2C                        (4 + IH2_BASE)
-#define INT_MPUIO              (5 + IH2_BASE)
-#define INT_USB_HHC_1          (6 + IH2_BASE)
-#define INT_McBSP3TX           (10 + IH2_BASE)
-#define INT_McBSP3RX           (11 + IH2_BASE)
-#define INT_McBSP1TX           (12 + IH2_BASE)
-#define INT_McBSP1RX           (13 + IH2_BASE)
-#define INT_UART1              (14 + IH2_BASE)
-#define INT_UART2              (15 + IH2_BASE)
-#define INT_BT_MCSI1TX         (16 + IH2_BASE)
-#define INT_BT_MCSI1RX         (17 + IH2_BASE)
-#define INT_SOSSI_MATCH                (19 + IH2_BASE)
-#define INT_USB_W2FC           (20 + IH2_BASE)
-#define INT_1WIRE              (21 + IH2_BASE)
-#define INT_OS_TIMER           (22 + IH2_BASE)
-#define INT_MMC                        (23 + IH2_BASE)
-#define INT_GAUGE_32K          (24 + IH2_BASE)
-#define INT_RTC_TIMER          (25 + IH2_BASE)
-#define INT_RTC_ALARM          (26 + IH2_BASE)
-#define INT_MEM_STICK          (27 + IH2_BASE)
-
-/*
- * OMAP-1510 specific IRQ numbers for interrupt handler 2
- */
-#define INT_1510_DSP_MMU       (28 + IH2_BASE)
-#define INT_1510_COM_SPI_RO    (31 + IH2_BASE)
-
-/*
- * OMAP-1610 specific IRQ numbers for interrupt handler 2
- */
-#define INT_1610_FAC           (0 + IH2_BASE)
-#define INT_1610_USB_HHC_2     (7 + IH2_BASE)
-#define INT_1610_USB_OTG       (8 + IH2_BASE)
-#define INT_1610_SoSSI         (9 + IH2_BASE)
-#define INT_1610_SoSSI_MATCH   (19 + IH2_BASE)
-#define INT_1610_DSP_MMU       (28 + IH2_BASE)
-#define INT_1610_McBSP2RX_OF   (31 + IH2_BASE)
-#define INT_1610_STI           (32 + IH2_BASE)
-#define INT_1610_STI_WAKEUP    (33 + IH2_BASE)
-#define INT_1610_GPTIMER3      (34 + IH2_BASE)
-#define INT_1610_GPTIMER4      (35 + IH2_BASE)
-#define INT_1610_GPTIMER5      (36 + IH2_BASE)
-#define INT_1610_GPTIMER6      (37 + IH2_BASE)
-#define INT_1610_GPTIMER7      (38 + IH2_BASE)
-#define INT_1610_GPTIMER8      (39 + IH2_BASE)
-#define INT_1610_GPIO_BANK2    (40 + IH2_BASE)
-#define INT_1610_GPIO_BANK3    (41 + IH2_BASE)
-#define INT_1610_MMC2          (42 + IH2_BASE)
-#define INT_1610_CF            (43 + IH2_BASE)
-#define INT_1610_WAKE_UP_REQ   (46 + IH2_BASE)
-#define INT_1610_GPIO_BANK4    (48 + IH2_BASE)
-#define INT_1610_SPI           (49 + IH2_BASE)
-#define INT_1610_DMA_CH6       (53 + IH2_BASE)
-#define INT_1610_DMA_CH7       (54 + IH2_BASE)
-#define INT_1610_DMA_CH8       (55 + IH2_BASE)
-#define INT_1610_DMA_CH9       (56 + IH2_BASE)
-#define INT_1610_DMA_CH10      (57 + IH2_BASE)
-#define INT_1610_DMA_CH11      (58 + IH2_BASE)
-#define INT_1610_DMA_CH12      (59 + IH2_BASE)
-#define INT_1610_DMA_CH13      (60 + IH2_BASE)
-#define INT_1610_DMA_CH14      (61 + IH2_BASE)
-#define INT_1610_DMA_CH15      (62 + IH2_BASE)
-#define INT_1610_NAND          (63 + IH2_BASE)
-#define INT_1610_SHA1MD5       (91 + IH2_BASE)
-
-/*
- * OMAP-7xx specific IRQ numbers for interrupt handler 2
- */
-#define INT_7XX_HW_ERRORS      (0 + IH2_BASE)
-#define INT_7XX_NFIQ_PWR_FAIL  (1 + IH2_BASE)
-#define INT_7XX_CFCD           (2 + IH2_BASE)
-#define INT_7XX_CFIREQ         (3 + IH2_BASE)
-#define INT_7XX_I2C            (4 + IH2_BASE)
-#define INT_7XX_PCC            (5 + IH2_BASE)
-#define INT_7XX_MPU_EXT_NIRQ   (6 + IH2_BASE)
-#define INT_7XX_SPI_100K_1     (7 + IH2_BASE)
-#define INT_7XX_SYREN_SPI      (8 + IH2_BASE)
-#define INT_7XX_VLYNQ          (9 + IH2_BASE)
-#define INT_7XX_GPIO_BANK4     (10 + IH2_BASE)
-#define INT_7XX_McBSP1TX       (11 + IH2_BASE)
-#define INT_7XX_McBSP1RX       (12 + IH2_BASE)
-#define INT_7XX_McBSP1RX_OF    (13 + IH2_BASE)
-#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
-#define INT_7XX_UART_MODEM_1   (15 + IH2_BASE)
-#define INT_7XX_MCSI           (16 + IH2_BASE)
-#define INT_7XX_uWireTX                (17 + IH2_BASE)
-#define INT_7XX_uWireRX                (18 + IH2_BASE)
-#define INT_7XX_SMC_CD         (19 + IH2_BASE)
-#define INT_7XX_SMC_IREQ       (20 + IH2_BASE)
-#define INT_7XX_HDQ_1WIRE      (21 + IH2_BASE)
-#define INT_7XX_TIMER32K       (22 + IH2_BASE)
-#define INT_7XX_MMC_SDIO       (23 + IH2_BASE)
-#define INT_7XX_UPLD           (24 + IH2_BASE)
-#define INT_7XX_USB_HHC_1      (27 + IH2_BASE)
-#define INT_7XX_USB_HHC_2      (28 + IH2_BASE)
-#define INT_7XX_USB_GENI       (29 + IH2_BASE)
-#define INT_7XX_USB_OTG                (30 + IH2_BASE)
-#define INT_7XX_CAMERA_IF      (31 + IH2_BASE)
-#define INT_7XX_RNG            (32 + IH2_BASE)
-#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
-#define INT_7XX_DBB_RF_EN      (34 + IH2_BASE)
-#define INT_7XX_MPUIO_KEYPAD   (35 + IH2_BASE)
-#define INT_7XX_SHA1_MD5       (36 + IH2_BASE)
-#define INT_7XX_SPI_100K_2     (37 + IH2_BASE)
-#define INT_7XX_RNG_IDLE       (38 + IH2_BASE)
-#define INT_7XX_MPUIO          (39 + IH2_BASE)
-#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF       (40 + IH2_BASE)
-#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
-#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE)
-#define INT_7XX_LLPC_VSYNC     (43 + IH2_BASE)
-#define INT_7XX_WAKE_UP_REQ    (46 + IH2_BASE)
-#define INT_7XX_DMA_CH6                (53 + IH2_BASE)
-#define INT_7XX_DMA_CH7                (54 + IH2_BASE)
-#define INT_7XX_DMA_CH8                (55 + IH2_BASE)
-#define INT_7XX_DMA_CH9                (56 + IH2_BASE)
-#define INT_7XX_DMA_CH10       (57 + IH2_BASE)
-#define INT_7XX_DMA_CH11       (58 + IH2_BASE)
-#define INT_7XX_DMA_CH12       (59 + IH2_BASE)
-#define INT_7XX_DMA_CH13       (60 + IH2_BASE)
-#define INT_7XX_DMA_CH14       (61 + IH2_BASE)
-#define INT_7XX_DMA_CH15       (62 + IH2_BASE)
-#define INT_7XX_NAND           (63 + IH2_BASE)
-
-#define INT_24XX_SYS_NIRQ      7
-#define INT_24XX_SDMA_IRQ0     12
-#define INT_24XX_SDMA_IRQ1     13
-#define INT_24XX_SDMA_IRQ2     14
-#define INT_24XX_SDMA_IRQ3     15
-#define INT_24XX_CAM_IRQ       24
-#define INT_24XX_DSS_IRQ       25
-#define INT_24XX_MAIL_U0_MPU   26
-#define INT_24XX_DSP_UMA       27
-#define INT_24XX_DSP_MMU       28
-#define INT_24XX_GPIO_BANK1    29
-#define INT_24XX_GPIO_BANK2    30
-#define INT_24XX_GPIO_BANK3    31
-#define INT_24XX_GPIO_BANK4    32
-#define INT_24XX_GPIO_BANK5    33
-#define INT_24XX_MAIL_U3_MPU   34
-#define INT_24XX_GPTIMER1      37
-#define INT_24XX_GPTIMER2      38
-#define INT_24XX_GPTIMER3      39
-#define INT_24XX_GPTIMER4      40
-#define INT_24XX_GPTIMER5      41
-#define INT_24XX_GPTIMER6      42
-#define INT_24XX_GPTIMER7      43
-#define INT_24XX_GPTIMER8      44
-#define INT_24XX_GPTIMER9      45
-#define INT_24XX_GPTIMER10     46
-#define INT_24XX_GPTIMER11     47
-#define INT_24XX_GPTIMER12     48
-#define INT_24XX_SHA1MD5       51
-#define INT_24XX_MCBSP4_IRQ_TX 54
-#define INT_24XX_MCBSP4_IRQ_RX 55
-#define INT_24XX_I2C1_IRQ      56
-#define INT_24XX_I2C2_IRQ      57
-#define INT_24XX_HDQ_IRQ       58
-#define INT_24XX_MCBSP1_IRQ_TX 59
-#define INT_24XX_MCBSP1_IRQ_RX 60
-#define INT_24XX_MCBSP2_IRQ_TX 62
-#define INT_24XX_MCBSP2_IRQ_RX 63
-#define INT_24XX_SPI1_IRQ      65
-#define INT_24XX_SPI2_IRQ      66
-#define INT_24XX_UART1_IRQ     72
-#define INT_24XX_UART2_IRQ     73
-#define INT_24XX_UART3_IRQ     74
-#define INT_24XX_USB_IRQ_GEN   75
-#define INT_24XX_USB_IRQ_NISO  76
-#define INT_24XX_USB_IRQ_ISO   77
-#define INT_24XX_USB_IRQ_HGEN  78
-#define INT_24XX_USB_IRQ_HSOF  79
-#define INT_24XX_USB_IRQ_OTG   80
-#define INT_24XX_MCBSP5_IRQ_TX 81
-#define INT_24XX_MCBSP5_IRQ_RX 82
-#define INT_24XX_MMC_IRQ       83
-#define INT_24XX_MMC2_IRQ      86
-#define INT_24XX_MCBSP3_IRQ_TX 89
-#define INT_24XX_MCBSP3_IRQ_RX 90
-#define INT_24XX_SPI3_IRQ      91
-
-#define INT_243X_MCBSP2_IRQ    16
-#define INT_243X_MCBSP3_IRQ    17
-#define INT_243X_MCBSP4_IRQ    18
-#define INT_243X_MCBSP5_IRQ    19
-#define INT_243X_MCBSP1_IRQ    64
-#define INT_243X_HS_USB_MC     92
-#define INT_243X_HS_USB_DMA    93
-#define INT_243X_CARKIT_IRQ    94
-
-#define INT_34XX_BENCH_MPU_EMUL        3
-#define INT_34XX_ST_MCBSP2_IRQ 4
-#define INT_34XX_ST_MCBSP3_IRQ 5
-#define INT_34XX_SSM_ABORT_IRQ 6
-#define INT_34XX_SYS_NIRQ      7
-#define INT_34XX_D2D_FW_IRQ    8
-#define INT_34XX_L3_DBG_IRQ     9
-#define INT_34XX_L3_APP_IRQ     10
-#define INT_34XX_PRCM_MPU_IRQ  11
-#define INT_34XX_MCBSP1_IRQ    16
-#define INT_34XX_MCBSP2_IRQ    17
-#define INT_34XX_GPMC_IRQ      20
-#define INT_34XX_MCBSP3_IRQ    22
-#define INT_34XX_MCBSP4_IRQ    23
-#define INT_34XX_CAM_IRQ       24
-#define INT_34XX_MCBSP5_IRQ    27
-#define INT_34XX_GPIO_BANK1    29
-#define INT_34XX_GPIO_BANK2    30
-#define INT_34XX_GPIO_BANK3    31
-#define INT_34XX_GPIO_BANK4    32
-#define INT_34XX_GPIO_BANK5    33
-#define INT_34XX_GPIO_BANK6    34
-#define INT_34XX_USIM_IRQ      35
-#define INT_34XX_WDT3_IRQ      36
-#define INT_34XX_SPI4_IRQ      48
-#define INT_34XX_SHA1MD52_IRQ  49
-#define INT_34XX_FPKA_READY_IRQ        50
-#define INT_34XX_SHA1MD51_IRQ  51
-#define INT_34XX_RNG_IRQ       52
-#define INT_34XX_I2C3_IRQ      61
-#define INT_34XX_FPKA_ERROR_IRQ        64
-#define INT_34XX_PBIAS_IRQ     75
-#define INT_34XX_OHCI_IRQ      76
-#define INT_34XX_EHCI_IRQ      77
-#define INT_34XX_TLL_IRQ       78
-#define INT_34XX_PARTHASH_IRQ  79
-#define INT_34XX_MMC3_IRQ      94
-#define INT_34XX_GPT12_IRQ     95
-
-#define INT_36XX_UART4_IRQ     80
-
-#define INT_35XX_HECC0_IRQ             24
-#define INT_35XX_HECC1_IRQ             28
-#define INT_35XX_EMAC_C0_RXTHRESH_IRQ  67
-#define INT_35XX_EMAC_C0_RX_PULSE_IRQ  68
-#define INT_35XX_EMAC_C0_TX_PULSE_IRQ  69
-#define INT_35XX_EMAC_C0_MISC_PULSE_IRQ        70
-#define INT_35XX_USBOTG_IRQ            71
-#define INT_35XX_UART4_IRQ             84
-#define INT_35XX_CCDC_VD0_IRQ          88
-#define INT_35XX_CCDC_VD1_IRQ          92
-#define INT_35XX_CCDC_VD2_IRQ          93
-
-/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
- * 16 MPUIO lines */
-#define OMAP_MAX_GPIO_LINES    192
-#define IH_GPIO_BASE           (128 + IH2_BASE)
-#define IH_MPUIO_BASE          (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
-#define OMAP_IRQ_END           (IH_MPUIO_BASE + 16)
-
-/* External FPGA handles interrupts on Innovator boards */
-#define        OMAP_FPGA_IRQ_BASE      (OMAP_IRQ_END)
-#ifdef CONFIG_MACH_OMAP_INNOVATOR
-#define OMAP_FPGA_NR_IRQS      24
-#else
-#define OMAP_FPGA_NR_IRQS      0
-#endif
-#define OMAP_FPGA_IRQ_END      (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
-
-/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
-#define        TWL4030_IRQ_BASE        (OMAP_FPGA_IRQ_END)
-#ifdef CONFIG_TWL4030_CORE
-#define        TWL4030_BASE_NR_IRQS    8
-#define        TWL4030_PWR_NR_IRQS     8
-#else
-#define        TWL4030_BASE_NR_IRQS    0
-#define        TWL4030_PWR_NR_IRQS     0
-#endif
-#define TWL4030_IRQ_END                (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
-#define TWL4030_PWR_IRQ_BASE   TWL4030_IRQ_END
-#define        TWL4030_PWR_IRQ_END     (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
-
-/* External TWL4030 gpio interrupts are optional */
-#define TWL4030_GPIO_IRQ_BASE  TWL4030_PWR_IRQ_END
-#ifdef CONFIG_GPIO_TWL4030
-#define TWL4030_GPIO_NR_IRQS   18
-#else
-#define        TWL4030_GPIO_NR_IRQS    0
-#endif
-#define TWL4030_GPIO_IRQ_END   (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
-
-#define        TWL6030_IRQ_BASE        (OMAP_FPGA_IRQ_END)
-#ifdef CONFIG_TWL4030_CORE
-#define        TWL6030_BASE_NR_IRQS    20
-#else
-#define        TWL6030_BASE_NR_IRQS    0
-#endif
-#define TWL6030_IRQ_END                (TWL6030_IRQ_BASE + TWL6030_BASE_NR_IRQS)
-
-#define TWL6040_CODEC_IRQ_BASE TWL6030_IRQ_END
-#ifdef CONFIG_TWL6040_CODEC
-#define TWL6040_CODEC_NR_IRQS  6
-#else
-#define TWL6040_CODEC_NR_IRQS  0
-#endif
-#define TWL6040_CODEC_IRQ_END  (TWL6040_CODEC_IRQ_BASE + TWL6040_CODEC_NR_IRQS)
-
-/* Total number of interrupts depends on the enabled blocks above */
-#if (TWL4030_GPIO_IRQ_END > TWL6040_CODEC_IRQ_END)
-#define TWL_IRQ_END            TWL4030_GPIO_IRQ_END
-#else
-#define TWL_IRQ_END            TWL6040_CODEC_IRQ_END
-#endif
-
-/* GPMC related */
-#define OMAP_GPMC_IRQ_BASE     (TWL_IRQ_END)
-#define OMAP_GPMC_NR_IRQS      8
-#define OMAP_GPMC_IRQ_END      (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)
-
-/* PRCM IRQ handler */
-#ifdef CONFIG_ARCH_OMAP2PLUS
-#define OMAP_PRCM_IRQ_BASE     (OMAP_GPMC_IRQ_END)
-#define OMAP_PRCM_NR_IRQS      64
-#define OMAP_PRCM_IRQ_END      (OMAP_PRCM_IRQ_BASE + OMAP_PRCM_NR_IRQS)
-#else
-#define OMAP_PRCM_IRQ_END      OMAP_GPMC_IRQ_END
-#endif
-
-#define NR_IRQS                        OMAP_PRCM_IRQ_END
-
-#define OMAP_IRQ_BIT(irq)      (1 << ((irq) % 32))
-
-#define INTCPS_NR_MIR_REGS     3
-#define INTCPS_NR_IRQS         96
-
-#include <mach/hardware.h>
-
-#ifdef CONFIG_FIQ
-#define FIQ_START              1024
-#endif
-
-#endif
index eb3e4d5..8b4e4f2 100644 (file)
@@ -15,7 +15,6 @@
 #include <linux/device.h>
 #include <linux/mmc/host.h>
 
-#include <plat/board.h>
 #include <plat/omap_hwmod.h>
 
 #define OMAP15XX_NR_MMC                1
index a531149..f4a4cd0 100644 (file)
@@ -21,8 +21,6 @@
 #include <linux/device.h>
 #include <linux/pm_qos.h>
 
-#include <plat/mux.h>
-
 #define DRIVER_NAME    "omap_uart"
 
 /*
@@ -54,7 +52,7 @@
 
 #define OMAP_UART_DMA_CH_FREE  -1
 
-#define OMAP_MAX_HSUART_PORTS  4
+#define OMAP_MAX_HSUART_PORTS  6
 
 #define MSR_SAVE_FLAGS         UART_MSR_ANY_DELTA
 
diff --git a/arch/arm/plat-omap/include/plat/param.h b/arch/arm/plat-omap/include/plat/param.h
deleted file mode 100644 (file)
index 1eb4dc3..0000000
+++ /dev/null
@@ -1,8 +0,0 @@
-/*
- *  arch/arm/plat-omap/include/mach/param.h
- *
- */
-
-#ifdef CONFIG_OMAP_32K_TIMER_HZ
-#define HZ     CONFIG_OMAP_32K_TIMER_HZ
-#endif
index 548a4c8..bd20588 100644 (file)
@@ -5,7 +5,6 @@
 
 #include <linux/io.h>
 #include <linux/usb/musb.h>
-#include <plat/board.h>
 
 #define OMAP3_HS_USB_PORTS     3
 
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c
deleted file mode 100644 (file)
index cff8712..0000000
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * linux/arch/arm/plat-omap/mux.c
- *
- * Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h
- *
- * Copyright (C) 2003 - 2008 Nokia Corporation
- *
- * Written by Tony Lindgren
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/spinlock.h>
-
-#include <asm/system.h>
-
-#include <plat/cpu.h>
-#include <plat/mux.h>
-
-#ifdef CONFIG_OMAP_MUX
-
-static struct omap_mux_cfg *mux_cfg;
-
-int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
-{
-       if (!arch_mux_cfg || !arch_mux_cfg->pins || arch_mux_cfg->size == 0
-                       || !arch_mux_cfg->cfg_reg) {
-               printk(KERN_ERR "Invalid pin table\n");
-               return -EINVAL;
-       }
-
-       mux_cfg = arch_mux_cfg;
-
-       return 0;
-}
-
-/*
- * Sets the Omap MUX and PULL_DWN registers based on the table
- */
-int __init_or_module omap_cfg_reg(const unsigned long index)
-{
-       struct pin_config *reg;
-
-       if (!cpu_class_is_omap1()) {
-               printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n",
-                               index);
-               WARN_ON(1);
-               return -EINVAL;
-       }
-
-       if (mux_cfg == NULL) {
-               printk(KERN_ERR "Pin mux table not initialized\n");
-               return -ENODEV;
-       }
-
-       if (index >= mux_cfg->size) {
-               printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
-                      index, mux_cfg->size);
-               dump_stack();
-               return -ENODEV;
-       }
-
-       reg = (struct pin_config *)&mux_cfg->pins[index];
-
-       if (!mux_cfg->cfg_reg)
-               return -ENODEV;
-
-       return mux_cfg->cfg_reg(reg);
-}
-EXPORT_SYMBOL(omap_cfg_reg);
-#else
-#define omap_mux_init() do {} while(0)
-#define omap_cfg_reg(x)        do {} while(0)
-#endif /* CONFIG_OMAP_MUX */
index 5a97b4d..9f64133 100644 (file)
@@ -41,11 +41,11 @@ int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t)
        };
 
        if (t == -1)
-               pr_debug("OMAP PM: remove max MPU wakeup latency constraint: "
-                        "dev %s\n", dev_name(dev));
+               pr_debug("OMAP PM: remove max MPU wakeup latency constraint: dev %s\n",
+                        dev_name(dev));
        else
-               pr_debug("OMAP PM: add max MPU wakeup latency constraint: "
-                        "dev %s, t = %ld usec\n", dev_name(dev), t);
+               pr_debug("OMAP PM: add max MPU wakeup latency constraint: dev %s, t = %ld usec\n",
+                        dev_name(dev), t);
 
        /*
         * For current Linux, this needs to map the MPU to a
@@ -70,11 +70,10 @@ int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r)
        };
 
        if (r == 0)
-               pr_debug("OMAP PM: remove min bus tput constraint: "
-                        "dev %s for agent_id %d\n", dev_name(dev), agent_id);
+               pr_debug("OMAP PM: remove min bus tput constraint: dev %s for agent_id %d\n",
+                        dev_name(dev), agent_id);
        else
-               pr_debug("OMAP PM: add min bus tput constraint: "
-                        "dev %s for agent_id %d: rate %ld KiB\n",
+               pr_debug("OMAP PM: add min bus tput constraint: dev %s for agent_id %d: rate %ld KiB\n",
                         dev_name(dev), agent_id, r);
 
        /*
@@ -97,11 +96,11 @@ int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev,
        };
 
        if (t == -1)
-               pr_debug("OMAP PM: remove max device latency constraint: "
-                        "dev %s\n", dev_name(dev));
+               pr_debug("OMAP PM: remove max device latency constraint: dev %s\n",
+                        dev_name(dev));
        else
-               pr_debug("OMAP PM: add max device latency constraint: "
-                        "dev %s, t = %ld usec\n", dev_name(dev), t);
+               pr_debug("OMAP PM: add max device latency constraint: dev %s, t = %ld usec\n",
+                        dev_name(dev), t);
 
        /*
         * For current Linux, this needs to map the device to a
@@ -127,11 +126,11 @@ int omap_pm_set_max_sdma_lat(struct device *dev, long t)
        };
 
        if (t == -1)
-               pr_debug("OMAP PM: remove max DMA latency constraint: "
-                        "dev %s\n", dev_name(dev));
+               pr_debug("OMAP PM: remove max DMA latency constraint: dev %s\n",
+                        dev_name(dev));
        else
-               pr_debug("OMAP PM: add max DMA latency constraint: "
-                        "dev %s, t = %ld usec\n", dev_name(dev), t);
+               pr_debug("OMAP PM: add max DMA latency constraint: dev %s, t = %ld usec\n",
+                        dev_name(dev), t);
 
        /*
         * For current Linux PM QOS params, this code should scan the
@@ -156,11 +155,11 @@ int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r)
        }
 
        if (r == 0)
-               pr_debug("OMAP PM: remove min clk rate constraint: "
-                        "dev %s\n", dev_name(dev));
+               pr_debug("OMAP PM: remove min clk rate constraint: dev %s\n",
+                        dev_name(dev));
        else
-               pr_debug("OMAP PM: add min clk rate constraint: "
-                        "dev %s, rate = %ld Hz\n", dev_name(dev), r);
+               pr_debug("OMAP PM: add min clk rate constraint: dev %s, rate = %ld Hz\n",
+                        dev_name(dev), r);
 
        /*
         * Code in a real implementation should keep track of these
index c490240..b59edb0 100644 (file)
@@ -1,4 +1,3 @@
-
 /*
  * omap_device implementation
  *
@@ -153,21 +152,19 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
                act_lat = timespec_to_ns(&c);
 
                dev_dbg(&od->pdev->dev,
-                       "omap_device: pm_lat %d: activate: elapsed time "
-                       "%llu nsec\n", od->pm_lat_level, act_lat);
+                       "omap_device: pm_lat %d: activate: elapsed time %llu nsec\n",
+                       od->pm_lat_level, act_lat);
 
                if (act_lat > odpl->activate_lat) {
                        odpl->activate_lat_worst = act_lat;
                        if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
                                odpl->activate_lat = act_lat;
                                dev_dbg(&od->pdev->dev,
-                                       "new worst case activate latency "
-                                       "%d: %llu\n",
+                                       "new worst case activate latency %d: %llu\n",
                                        od->pm_lat_level, act_lat);
                        } else
                                dev_warn(&od->pdev->dev,
-                                        "activate latency %d "
-                                        "higher than exptected. (%llu > %d)\n",
+                                        "activate latency %d higher than expected. (%llu > %d)\n",
                                         od->pm_lat_level, act_lat,
                                         odpl->activate_lat);
                }
@@ -220,21 +217,19 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
                deact_lat = timespec_to_ns(&c);
 
                dev_dbg(&od->pdev->dev,
-                       "omap_device: pm_lat %d: deactivate: elapsed time "
-                       "%llu nsec\n", od->pm_lat_level, deact_lat);
+                       "omap_device: pm_lat %d: deactivate: elapsed time %llu nsec\n",
+                       od->pm_lat_level, deact_lat);
 
                if (deact_lat > odpl->deactivate_lat) {
                        odpl->deactivate_lat_worst = deact_lat;
                        if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
                                odpl->deactivate_lat = deact_lat;
                                dev_dbg(&od->pdev->dev,
-                                       "new worst case deactivate latency "
-                                       "%d: %llu\n",
+                                       "new worst case deactivate latency %d: %llu\n",
                                        od->pm_lat_level, deact_lat);
                        } else
                                dev_warn(&od->pdev->dev,
-                                        "deactivate latency %d "
-                                        "higher than exptected. (%llu > %d)\n",
+                                        "deactivate latency %d higher than expected. (%llu > %d)\n",
                                         od->pm_lat_level, deact_lat,
                                         odpl->deactivate_lat);
                }
@@ -449,8 +444,8 @@ static int omap_device_count_resources(struct omap_device *od)
        for (i = 0; i < od->hwmods_cnt; i++)
                c += omap_hwmod_count_resources(od->hwmods[i]);
 
-       pr_debug("omap_device: %s: counted %d total resources across %d "
-                "hwmods\n", od->pdev->name, c, od->hwmods_cnt);
+       pr_debug("omap_device: %s: counted %d total resources across %d hwmods\n",
+                od->pdev->name, c, od->hwmods_cnt);
 
        return c;
 }
index 024f3b0..28acb38 100644 (file)
@@ -26,7 +26,6 @@
 #include <asm/mach/map.h>
 
 #include <plat/sram.h>
-#include <plat/board.h>
 #include <plat/cpu.h>
 
 #include "sram.h"
index 2195209..fed07d2 100644 (file)
@@ -35,7 +35,6 @@
 #include <media/s5p_hdmi.h>
 
 #include <asm/irq.h>
-#include <asm/pmu.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
@@ -1132,7 +1131,7 @@ static struct resource s5p_pmu_resource[] = {
 
 static struct platform_device s5p_device_pmu = {
        .name           = "arm-pmu",
-       .id             = ARM_PMU_DEVICE_CPU,
+       .id             = -1,
        .num_resources  = ARRAY_SIZE(s5p_pmu_resource),
        .resource       = s5p_pmu_resource,
 };
index bab1392..d1ecef0 100644 (file)
@@ -1,98 +1 @@
-/* arch/arm/mach-s3c2410/include/mach/gpio-fns.h
- *
- * Copyright (c) 2003-2009 Simtec Electronics
- *     Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - hardware
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __MACH_GPIO_FNS_H
-#define __MACH_GPIO_FNS_H __FILE__
-
-/* These functions are in the to-be-removed category and it is strongly
- * encouraged not to use these in new code. They will be marked deprecated
- * very soon.
- *
- * Most of the functionality can be either replaced by the gpiocfg calls
- * for the s3c platform or by the generic GPIOlib API.
- *
- * As of 2.6.35-rc, these will be removed, with the few drivers using them
- * either replaced or given a wrapper until the calls can be removed.
-*/
-
 #include <plat/gpio-cfg.h>
-
-static inline void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int cfg)
-{
-       /* 1:1 mapping between cfgpin and setcfg calls at the moment */
-       s3c_gpio_cfgpin(pin, cfg);
-}
-
-/* external functions for GPIO support
- *
- * These allow various different clients to access the same GPIO
- * registers without conflicting. If your driver only owns the entire
- * GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
-*/
-
-extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
-
-/* s3c2410_gpio_getirq
- *
- * turn the given pin number into the corresponding IRQ number
- *
- * returns:
- *     < 0 = no interrupt for this pin
- *     >=0 = interrupt number for the pin
-*/
-
-extern int s3c2410_gpio_getirq(unsigned int pin);
-
-/* s3c2410_gpio_irqfilter
- *
- * set the irq filtering on the given pin
- *
- * on = 0 => disable filtering
- *      1 => enable filtering
- *
- * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with
- *          width of filter (0 through 63)
- *
- *
-*/
-
-extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
-                                 unsigned int config);
-
-/* s3c2410_gpio_pullup
- *
- * This call should be replaced with s3c_gpio_setpull().
- *
- * As a note, there is currently no distinction between pull-up and pull-down
- * in the s3c24xx series devices with only an on/off configuration.
- */
-
-/* s3c2410_gpio_pullup
- *
- * configure the pull-up control on the given pin
- *
- * to = 1 => disable the pull-up
- *      0 => enable the pull-up
- *
- * eg;
- *
- *   s3c2410_gpio_pullup(S3C2410_GPB(0), 0);
- *   s3c2410_gpio_pullup(S3C2410_GPE(8), 0);
-*/
-
-extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
-
-extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
-
-extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
-
-#endif /* __MACH_GPIO_FNS_H */
index f9431fe..23557d3 100644 (file)
@@ -24,7 +24,7 @@
 
 #include <asm/mach/irq.h>
 
-#define GPIO_BASE(chip)                (((unsigned long)(chip)->base) & 0xFFFFF000u)
+#define GPIO_BASE(chip)                ((void __iomem *)((unsigned long)((chip)->base) & 0xFFFFF000u))
 
 #define CON_OFFSET             0x700
 #define MASK_OFFSET            0x900
@@ -153,7 +153,7 @@ static __init int s5p_gpioint_add(struct samsung_gpio_chip *chip)
        bank->chips[group - bank->start] = chip;
 
        gc = irq_alloc_generic_chip("s5p_gpioint", 1, chip->irq_base,
-                                   (void __iomem *)GPIO_BASE(chip),
+                                   GPIO_BASE(chip),
                                    handle_level_irq);
        if (!gc)
                return -ENOMEM;
index 2997e56..7bc7948 100644 (file)
@@ -158,7 +158,6 @@ edb9315a            MACH_EDB9315A           EDB9315A                772
 stargate2              MACH_STARGATE2          STARGATE2               774
 intelmote2             MACH_INTELMOTE2         INTELMOTE2              775
 trizeps4               MACH_TRIZEPS4           TRIZEPS4                776
-pnx4008                        MACH_PNX4008            PNX4008                 782
 cpuat91                        MACH_CPUAT91            CPUAT91                 787
 iq81340sc              MACH_IQ81340SC          IQ81340SC               799
 iq81340mc              MACH_IQ81340MC          IQ81340MC               801
index ae05618..2e16627 100644 (file)
@@ -18,6 +18,8 @@
 #include <linux/spinlock.h>
 
 #include "virt-dma.h"
+
+#include <plat/cpu.h>
 #include <plat/dma.h>
 
 struct omap_dmadev {
index 0725d18..94cbc84 100644 (file)
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/irqdomain.h>
+#include <linux/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
 
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <mach/irqs.h>
-#include <asm/gpio.h>
 #include <asm/mach/irq.h>
 
 #define OFF_MODE       1
@@ -385,13 +383,16 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
 static int gpio_irq_type(struct irq_data *d, unsigned type)
 {
        struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
-       unsigned gpio;
+       unsigned gpio = 0;
        int retval;
        unsigned long flags;
 
-       if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
+#ifdef CONFIG_ARCH_OMAP1
+       if (d->irq > IH_MPUIO_BASE)
                gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
-       else
+#endif
+
+       if (!gpio)
                gpio = irq_to_gpio(bank, d->irq);
 
        if (type & ~IRQ_TYPE_SENSE_MASK)
index ba126cc..1c16932 100644 (file)
@@ -3131,46 +3131,6 @@ samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
 }
 EXPORT_SYMBOL(s3c_gpio_getpull);
 
-/* gpiolib wrappers until these are totally eliminated */
-
-void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
-{
-       int ret;
-
-       WARN_ON(to);    /* should be none of these left */
-
-       if (!to) {
-               /* if pull is enabled, try first with up, and if that
-                * fails, try using down */
-
-               ret = s3c_gpio_setpull(pin, S3C_GPIO_PULL_UP);
-               if (ret)
-                       s3c_gpio_setpull(pin, S3C_GPIO_PULL_DOWN);
-       } else {
-               s3c_gpio_setpull(pin, S3C_GPIO_PULL_NONE);
-       }
-}
-EXPORT_SYMBOL(s3c2410_gpio_pullup);
-
-void s3c2410_gpio_setpin(unsigned int pin, unsigned int to)
-{
-       /* do this via gpiolib until all users removed */
-
-       gpio_request(pin, "temporary");
-       gpio_set_value(pin, to);
-       gpio_free(pin);
-}
-EXPORT_SYMBOL(s3c2410_gpio_setpin);
-
-unsigned int s3c2410_gpio_getpin(unsigned int pin)
-{
-       struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
-       unsigned long offs = pin - chip->chip.base;
-
-       return __raw_readl(chip->base + 0x04) & (1 << offs);
-}
-EXPORT_SYMBOL(s3c2410_gpio_getpin);
-
 #ifdef CONFIG_S5P_GPIO_DRVSTR
 s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
 {
index dc5184d..d982593 100644 (file)
@@ -30,9 +30,6 @@
 
 #include <asm/mach/irq.h>
 
-#include <mach/iomap.h>
-#include <mach/suspend.h>
-
 #define GPIO_BANK(x)           ((x) >> 5)
 #define GPIO_PORT(x)           (((x) >> 3) & 0x3)
 #define GPIO_BIT(x)            ((x) & 0x7)
index 94256fe..f030880 100644 (file)
@@ -51,6 +51,7 @@
 
 
 static struct gpio_chip twl_gpiochip;
+static int twl4030_gpio_base;
 static int twl4030_gpio_irq_base;
 
 /* genirq interfaces are not available to modules */
@@ -428,8 +429,6 @@ no_irqs:
        twl_gpiochip.dev = &pdev->dev;
 
        if (pdata) {
-               twl_gpiochip.base = pdata->gpio_base;
-
                /*
                 * NOTE:  boards may waste power if they don't set pullups
                 * and pulldowns correctly ... default for non-ULPI pins is
@@ -461,15 +460,21 @@ no_irqs:
                dev_err(&pdev->dev, "could not register gpiochip, %d\n", ret);
                twl_gpiochip.ngpio = 0;
                gpio_twl4030_remove(pdev);
-       } else if (pdata && pdata->setup) {
+               goto out;
+       }
+
+       twl4030_gpio_base = twl_gpiochip.base;
+
+       if (pdata && pdata->setup) {
                int status;
 
                status = pdata->setup(&pdev->dev,
-                               pdata->gpio_base, TWL4030_GPIO_MAX);
+                               twl4030_gpio_base, TWL4030_GPIO_MAX);
                if (status)
                        dev_dbg(&pdev->dev, "setup --> %d\n", status);
        }
 
+out:
        return ret;
 }
 
@@ -481,7 +486,7 @@ static int gpio_twl4030_remove(struct platform_device *pdev)
 
        if (pdata && pdata->teardown) {
                status = pdata->teardown(&pdev->dev,
-                               pdata->gpio_base, TWL4030_GPIO_MAX);
+                               twl4030_gpio_base, TWL4030_GPIO_MAX);
                if (status) {
                        dev_dbg(&pdev->dev, "teardown --> %d\n", status);
                        return status;
index 970a161..42d9fdd 100644 (file)
@@ -551,7 +551,7 @@ config I2C_PMCMSP
 
 config I2C_PNX
        tristate "I2C bus support for Philips PNX and NXP LPC targets"
-       depends on ARCH_PNX4008 || ARCH_LPC32XX
+       depends on ARCH_LPC32XX
        help
          This driver supports the Philips IP3204 I2C IP block master and/or
          slave controller
index 93f147a..2f99613 100644 (file)
@@ -4,13 +4,13 @@
 /* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
  *                    <Peter dot Milne at D hyphen TACQ dot com>
  *
- * With acknowledgements to i2c-algo-ibm_ocp.c by 
+ * With acknowledgements to i2c-algo-ibm_ocp.c by
  * Ian DaSilva, MontaVista Software, Inc. idasilva@mvista.com
  *
  * And i2c-algo-pcf.c, which was created by Simon G. Vogl and Hans Berglund:
  *
  * Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund
- *  
+ *
  * And which acknowledged Kyösti Mälkki <kmalkki@cc.hut.fi>,
  * Frodo Looijaard <frodol@dds.nl>, Martin Bailey<mbailey@littlefeet-inc.com>
  *
 #include <linux/platform_device.h>
 #include <linux/i2c.h>
 #include <linux/io.h>
+#include <linux/gpio.h>
 
 #include "i2c-iop3xx.h"
 
 /* global unit counter */
 static int i2c_id;
 
-static inline unsigned char 
-iic_cook_addr(struct i2c_msg *msg) 
+static inline unsigned char
+iic_cook_addr(struct i2c_msg *msg)
 {
        unsigned char addr;
 
@@ -55,38 +56,38 @@ iic_cook_addr(struct i2c_msg *msg)
        if (msg->flags & I2C_M_RD)
                addr |= 1;
 
-       return addr;   
+       return addr;
 }
 
-static void 
+static void
 iop3xx_i2c_reset(struct i2c_algo_iop3xx_data *iop3xx_adap)
 {
        /* Follows devman 9.3 */
        __raw_writel(IOP3XX_ICR_UNIT_RESET, iop3xx_adap->ioaddr + CR_OFFSET);
        __raw_writel(IOP3XX_ISR_CLEARBITS, iop3xx_adap->ioaddr + SR_OFFSET);
        __raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET);
-} 
+}
 
-static void 
+static void
 iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap)
 {
        u32 cr = IOP3XX_ICR_GCD | IOP3XX_ICR_SCLEN | IOP3XX_ICR_UE;
 
-       /* 
+       /*
         * Every time unit enable is asserted, GPOD needs to be cleared
         * on IOP3XX to avoid data corruption on the bus.
         */
 #if defined(CONFIG_ARCH_IOP32X) || defined(CONFIG_ARCH_IOP33X)
        if (iop3xx_adap->id == 0) {
-               gpio_line_set(IOP3XX_GPIO_LINE(7), GPIO_LOW);
-               gpio_line_set(IOP3XX_GPIO_LINE(6), GPIO_LOW);
+               gpio_set_value(7, 0);
+               gpio_set_value(6, 0);
        } else {
-               gpio_line_set(IOP3XX_GPIO_LINE(5), GPIO_LOW);
-               gpio_line_set(IOP3XX_GPIO_LINE(4), GPIO_LOW);
+               gpio_set_value(5, 0);
+               gpio_set_value(4, 0);
        }
 #endif
        /* NB SR bits not same position as CR IE bits :-( */
-       iop3xx_adap->SR_enabled = 
+       iop3xx_adap->SR_enabled =
                IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD |
                IOP3XX_ISR_RXFULL | IOP3XX_ISR_TXEMPTY;
 
@@ -96,23 +97,23 @@ iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap)
        __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
 }
 
-static void 
+static void
 iop3xx_i2c_transaction_cleanup(struct i2c_algo_iop3xx_data *iop3xx_adap)
 {
        unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
-       
-       cr &= ~(IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE | 
+
+       cr &= ~(IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE |
                IOP3XX_ICR_MSTOP | IOP3XX_ICR_SCLEN);
 
        __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
 }
 
-/* 
- * NB: the handler has to clear the source of the interrupt! 
+/*
+ * NB: the handler has to clear the source of the interrupt!
  * Then it passes the SR flags of interest to BH via adap data
  */
-static irqreturn_t 
-iop3xx_i2c_irq_handler(int this_irq, void *dev_id) 
+static irqreturn_t
+iop3xx_i2c_irq_handler(int this_irq, void *dev_id)
 {
        struct i2c_algo_iop3xx_data *iop3xx_adap = dev_id;
        u32 sr = __raw_readl(iop3xx_adap->ioaddr + SR_OFFSET);
@@ -126,7 +127,7 @@ iop3xx_i2c_irq_handler(int this_irq, void *dev_id)
 }
 
 /* check all error conditions, clear them , report most important */
-static int 
+static int
 iop3xx_i2c_error(u32 sr)
 {
        int rc = 0;
@@ -135,12 +136,12 @@ iop3xx_i2c_error(u32 sr)
                if ( !rc ) rc = -I2C_ERR_BERR;
        }
        if ((sr & IOP3XX_ISR_ALD)) {
-               if ( !rc ) rc = -I2C_ERR_ALD;           
+               if ( !rc ) rc = -I2C_ERR_ALD;
        }
-       return rc;      
+       return rc;
 }
 
-static inline u32 
+static inline u32
 iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap)
 {
        unsigned long flags;
@@ -161,8 +162,8 @@ iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap)
 typedef int (* compare_func)(unsigned test, unsigned mask);
 /* returns 1 on correct comparison */
 
-static int 
-iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap, 
+static int
+iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap,
                          unsigned flags, unsigned* status,
                          compare_func compare)
 {
@@ -192,47 +193,47 @@ iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap,
 }
 
 /*
- * Concrete compare_funcs 
+ * Concrete compare_funcs
  */
-static int 
+static int
 all_bits_clear(unsigned test, unsigned mask)
 {
        return (test & mask) == 0;
 }
 
-static int 
+static int
 any_bits_set(unsigned test, unsigned mask)
 {
        return (test & mask) != 0;
 }
 
-static int 
+static int
 iop3xx_i2c_wait_tx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
 {
-       return iop3xx_i2c_wait_event( 
-               iop3xx_adap, 
+       return iop3xx_i2c_wait_event(
+               iop3xx_adap,
                IOP3XX_ISR_TXEMPTY | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
                status, any_bits_set);
 }
 
-static int 
+static int
 iop3xx_i2c_wait_rx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
 {
-       return iop3xx_i2c_wait_event( 
-               iop3xx_adap, 
+       return iop3xx_i2c_wait_event(
+               iop3xx_adap,
                IOP3XX_ISR_RXFULL | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
                status, any_bits_set);
 }
 
-static int 
+static int
 iop3xx_i2c_wait_idle(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
 {
-       return iop3xx_i2c_wait_event( 
+       return iop3xx_i2c_wait_event(
                iop3xx_adap, IOP3XX_ISR_UNITBUSY, status, all_bits_clear);
 }
 
-static int 
-iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap, 
+static int
+iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap,
                                struct i2c_msg* msg)
 {
        unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
@@ -247,7 +248,7 @@ iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap,
        }
 
        __raw_writel(iic_cook_addr(msg), iop3xx_adap->ioaddr + DBR_OFFSET);
-       
+
        cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK);
        cr |= IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE;
 
@@ -257,8 +258,8 @@ iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap,
        return rc;
 }
 
-static int 
-iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte, 
+static int
+iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte,
                                int stop)
 {
        unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
@@ -277,10 +278,10 @@ iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte,
        rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);
 
        return rc;
-} 
+}
 
-static int 
-iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte, 
+static int
+iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte,
                                int stop)
 {
        unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
@@ -304,19 +305,19 @@ iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte,
        return rc;
 }
 
-static int 
+static int
 iop3xx_i2c_writebytes(struct i2c_adapter *i2c_adap, const char *buf, int count)
 {
        struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
        int ii;
        int rc = 0;
 
-       for (ii = 0; rc == 0 && ii != count; ++ii) 
+       for (ii = 0; rc == 0 && ii != count; ++ii)
                rc = iop3xx_i2c_write_byte(iop3xx_adap, buf[ii], ii==count-1);
        return rc;
 }
 
-static int 
+static int
 iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count)
 {
        struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
@@ -325,7 +326,7 @@ iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count)
 
        for (ii = 0; rc == 0 && ii != count; ++ii)
                rc = iop3xx_i2c_read_byte(iop3xx_adap, &buf[ii], ii==count-1);
-       
+
        return rc;
 }
 
@@ -336,8 +337,8 @@ iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count)
  * Each transfer (i.e. a read or a write) is separated by a repeated start
  * condition.
  */
-static int 
-iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg) 
+static int
+iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg)
 {
        struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
        int rc;
@@ -357,8 +358,8 @@ iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg)
 /*
  * master_xfer() - main read/write entry
  */
-static int 
-iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, 
+static int
+iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
                                int num)
 {
        struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
@@ -375,14 +376,14 @@ iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
        }
 
        iop3xx_i2c_transaction_cleanup(iop3xx_adap);
-       
+
        if(ret)
                return ret;
 
-       return im;   
+       return im;
 }
 
-static u32 
+static u32
 iop3xx_i2c_func(struct i2c_adapter *adap)
 {
        return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
@@ -393,11 +394,11 @@ static const struct i2c_algorithm iop3xx_i2c_algo = {
        .functionality  = iop3xx_i2c_func,
 };
 
-static int 
+static int
 iop3xx_i2c_remove(struct platform_device *pdev)
 {
        struct i2c_adapter *padapter = platform_get_drvdata(pdev);
-       struct i2c_algo_iop3xx_data *adapter_data = 
+       struct i2c_algo_iop3xx_data *adapter_data =
                (struct i2c_algo_iop3xx_data *)padapter->algo_data;
        struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        unsigned long cr = __raw_readl(adapter_data->ioaddr + CR_OFFSET);
@@ -419,7 +420,7 @@ iop3xx_i2c_remove(struct platform_device *pdev)
        return 0;
 }
 
-static int 
+static int
 iop3xx_i2c_probe(struct platform_device *pdev)
 {
        struct resource *res;
index c50fa75..b4b65af 100644 (file)
@@ -533,7 +533,7 @@ config KEYBOARD_DAVINCI
 
 config KEYBOARD_OMAP
        tristate "TI OMAP keypad support"
-       depends on (ARCH_OMAP1 || ARCH_OMAP2)
+       depends on ARCH_OMAP1
        select INPUT_MATRIXKMAP
        help
          Say Y here if you want to use the OMAP keypad.
index a0222db..6d6b142 100644 (file)
 #include <linux/mutex.h>
 #include <linux/errno.h>
 #include <linux/slab.h>
-#include <asm/gpio.h>
-#include <plat/keypad.h>
-#include <plat/menelaus.h>
-#include <asm/irq.h>
-#include <mach/hardware.h>
-#include <asm/io.h>
-#include <plat/mux.h>
+#include <linux/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
+#include <linux/platform_data/keypad-omap.h>
 
 #undef NEW_BOARD_LEARNING_MODE
 
@@ -96,28 +92,8 @@ static u8 get_row_gpio_val(struct omap_kp *omap_kp)
 
 static irqreturn_t omap_kp_interrupt(int irq, void *dev_id)
 {
-       struct omap_kp *omap_kp = dev_id;
-
        /* disable keyboard interrupt and schedule for handling */
-       if (cpu_is_omap24xx()) {
-               int i;
-
-               for (i = 0; i < omap_kp->rows; i++) {
-                       int gpio_irq = gpio_to_irq(row_gpios[i]);
-                       /*
-                        * The interrupt which we're currently handling should
-                        * be disabled _nosync() to avoid deadlocks waiting
-                        * for this handler to complete.  All others should
-                        * be disabled the regular way for SMP safety.
-                        */
-                       if (gpio_irq == irq)
-                               disable_irq_nosync(gpio_irq);
-                       else
-                               disable_irq(gpio_irq);
-               }
-       } else
-               /* disable keyboard interrupt and schedule for handling */
-               omap_writew(1, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
+       omap_writew(1, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
 
        tasklet_schedule(&kp_tasklet);
 
@@ -133,33 +109,22 @@ static void omap_kp_scan_keypad(struct omap_kp *omap_kp, unsigned char *state)
 {
        int col = 0;
 
-       /* read the keypad status */
-       if (cpu_is_omap24xx()) {
-               /* read the keypad status */
-               for (col = 0; col < omap_kp->cols; col++) {
-                       set_col_gpio_val(omap_kp, ~(1 << col));
-                       state[col] = ~(get_row_gpio_val(omap_kp)) & 0xff;
-               }
-               set_col_gpio_val(omap_kp, 0);
-
-       } else {
-               /* disable keyboard interrupt and schedule for handling */
-               omap_writew(1, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
+       /* disable keyboard interrupt and schedule for handling */
+       omap_writew(1, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
 
-               /* read the keypad status */
-               omap_writew(0xff, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBC);
-               for (col = 0; col < omap_kp->cols; col++) {
-                       omap_writew(~(1 << col) & 0xff,
-                                   OMAP1_MPUIO_BASE + OMAP_MPUIO_KBC);
+       /* read the keypad status */
+       omap_writew(0xff, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBC);
+       for (col = 0; col < omap_kp->cols; col++) {
+               omap_writew(~(1 << col) & 0xff,
+                           OMAP1_MPUIO_BASE + OMAP_MPUIO_KBC);
 
-                       udelay(omap_kp->delay);
+               udelay(omap_kp->delay);
 
-                       state[col] = ~omap_readw(OMAP1_MPUIO_BASE +
-                                                OMAP_MPUIO_KBR_LATCH) & 0xff;
-               }
-               omap_writew(0x00, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBC);
-               udelay(2);
+               state[col] = ~omap_readw(OMAP1_MPUIO_BASE +
+                                        OMAP_MPUIO_KBR_LATCH) & 0xff;
        }
+       omap_writew(0x00, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBC);
+       udelay(2);
 }
 
 static void omap_kp_tasklet(unsigned long data)
@@ -222,14 +187,8 @@ static void omap_kp_tasklet(unsigned long data)
                mod_timer(&omap_kp_data->timer, jiffies + delay);
        } else {
                /* enable interrupts */
-               if (cpu_is_omap24xx()) {
-                       int i;
-                       for (i = 0; i < omap_kp_data->rows; i++)
-                               enable_irq(gpio_to_irq(row_gpios[i]));
-               } else {
-                       omap_writew(0, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
-                       kp_cur_group = -1;
-               }
+               omap_writew(0, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
+               kp_cur_group = -1;
        }
 }
 
@@ -242,6 +201,7 @@ static ssize_t omap_kp_enable_show(struct device *dev,
 static ssize_t omap_kp_enable_store(struct device *dev, struct device_attribute *attr,
                                    const char *buf, size_t count)
 {
+       struct omap_kp *omap_kp = dev_get_drvdata(dev);
        int state;
 
        if (sscanf(buf, "%u", &state) != 1)
@@ -253,9 +213,9 @@ static ssize_t omap_kp_enable_store(struct device *dev, struct device_attribute
        mutex_lock(&kp_enable_mutex);
        if (state != kp_enable) {
                if (state)
-                       enable_irq(INT_KEYBOARD);
+                       enable_irq(omap_kp->irq);
                else
-                       disable_irq(INT_KEYBOARD);
+                       disable_irq(omap_kp->irq);
                kp_enable = state;
        }
        mutex_unlock(&kp_enable_mutex);
@@ -289,7 +249,7 @@ static int __devinit omap_kp_probe(struct platform_device *pdev)
        struct omap_kp *omap_kp;
        struct input_dev *input_dev;
        struct omap_kp_platform_data *pdata =  pdev->dev.platform_data;
-       int i, col_idx, row_idx, irq_idx, ret;
+       int i, col_idx, row_idx, ret;
        unsigned int row_shift, keycodemax;
 
        if (!pdata->rows || !pdata->cols || !pdata->keymap_data) {
@@ -314,8 +274,7 @@ static int __devinit omap_kp_probe(struct platform_device *pdev)
        omap_kp->input = input_dev;
 
        /* Disable the interrupt for the MPUIO keyboard */
-       if (!cpu_is_omap24xx())
-               omap_writew(1, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
+       omap_writew(1, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
 
        if (pdata->delay)
                omap_kp->delay = pdata->delay;
@@ -328,31 +287,8 @@ static int __devinit omap_kp_probe(struct platform_device *pdev)
        omap_kp->rows = pdata->rows;
        omap_kp->cols = pdata->cols;
 
-       if (cpu_is_omap24xx()) {
-               /* Cols: outputs */
-               for (col_idx = 0; col_idx < omap_kp->cols; col_idx++) {
-                       if (gpio_request(col_gpios[col_idx], "omap_kp_col") < 0) {
-                               printk(KERN_ERR "Failed to request"
-                                      "GPIO%d for keypad\n",
-                                      col_gpios[col_idx]);
-                               goto err1;
-                       }
-                       gpio_direction_output(col_gpios[col_idx], 0);
-               }
-               /* Rows: inputs */
-               for (row_idx = 0; row_idx < omap_kp->rows; row_idx++) {
-                       if (gpio_request(row_gpios[row_idx], "omap_kp_row") < 0) {
-                               printk(KERN_ERR "Failed to request"
-                                      "GPIO%d for keypad\n",
-                                      row_gpios[row_idx]);
-                               goto err2;
-                       }
-                       gpio_direction_input(row_gpios[row_idx]);
-               }
-       } else {
-               col_idx = 0;
-               row_idx = 0;
-       }
+       col_idx = 0;
+       row_idx = 0;
 
        setup_timer(&omap_kp->timer, omap_kp_timer, (unsigned long)omap_kp);
 
@@ -394,27 +330,16 @@ static int __devinit omap_kp_probe(struct platform_device *pdev)
 
        /* scan current status and enable interrupt */
        omap_kp_scan_keypad(omap_kp, keypad_state);
-       if (!cpu_is_omap24xx()) {
-               omap_kp->irq = platform_get_irq(pdev, 0);
-               if (omap_kp->irq >= 0) {
-                       if (request_irq(omap_kp->irq, omap_kp_interrupt, 0,
-                                       "omap-keypad", omap_kp) < 0)
-                               goto err4;
-               }
-               omap_writew(0, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
-       } else {
-               for (irq_idx = 0; irq_idx < omap_kp->rows; irq_idx++) {
-                       if (request_irq(gpio_to_irq(row_gpios[irq_idx]),
-                                       omap_kp_interrupt,
-                                       IRQF_TRIGGER_FALLING,
-                                       "omap-keypad", omap_kp) < 0)
-                               goto err5;
-               }
+       omap_kp->irq = platform_get_irq(pdev, 0);
+       if (omap_kp->irq >= 0) {
+               if (request_irq(omap_kp->irq, omap_kp_interrupt, 0,
+                               "omap-keypad", omap_kp) < 0)
+                       goto err4;
        }
+       omap_writew(0, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
+
        return 0;
-err5:
-       for (i = irq_idx - 1; i >=0; i--)
-               free_irq(row_gpios[i], omap_kp);
+
 err4:
        input_unregister_device(omap_kp->input);
        input_dev = NULL;
@@ -423,7 +348,6 @@ err3:
 err2:
        for (i = row_idx - 1; i >=0; i--)
                gpio_free(row_gpios[i]);
-err1:
        for (i = col_idx - 1; i >=0; i--)
                gpio_free(col_gpios[i]);
 
@@ -439,18 +363,8 @@ static int __devexit omap_kp_remove(struct platform_device *pdev)
 
        /* disable keypad interrupt handling */
        tasklet_disable(&kp_tasklet);
-       if (cpu_is_omap24xx()) {
-               int i;
-               for (i = 0; i < omap_kp->cols; i++)
-                       gpio_free(col_gpios[i]);
-               for (i = 0; i < omap_kp->rows; i++) {
-                       gpio_free(row_gpios[i]);
-                       free_irq(gpio_to_irq(row_gpios[i]), omap_kp);
-               }
-       } else {
-               omap_writew(1, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
-               free_irq(omap_kp->irq, omap_kp);
-       }
+       omap_writew(1, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
+       free_irq(omap_kp->irq, omap_kp);
 
        del_timer_sync(&omap_kp->timer);
        tasklet_kill(&kp_tasklet);
index 272dedd..21c60fe 100644 (file)
@@ -42,7 +42,7 @@ static irqreturn_t rpcmouse_irq(int irq, void *dev_id)
 
        x = (short) iomd_readl(IOMD_MOUSEX);
        y = (short) iomd_readl(IOMD_MOUSEY);
-       b = (short) (__raw_readl(0xe0310000) ^ 0x70);
+       b = (short) (__raw_readl(IOMEM(0xe0310000)) ^ 0x70);
 
        dx = x - rpcmouse_lastx;
        dy = y - rpcmouse_lasty;
index f5fbdf9..45887e3 100644 (file)
@@ -27,7 +27,7 @@
 #include <linux/module.h>
 
 #include <asm/mach-types.h>
-#include <plat/board-ams-delta.h>
+#include <mach/board-ams-delta.h>
 
 #include <mach/ams-delta-fiq.h>
 
index 88cf9d9..409da0f 100644 (file)
@@ -44,6 +44,7 @@
 #include <media/v4l2-device.h>
 #include <media/v4l2-ioctl.h>
 
+#include <plat/cpu.h>
 #include <plat/dma.h>
 #include <plat/vrfb.h>
 #include <video/omapdss.h>
index 1c34763..43e61fe 100644 (file)
@@ -70,6 +70,8 @@
 #include <media/v4l2-common.h>
 #include <media/v4l2-device.h>
 
+#include <plat/cpu.h>
+
 #include "isp.h"
 #include "ispreg.h"
 #include "ispccdc.h"
index 1c32afe..9d3a0bc 100644 (file)
@@ -1132,12 +1132,7 @@ static void clocks_init(struct device *dev,
        u32 rate;
        u8 ctrl = HFCLK_FREQ_26_MHZ;
 
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-       if (cpu_is_omap2430())
-               osc = clk_get(dev, "osc_ck");
-       else
-               osc = clk_get(dev, "osc_sys_ck");
-
+       osc = clk_get(dev, "fck");
        if (IS_ERR(osc)) {
                printk(KERN_WARNING "Skipping twl internal clock init and "
                                "using bootloader value (unknown osc rate)\n");
@@ -1147,18 +1142,6 @@ static void clocks_init(struct device *dev,
        rate = clk_get_rate(osc);
        clk_put(osc);
 
-#else
-       /* REVISIT for non-OMAP systems, pass the clock rate from
-        * board init code, using platform_data.
-        */
-       osc = ERR_PTR(-EIO);
-
-       printk(KERN_WARNING "Skipping twl internal clock init and "
-              "using bootloader value (unknown osc rate)\n");
-
-       return;
-#endif
-
        switch (rate) {
        case 19200000:
                ctrl = HFCLK_FREQ_19p2_MHZ;
@@ -1220,10 +1203,23 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
 {
        struct twl4030_platform_data    *pdata = client->dev.platform_data;
        struct device_node              *node = client->dev.of_node;
+       struct platform_device          *pdev;
        int                             irq_base = 0;
        int                             status;
        unsigned                        i, num_slaves;
 
+       pdev = platform_device_alloc(DRIVER_NAME, -1);
+       if (!pdev) {
+               dev_err(&client->dev, "can't alloc pdev\n");
+               return -ENOMEM;
+       }
+
+       status = platform_device_add(pdev);
+       if (status) {
+               platform_device_put(pdev);
+               return status;
+       }
+
        if (node && !pdata) {
                /*
                 * XXX: Temporary pdata until the information is correctly
@@ -1232,23 +1228,30 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
                pdata = devm_kzalloc(&client->dev,
                                     sizeof(struct twl4030_platform_data),
                                     GFP_KERNEL);
-               if (!pdata)
-                       return -ENOMEM;
+               if (!pdata) {
+                       status = -ENOMEM;
+                       goto free;
+               }
        }
 
        if (!pdata) {
                dev_dbg(&client->dev, "no platform data?\n");
-               return -EINVAL;
+               status = -EINVAL;
+               goto free;
        }
 
+       platform_set_drvdata(pdev, pdata);
+
        if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C) == 0) {
                dev_dbg(&client->dev, "can't talk I2C?\n");
-               return -EIO;
+               status = -EIO;
+               goto free;
        }
 
        if (inuse) {
                dev_dbg(&client->dev, "driver is already in use\n");
-               return -EBUSY;
+               status = -EBUSY;
+               goto free;
        }
 
        if ((id->driver_data) & TWL6030_CLASS) {
@@ -1283,7 +1286,7 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
        inuse = true;
 
        /* setup clock framework */
-       clocks_init(&client->dev, pdata->clock);
+       clocks_init(&pdev->dev, pdata->clock);
 
        /* read TWL IDCODE Register */
        if (twl_id == TWL4030_CLASS_ID) {
@@ -1333,6 +1336,9 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
 fail:
        if (status < 0)
                twl_remove(client);
+free:
+       if (status < 0)
+               platform_device_unregister(pdev);
 
        return status;
 }
index a5999a7..c6259a8 100644 (file)
 #include <asm/io.h>
 #include <asm/irq.h>
 
-#include <plat/board.h>
 #include <plat/mmc.h>
 #include <asm/gpio.h>
 #include <plat/dma.h>
-#include <plat/mux.h>
 #include <plat/fpga.h>
 
 #define        OMAP_MMC_REG_CMD        0x00
index 8e2d81f..38adc33 100644 (file)
@@ -40,7 +40,6 @@
 #include <linux/regulator/consumer.h>
 #include <linux/pm_runtime.h>
 #include <mach/hardware.h>
-#include <plat/board.h>
 #include <plat/mmc.h>
 #include <plat/cpu.h>
 
index 0810ccc..5393c64 100644 (file)
@@ -27,7 +27,6 @@
 
 #include <asm/gpio.h>
 
-#include <mach/gpio-tegra.h>
 #include <mach/sdhci.h>
 
 #include "sdhci-pltfm.h"
index 861ca8f..a7040af 100644 (file)
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
+#include <linux/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
+
 #include <asm/io.h>
-#include <mach/hardware.h>
 #include <asm/sizes.h>
-#include <linux/gpio.h>
-#include <plat/board-ams-delta.h>
+
+#include <mach/board-ams-delta.h>
+
+#include <mach/hardware.h>
 
 /*
  * MTD structure for E3 (Delta)
index c855e7c..d0d1bd4 100644 (file)
@@ -249,20 +249,20 @@ static int nand_dev_ready(struct mtd_info *mtd)
 int bcm_umi_nand_inithw(void)
 {
        /* Configure nand timing parameters */
-       REG_UMI_NAND_TCR &= ~0x7ffff;
-       REG_UMI_NAND_TCR |= HW_CFG_NAND_TCR;
+       writel(readl(&REG_UMI_NAND_TCR) & ~0x7ffff, &REG_UMI_NAND_TCR);
+       writel(readl(&REG_UMI_NAND_TCR) | HW_CFG_NAND_TCR, &REG_UMI_NAND_TCR);
 
 #if !defined(CONFIG_MTD_NAND_BCM_UMI_HWCS)
        /* enable software control of CS */
-       REG_UMI_NAND_TCR |= REG_UMI_NAND_TCR_CS_SWCTRL;
+       writel(readl(&REG_UMI_NAND_TCR) | REG_UMI_NAND_TCR_CS_SWCTRL, &REG_UMI_NAND_TCR);
 #endif
 
        /* keep NAND chip select asserted */
-       REG_UMI_NAND_RCSR |= REG_UMI_NAND_RCSR_CS_ASSERTED;
+       writel(readl(&REG_UMI_NAND_RCSR) | REG_UMI_NAND_RCSR_CS_ASSERTED, &REG_UMI_NAND_RCSR);
 
-       REG_UMI_NAND_TCR &= ~REG_UMI_NAND_TCR_WORD16;
+       writel(readl(&REG_UMI_NAND_TCR) & ~REG_UMI_NAND_TCR_WORD16, &REG_UMI_NAND_TCR);
        /* enable writes to flash */
-       REG_UMI_MMD_ICR |= REG_UMI_MMD_ICR_FLASH_WP;
+       writel(readl(&REG_UMI_MMD_ICR) | REG_UMI_MMD_ICR_FLASH_WP, &REG_UMI_MMD_ICR);
 
        writel(NAND_CMD_RESET, bcm_umi_io_base + REG_NAND_CMD_OFFSET);
        nand_bcm_umi_wait_till_ready();
index 198b304..d901866 100644 (file)
@@ -17,7 +17,7 @@
 /* ---- Include Files ---------------------------------------------------- */
 #include <mach/reg_umi.h>
 #include <mach/reg_nand.h>
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
 
 /* ---- Constants and Types ---------------------------------------------- */
 #if (CFG_GLOBAL_CHIP_FAMILY == CFG_GLOBAL_CHIP_FAMILY_BCMRING)
@@ -48,7 +48,7 @@ int nand_bcm_umi_bch_correct_page(uint8_t *datap, uint8_t *readEccData,
 /* Check in device is ready */
 static inline int nand_bcm_umi_dev_ready(void)
 {
-       return REG_UMI_NAND_RCSR & REG_UMI_NAND_RCSR_RDY;
+       return readl(&REG_UMI_NAND_RCSR) & REG_UMI_NAND_RCSR_RDY;
 }
 
 /* Wait until device is ready */
@@ -62,10 +62,11 @@ static inline void nand_bcm_umi_wait_till_ready(void)
 static inline void nand_bcm_umi_hamming_enable_hwecc(void)
 {
        /* disable and reset ECC, 512 byte page */
-       REG_UMI_NAND_ECC_CSR &= ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE |
-               REG_UMI_NAND_ECC_CSR_256BYTE);
+       writel(readl(&REG_UMI_NAND_ECC_CSR) & ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE |
+               REG_UMI_NAND_ECC_CSR_256BYTE), &REG_UMI_NAND_ECC_CSR);
        /* enable ECC */
-       REG_UMI_NAND_ECC_CSR |= REG_UMI_NAND_ECC_CSR_ECC_ENABLE;
+       writel(readl(&REG_UMI_NAND_ECC_CSR) | REG_UMI_NAND_ECC_CSR_ECC_ENABLE,
+               &REG_UMI_NAND_ECC_CSR);
 }
 
 #if NAND_ECC_BCH
@@ -76,18 +77,18 @@ static inline void nand_bcm_umi_hamming_enable_hwecc(void)
 static inline void nand_bcm_umi_bch_enable_read_hwecc(void)
 {
        /* disable and reset ECC */
-       REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID;
+       writel(REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID, &REG_UMI_BCH_CTRL_STATUS);
        /* Turn on ECC */
-       REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN;
+       writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN, &REG_UMI_BCH_CTRL_STATUS);
 }
 
 /* Enable BCH Write ECC */
 static inline void nand_bcm_umi_bch_enable_write_hwecc(void)
 {
        /* disable and reset ECC */
-       REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID;
+       writel(REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID, &REG_UMI_BCH_CTRL_STATUS);
        /* Turn on ECC */
-       REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN;
+       writel(REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN, &REG_UMI_BCH_CTRL_STATUS);
 }
 
 /* Config number of BCH ECC bytes */
@@ -99,9 +100,9 @@ static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes)
        uint32_t numBits = numEccBytes * 8;
 
        /* disable and reset ECC */
-       REG_UMI_BCH_CTRL_STATUS =
-           REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID |
-           REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID;
+       writel(REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID |
+              REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID,
+              &REG_UMI_BCH_CTRL_STATUS);
 
        /* Every correctible bit requires 13 ECC bits */
        tValue = (uint32_t) (numBits / ECC_BITS_PER_CORRECTABLE_BIT);
@@ -113,23 +114,21 @@ static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes)
        kValue = nValue - (tValue * ECC_BITS_PER_CORRECTABLE_BIT);
 
        /* Write the settings */
-       REG_UMI_BCH_N = nValue;
-       REG_UMI_BCH_T = tValue;
-       REG_UMI_BCH_K = kValue;
+       writel(nValue, &REG_UMI_BCH_N);
+       writel(tValue, &REG_UMI_BCH_T);
+       writel(kValue, &REG_UMI_BCH_K);
 }
 
 /* Pause during ECC read calculation to skip bytes in OOB */
 static inline void nand_bcm_umi_bch_pause_read_ecc_calc(void)
 {
-       REG_UMI_BCH_CTRL_STATUS =
-           REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN |
-           REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC;
+       writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN | REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC, &REG_UMI_BCH_CTRL_STATUS);
 }
 
 /* Resume during ECC read calculation after skipping bytes in OOB */
 static inline void nand_bcm_umi_bch_resume_read_ecc_calc(void)
 {
-       REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN;
+       writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN, &REG_UMI_BCH_CTRL_STATUS);
 }
 
 /* Poll read ECC calc to check when hardware completes */
@@ -139,7 +138,7 @@ static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void)
 
        do {
                /* wait for ECC to be valid */
-               regVal = REG_UMI_BCH_CTRL_STATUS;
+               regVal = readl(&REG_UMI_BCH_CTRL_STATUS);
        } while ((regVal & REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID) == 0);
 
        return regVal;
@@ -149,7 +148,7 @@ static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void)
 static inline void nand_bcm_umi_bch_poll_write_ecc_calc(void)
 {
        /* wait for ECC to be valid */
-       while ((REG_UMI_BCH_CTRL_STATUS & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID)
+       while ((readl(&REG_UMI_BCH_CTRL_STATUS) & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID)
               == 0)
                ;
 }
@@ -170,9 +169,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
        if (pageSize != NAND_DATA_ACCESS_SIZE) {
                /* skip BI */
 #if defined(__KERNEL__) && !defined(STANDALONE)
-               *oobp++ = REG_NAND_DATA8;
+               *oobp++ = readb(&REG_NAND_DATA8);
 #else
-               REG_NAND_DATA8;
+               readb(&REG_NAND_DATA8);
 #endif
                numToRead--;
        }
@@ -180,9 +179,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
        while (numToRead > numEccBytes) {
                /* skip free oob region */
 #if defined(__KERNEL__) && !defined(STANDALONE)
-               *oobp++ = REG_NAND_DATA8;
+               *oobp++ = readb(&REG_NAND_DATA8);
 #else
-               REG_NAND_DATA8;
+               readb(&REG_NAND_DATA8);
 #endif
                numToRead--;
        }
@@ -193,11 +192,11 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
 
                while (numToRead > 11) {
 #if defined(__KERNEL__) && !defined(STANDALONE)
-                       *oobp = REG_NAND_DATA8;
+                       *oobp = readb(&REG_NAND_DATA8);
                        eccCalc[eccPos++] = *oobp;
                        oobp++;
 #else
-                       eccCalc[eccPos++] = REG_NAND_DATA8;
+                       eccCalc[eccPos++] = readb(&REG_NAND_DATA8);
 #endif
                        numToRead--;
                }
@@ -207,9 +206,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
                if (numToRead == 11) {
                        /* read BI */
 #if defined(__KERNEL__) && !defined(STANDALONE)
-                       *oobp++ = REG_NAND_DATA8;
+                       *oobp++ = readb(&REG_NAND_DATA8);
 #else
-                       REG_NAND_DATA8;
+                       readb(&REG_NAND_DATA8);
 #endif
                        numToRead--;
                }
@@ -219,11 +218,11 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
        nand_bcm_umi_bch_resume_read_ecc_calc();
        while (numToRead) {
 #if defined(__KERNEL__) && !defined(STANDALONE)
-               *oobp = REG_NAND_DATA8;
+               *oobp = readb(&REG_NAND_DATA8);
                eccCalc[eccPos++] = *oobp;
                oobp++;
 #else
-               eccCalc[eccPos++] = REG_NAND_DATA8;
+               eccCalc[eccPos++] = readb(&REG_NAND_DATA8);
 #endif
                numToRead--;
        }
@@ -255,7 +254,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
        if (pageSize == NAND_DATA_ACCESS_SIZE) {
                /* Now fill in the ECC bytes */
                if (numEccBytes >= 13)
-                       eccVal = REG_UMI_BCH_WR_ECC_3;
+                       eccVal = readl(&REG_UMI_BCH_WR_ECC_3);
 
                /* Usually we skip CM in oob[0,1] */
                NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[0],
@@ -268,7 +267,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
                        eccVal & 0xff); /* ECC 12 */
 
                if (numEccBytes >= 9)
-                       eccVal = REG_UMI_BCH_WR_ECC_2;
+                       eccVal = readl(&REG_UMI_BCH_WR_ECC_2);
 
                NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[3],
                        (eccVal >> 24) & 0xff); /* ECC11 */
@@ -281,7 +280,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
 
                /* Now fill in the ECC bytes */
                if (numEccBytes >= 13)
-                       eccVal = REG_UMI_BCH_WR_ECC_3;
+                       eccVal = readl(&REG_UMI_BCH_WR_ECC_3);
 
                /* Usually skip CM in oob[1,2] */
                NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[1],
@@ -294,7 +293,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
                        eccVal & 0xff); /* ECC12 */
 
                if (numEccBytes >= 9)
-                       eccVal = REG_UMI_BCH_WR_ECC_2;
+                       eccVal = readl(&REG_UMI_BCH_WR_ECC_2);
 
                NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[4],
                        (eccVal >> 24) & 0xff); /* ECC11 */
@@ -309,7 +308,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
                eccVal & 0xff); /* ECC8 */
 
        if (numEccBytes >= 5)
-               eccVal = REG_UMI_BCH_WR_ECC_1;
+               eccVal = readl(&REG_UMI_BCH_WR_ECC_1);
 
        NAND_BCM_UMI_ECC_WRITE(numEccBytes, 8, &oobp[8],
                (eccVal >> 24) & 0xff); /* ECC7 */
@@ -321,7 +320,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
                eccVal & 0xff); /* ECC4 */
 
        if (numEccBytes >= 1)
-               eccVal = REG_UMI_BCH_WR_ECC_0;
+               eccVal = readl(&REG_UMI_BCH_WR_ECC_0);
 
        NAND_BCM_UMI_ECC_WRITE(numEccBytes, 4, &oobp[12],
                (eccVal >> 24) & 0xff); /* ECC3 */
index ac4fd75..fc81112 100644 (file)
@@ -29,7 +29,7 @@
 
 #include <plat/dma.h>
 #include <plat/gpmc.h>
-#include <plat/nand.h>
+#include <linux/platform_data/mtd-nand-omap2.h>
 
 #define        DRIVER_NAME     "omap2-nand"
 #define        OMAP_NAND_TIMEOUT_MS    5000
 #define P4e_s(a)       (TF(a & NAND_Ecc_P4e)           << 0)
 #define P4o_s(a)       (TF(a & NAND_Ecc_P4o)           << 1)
 
+#define        PREFETCH_CONFIG1_CS_SHIFT       24
+#define        ECC_CONFIG_CS_SHIFT             1
+#define        CS_MASK                         0x7
+#define        ENABLE_PREFETCH                 (0x1 << 7)
+#define        DMA_MPU_MODE_SHIFT              2
+#define        ECCSIZE1_SHIFT                  22
+#define        ECC1RESULTSIZE                  0x1
+#define        ECCCLEAR                        0x100
+#define        ECC1                            0x1
+
 /* oob info generated runtime depending on ecc algorithm and layout selected */
 static struct nand_ecclayout omap_oobinfo;
 /* Define some generic bad / good block scan pattern which are used
@@ -124,15 +134,18 @@ struct omap_nand_info {
 
        int                             gpmc_cs;
        unsigned long                   phys_base;
+       unsigned long                   mem_size;
        struct completion               comp;
        struct dma_chan                 *dma;
-       int                             gpmc_irq;
+       int                             gpmc_irq_fifo;
+       int                             gpmc_irq_count;
        enum {
                OMAP_NAND_IO_READ = 0,  /* read */
                OMAP_NAND_IO_WRITE,     /* write */
        } iomode;
        u_char                          *buf;
        int                                     buf_len;
+       struct gpmc_nand_regs           reg;
 
 #ifdef CONFIG_MTD_NAND_OMAP_BCH
        struct bch_control             *bch;
@@ -141,6 +154,63 @@ struct omap_nand_info {
 };
 
 /**
+ * omap_prefetch_enable - configures and starts prefetch transfer
+ * @cs: cs (chip select) number
+ * @fifo_th: fifo threshold to be used for read/ write
+ * @dma_mode: dma mode enable (1) or disable (0)
+ * @u32_count: number of bytes to be transferred
+ * @is_write: prefetch read(0) or write post(1) mode
+ */
+static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode,
+       unsigned int u32_count, int is_write, struct omap_nand_info *info)
+{
+       u32 val;
+
+       if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
+               return -1;
+
+       if (readl(info->reg.gpmc_prefetch_control))
+               return -EBUSY;
+
+       /* Set the amount of bytes to be prefetched */
+       writel(u32_count, info->reg.gpmc_prefetch_config2);
+
+       /* Set dma/mpu mode, the prefetch read / post write and
+        * enable the engine. Set which cs is has requested for.
+        */
+       val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) |
+               PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH |
+               (dma_mode << DMA_MPU_MODE_SHIFT) | (0x1 & is_write));
+       writel(val, info->reg.gpmc_prefetch_config1);
+
+       /*  Start the prefetch engine */
+       writel(0x1, info->reg.gpmc_prefetch_control);
+
+       return 0;
+}
+
+/**
+ * omap_prefetch_reset - disables and stops the prefetch engine
+ */
+static int omap_prefetch_reset(int cs, struct omap_nand_info *info)
+{
+       u32 config1;
+
+       /* check if the same module/cs is trying to reset */
+       config1 = readl(info->reg.gpmc_prefetch_config1);
+       if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs)
+               return -EINVAL;
+
+       /* Stop the PFPW engine */
+       writel(0x0, info->reg.gpmc_prefetch_control);
+
+       /* Reset/disable the PFPW engine */
+       writel(0x0, info->reg.gpmc_prefetch_config1);
+
+       return 0;
+}
+
+/**
  * omap_hwcontrol - hardware specific access to control-lines
  * @mtd: MTD device structure
  * @cmd: command to device
@@ -158,13 +228,13 @@ static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 
        if (cmd != NAND_CMD_NONE) {
                if (ctrl & NAND_CLE)
-                       gpmc_nand_write(info->gpmc_cs, GPMC_NAND_COMMAND, cmd);
+                       writeb(cmd, info->reg.gpmc_nand_command);
 
                else if (ctrl & NAND_ALE)
-                       gpmc_nand_write(info->gpmc_cs, GPMC_NAND_ADDRESS, cmd);
+                       writeb(cmd, info->reg.gpmc_nand_address);
 
                else /* NAND_NCE */
-                       gpmc_nand_write(info->gpmc_cs, GPMC_NAND_DATA, cmd);
+                       writeb(cmd, info->reg.gpmc_nand_data);
        }
 }
 
@@ -198,7 +268,8 @@ static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
                iowrite8(*p++, info->nand.IO_ADDR_W);
                /* wait until buffer is available for write */
                do {
-                       status = gpmc_read_status(GPMC_STATUS_BUFFER);
+                       status = readl(info->reg.gpmc_status) &
+                                       GPMC_STATUS_BUFF_EMPTY;
                } while (!status);
        }
 }
@@ -235,7 +306,8 @@ static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
                iowrite16(*p++, info->nand.IO_ADDR_W);
                /* wait until buffer is available for write */
                do {
-                       status = gpmc_read_status(GPMC_STATUS_BUFFER);
+                       status = readl(info->reg.gpmc_status) &
+                                       GPMC_STATUS_BUFF_EMPTY;
                } while (!status);
        }
 }
@@ -265,8 +337,8 @@ static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
        }
 
        /* configure and start prefetch transfer */
-       ret = gpmc_prefetch_enable(info->gpmc_cs,
-                       PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0);
+       ret = omap_prefetch_enable(info->gpmc_cs,
+                       PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info);
        if (ret) {
                /* PFPW engine is busy, use cpu copy method */
                if (info->nand.options & NAND_BUSWIDTH_16)
@@ -275,14 +347,15 @@ static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
                        omap_read_buf8(mtd, (u_char *)p, len);
        } else {
                do {
-                       r_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
+                       r_count = readl(info->reg.gpmc_prefetch_status);
+                       r_count = GPMC_PREFETCH_STATUS_FIFO_CNT(r_count);
                        r_count = r_count >> 2;
                        ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
                        p += r_count;
                        len -= r_count << 2;
                } while (len);
                /* disable and stop the PFPW engine */
-               gpmc_prefetch_reset(info->gpmc_cs);
+               omap_prefetch_reset(info->gpmc_cs, info);
        }
 }
 
@@ -301,6 +374,7 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
        int i = 0, ret = 0;
        u16 *p = (u16 *)buf;
        unsigned long tim, limit;
+       u32 val;
 
        /* take care of subpage writes */
        if (len % 2 != 0) {
@@ -310,8 +384,8 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
        }
 
        /*  configure and start prefetch transfer */
-       ret = gpmc_prefetch_enable(info->gpmc_cs,
-                       PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1);
+       ret = omap_prefetch_enable(info->gpmc_cs,
+                       PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info);
        if (ret) {
                /* PFPW engine is busy, use cpu copy method */
                if (info->nand.options & NAND_BUSWIDTH_16)
@@ -320,7 +394,8 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
                        omap_write_buf8(mtd, (u_char *)p, len);
        } else {
                while (len) {
-                       w_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
+                       w_count = readl(info->reg.gpmc_prefetch_status);
+                       w_count = GPMC_PREFETCH_STATUS_FIFO_CNT(w_count);
                        w_count = w_count >> 1;
                        for (i = 0; (i < w_count) && len; i++, len -= 2)
                                iowrite16(*p++, info->nand.IO_ADDR_W);
@@ -329,11 +404,14 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
                tim = 0;
                limit = (loops_per_jiffy *
                                        msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
-               while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
+               do {
                        cpu_relax();
+                       val = readl(info->reg.gpmc_prefetch_status);
+                       val = GPMC_PREFETCH_STATUS_COUNT(val);
+               } while (val && (tim++ < limit));
 
                /* disable and stop the PFPW engine */
-               gpmc_prefetch_reset(info->gpmc_cs);
+               omap_prefetch_reset(info->gpmc_cs, info);
        }
 }
 
@@ -365,6 +443,7 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
        unsigned long tim, limit;
        unsigned n;
        int ret;
+       u32 val;
 
        if (addr >= high_memory) {
                struct page *p1;
@@ -396,9 +475,9 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
        tx->callback_param = &info->comp;
        dmaengine_submit(tx);
 
-       /* configure and start prefetch transfer */
-       ret = gpmc_prefetch_enable(info->gpmc_cs,
-               PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write);
+       /*  configure and start prefetch transfer */
+       ret = omap_prefetch_enable(info->gpmc_cs,
+               PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info);
        if (ret)
                /* PFPW engine is busy, use cpu copy method */
                goto out_copy_unmap;
@@ -410,11 +489,15 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
        wait_for_completion(&info->comp);
        tim = 0;
        limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
-       while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
+
+       do {
                cpu_relax();
+               val = readl(info->reg.gpmc_prefetch_status);
+               val = GPMC_PREFETCH_STATUS_COUNT(val);
+       } while (val && (tim++ < limit));
 
        /* disable and stop the PFPW engine */
-       gpmc_prefetch_reset(info->gpmc_cs);
+       omap_prefetch_reset(info->gpmc_cs, info);
 
        dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
        return 0;
@@ -471,13 +554,12 @@ static irqreturn_t omap_nand_irq(int this_irq, void *dev)
 {
        struct omap_nand_info *info = (struct omap_nand_info *) dev;
        u32 bytes;
-       u32 irq_stat;
 
-       irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS);
-       bytes = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
+       bytes = readl(info->reg.gpmc_prefetch_status);
+       bytes = GPMC_PREFETCH_STATUS_FIFO_CNT(bytes);
        bytes = bytes  & 0xFFFC; /* io in multiple of 4 bytes */
        if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
-               if (irq_stat & 0x2)
+               if (this_irq == info->gpmc_irq_count)
                        goto done;
 
                if (info->buf_len && (info->buf_len < bytes))
@@ -494,20 +576,17 @@ static irqreturn_t omap_nand_irq(int this_irq, void *dev)
                                                (u32 *)info->buf, bytes >> 2);
                info->buf = info->buf + bytes;
 
-               if (irq_stat & 0x2)
+               if (this_irq == info->gpmc_irq_count)
                        goto done;
        }
-       gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
 
        return IRQ_HANDLED;
 
 done:
        complete(&info->comp);
-       /* disable irq */
-       gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, 0);
 
-       /* clear status */
-       gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
+       disable_irq_nosync(info->gpmc_irq_fifo);
+       disable_irq_nosync(info->gpmc_irq_count);
 
        return IRQ_HANDLED;
 }
@@ -534,22 +613,22 @@ static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
        init_completion(&info->comp);
 
        /*  configure and start prefetch transfer */
-       ret = gpmc_prefetch_enable(info->gpmc_cs,
-                       PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0);
+       ret = omap_prefetch_enable(info->gpmc_cs,
+                       PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info);
        if (ret)
                /* PFPW engine is busy, use cpu copy method */
                goto out_copy;
 
        info->buf_len = len;
-       /* enable irq */
-       gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
-               (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
+
+       enable_irq(info->gpmc_irq_count);
+       enable_irq(info->gpmc_irq_fifo);
 
        /* waiting for read to complete */
        wait_for_completion(&info->comp);
 
        /* disable and stop the PFPW engine */
-       gpmc_prefetch_reset(info->gpmc_cs);
+       omap_prefetch_reset(info->gpmc_cs, info);
        return;
 
 out_copy:
@@ -572,6 +651,7 @@ static void omap_write_buf_irq_pref(struct mtd_info *mtd,
                                                struct omap_nand_info, mtd);
        int ret = 0;
        unsigned long tim, limit;
+       u32 val;
 
        if (len <= mtd->oobsize) {
                omap_write_buf_pref(mtd, buf, len);
@@ -583,27 +663,31 @@ static void omap_write_buf_irq_pref(struct mtd_info *mtd,
        init_completion(&info->comp);
 
        /* configure and start prefetch transfer : size=24 */
-       ret = gpmc_prefetch_enable(info->gpmc_cs,
-                       (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1);
+       ret = omap_prefetch_enable(info->gpmc_cs,
+               (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info);
        if (ret)
                /* PFPW engine is busy, use cpu copy method */
                goto out_copy;
 
        info->buf_len = len;
-       /* enable irq */
-       gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
-                       (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
+
+       enable_irq(info->gpmc_irq_count);
+       enable_irq(info->gpmc_irq_fifo);
 
        /* waiting for write to complete */
        wait_for_completion(&info->comp);
+
        /* wait for data to flushed-out before reset the prefetch */
        tim = 0;
        limit = (loops_per_jiffy *  msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
-       while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
+       do {
+               val = readl(info->reg.gpmc_prefetch_status);
+               val = GPMC_PREFETCH_STATUS_COUNT(val);
                cpu_relax();
+       } while (val && (tim++ < limit));
 
        /* disable and stop the PFPW engine */
-       gpmc_prefetch_reset(info->gpmc_cs);
+       omap_prefetch_reset(info->gpmc_cs, info);
        return;
 
 out_copy:
@@ -843,7 +927,20 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 {
        struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
                                                        mtd);
-       return gpmc_calculate_ecc(info->gpmc_cs, dat, ecc_code);
+       u32 val;
+
+       val = readl(info->reg.gpmc_ecc_config);
+       if (((val >> ECC_CONFIG_CS_SHIFT)  & ~CS_MASK) != info->gpmc_cs)
+               return -EINVAL;
+
+       /* read ecc result */
+       val = readl(info->reg.gpmc_ecc1_result);
+       *ecc_code++ = val;          /* P128e, ..., P1e */
+       *ecc_code++ = val >> 16;    /* P128o, ..., P1o */
+       /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
+       *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
+
+       return 0;
 }
 
 /**
@@ -857,8 +954,34 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
                                                        mtd);
        struct nand_chip *chip = mtd->priv;
        unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
+       u32 val;
+
+       /* clear ecc and enable bits */
+       val = ECCCLEAR | ECC1;
+       writel(val, info->reg.gpmc_ecc_control);
+
+       /* program ecc and result sizes */
+       val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |
+                        ECC1RESULTSIZE);
+       writel(val, info->reg.gpmc_ecc_size_config);
 
-       gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size);
+       switch (mode) {
+       case NAND_ECC_READ:
+       case NAND_ECC_WRITE:
+               writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
+               break;
+       case NAND_ECC_READSYN:
+               writel(ECCCLEAR, info->reg.gpmc_ecc_control);
+               break;
+       default:
+               dev_info(&info->pdev->dev,
+                       "error: unrecognized Mode[%d]!\n", mode);
+               break;
+       }
+
+       /* (ECC 16 or 8 bit col) | ( CS  )  | ECC Enable */
+       val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
+       writel(val, info->reg.gpmc_ecc_config);
 }
 
 /**
@@ -886,10 +1009,9 @@ static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
        else
                timeo += (HZ * 20) / 1000;
 
-       gpmc_nand_write(info->gpmc_cs,
-                       GPMC_NAND_COMMAND, (NAND_CMD_STATUS & 0xFF));
+       writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command);
        while (time_before(jiffies, timeo)) {
-               status = gpmc_nand_read(info->gpmc_cs, GPMC_NAND_DATA);
+               status = readb(info->reg.gpmc_nand_data);
                if (status & NAND_STATUS_READY)
                        break;
                cond_resched();
@@ -909,22 +1031,13 @@ static int omap_dev_ready(struct mtd_info *mtd)
        struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
                                                        mtd);
 
-       val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
+       val = readl(info->reg.gpmc_status);
+
        if ((val & 0x100) == 0x100) {
-               /* Clear IRQ Interrupt */
-               val |= 0x100;
-               val &= ~(0x0);
-               gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, val);
+               return 1;
        } else {
-               unsigned int cnt = 0;
-               while (cnt++ < 0x1FF) {
-                       if  ((val & 0x100) == 0x100)
-                               return 0;
-                       val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
-               }
+               return 0;
        }
-
-       return 1;
 }
 
 #ifdef CONFIG_MTD_NAND_OMAP_BCH
@@ -1155,6 +1268,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
        int                             i, offset;
        dma_cap_mask_t mask;
        unsigned sig;
+       struct resource                 *res;
 
        pdata = pdev->dev.platform_data;
        if (pdata == NULL) {
@@ -1174,7 +1288,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
        info->pdev = pdev;
 
        info->gpmc_cs           = pdata->cs;
-       info->phys_base         = pdata->phys_base;
+       info->reg               = pdata->reg;
 
        info->mtd.priv          = &info->nand;
        info->mtd.name          = dev_name(&pdev->dev);
@@ -1183,16 +1297,23 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
        info->nand.options      = pdata->devsize;
        info->nand.options      |= NAND_SKIP_BBTSCAN;
 
-       /* NAND write protect off */
-       gpmc_cs_configure(info->gpmc_cs, GPMC_CONFIG_WP, 0);
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       if (res == NULL) {
+               err = -EINVAL;
+               dev_err(&pdev->dev, "error getting memory resource\n");
+               goto out_free_info;
+       }
+
+       info->phys_base = res->start;
+       info->mem_size = resource_size(res);
 
-       if (!request_mem_region(info->phys_base, NAND_IO_SIZE,
+       if (!request_mem_region(info->phys_base, info->mem_size,
                                pdev->dev.driver->name)) {
                err = -EBUSY;
                goto out_free_info;
        }
 
-       info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE);
+       info->nand.IO_ADDR_R = ioremap(info->phys_base, info->mem_size);
        if (!info->nand.IO_ADDR_R) {
                err = -ENOMEM;
                goto out_release_mem_region;
@@ -1265,17 +1386,39 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
                break;
 
        case NAND_OMAP_PREFETCH_IRQ:
-               err = request_irq(pdata->gpmc_irq,
-                               omap_nand_irq, IRQF_SHARED, "gpmc-nand", info);
+               info->gpmc_irq_fifo = platform_get_irq(pdev, 0);
+               if (info->gpmc_irq_fifo <= 0) {
+                       dev_err(&pdev->dev, "error getting fifo irq\n");
+                       err = -ENODEV;
+                       goto out_release_mem_region;
+               }
+               err = request_irq(info->gpmc_irq_fifo,  omap_nand_irq,
+                                       IRQF_SHARED, "gpmc-nand-fifo", info);
                if (err) {
                        dev_err(&pdev->dev, "requesting irq(%d) error:%d",
-                                                       pdata->gpmc_irq, err);
+                                               info->gpmc_irq_fifo, err);
+                       info->gpmc_irq_fifo = 0;
+                       goto out_release_mem_region;
+               }
+
+               info->gpmc_irq_count = platform_get_irq(pdev, 1);
+               if (info->gpmc_irq_count <= 0) {
+                       dev_err(&pdev->dev, "error getting count irq\n");
+                       err = -ENODEV;
+                       goto out_release_mem_region;
+               }
+               err = request_irq(info->gpmc_irq_count, omap_nand_irq,
+                                       IRQF_SHARED, "gpmc-nand-count", info);
+               if (err) {
+                       dev_err(&pdev->dev, "requesting irq(%d) error:%d",
+                                               info->gpmc_irq_count, err);
+                       info->gpmc_irq_count = 0;
                        goto out_release_mem_region;
-               } else {
-                       info->gpmc_irq       = pdata->gpmc_irq;
-                       info->nand.read_buf  = omap_read_buf_irq_pref;
-                       info->nand.write_buf = omap_write_buf_irq_pref;
                }
+
+               info->nand.read_buf  = omap_read_buf_irq_pref;
+               info->nand.write_buf = omap_write_buf_irq_pref;
+
                break;
 
        default:
@@ -1363,7 +1506,11 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
 out_release_mem_region:
        if (info->dma)
                dma_release_channel(info->dma);
-       release_mem_region(info->phys_base, NAND_IO_SIZE);
+       if (info->gpmc_irq_count > 0)
+               free_irq(info->gpmc_irq_count, info);
+       if (info->gpmc_irq_fifo > 0)
+               free_irq(info->gpmc_irq_fifo, info);
+       release_mem_region(info->phys_base, info->mem_size);
 out_free_info:
        kfree(info);
 
@@ -1381,8 +1528,10 @@ static int omap_nand_remove(struct platform_device *pdev)
        if (info->dma)
                dma_release_channel(info->dma);
 
-       if (info->gpmc_irq)
-               free_irq(info->gpmc_irq, info);
+       if (info->gpmc_irq_count > 0)
+               free_irq(info->gpmc_irq_count, info);
+       if (info->gpmc_irq_fifo > 0)
+               free_irq(info->gpmc_irq_fifo, info);
 
        /* Release NAND device, its internal structures and partitions */
        nand_release(&info->mtd);
index 398a827..1961be9 100644 (file)
 
 #include <asm/mach/flash.h>
 #include <plat/gpmc.h>
-#include <plat/onenand.h>
+#include <linux/platform_data/mtd-onenand-omap2.h>
 #include <asm/gpio.h>
 
 #include <plat/dma.h>
-
-#include <plat/board.h>
+#include <plat/cpu.h>
 
 #define DRIVER_NAME "omap2-onenand"
 
-#define ONENAND_IO_SIZE                SZ_128K
 #define ONENAND_BUFRAM_SIZE    (1024 * 5)
 
 struct omap2_onenand {
        struct platform_device *pdev;
        int gpmc_cs;
        unsigned long phys_base;
+       unsigned int mem_size;
        int gpio_irq;
        struct mtd_info mtd;
        struct onenand_chip onenand;
@@ -626,6 +625,7 @@ static int __devinit omap2_onenand_probe(struct platform_device *pdev)
        struct omap2_onenand *c;
        struct onenand_chip *this;
        int r;
+       struct resource *res;
 
        pdata = pdev->dev.platform_data;
        if (pdata == NULL) {
@@ -647,20 +647,24 @@ static int __devinit omap2_onenand_probe(struct platform_device *pdev)
                c->gpio_irq = 0;
        }
 
-       r = gpmc_cs_request(c->gpmc_cs, ONENAND_IO_SIZE, &c->phys_base);
-       if (r < 0) {
-               dev_err(&pdev->dev, "Cannot request GPMC CS\n");
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       if (res == NULL) {
+               r = -EINVAL;
+               dev_err(&pdev->dev, "error getting memory resource\n");
                goto err_kfree;
        }
 
-       if (request_mem_region(c->phys_base, ONENAND_IO_SIZE,
+       c->phys_base = res->start;
+       c->mem_size = resource_size(res);
+
+       if (request_mem_region(c->phys_base, c->mem_size,
                               pdev->dev.driver->name) == NULL) {
-               dev_err(&pdev->dev, "Cannot reserve memory region at 0x%08lx, "
-                       "size: 0x%x\n", c->phys_base, ONENAND_IO_SIZE);
+               dev_err(&pdev->dev, "Cannot reserve memory region at 0x%08lx, size: 0x%x\n",
+                                               c->phys_base, c->mem_size);
                r = -EBUSY;
-               goto err_free_cs;
+               goto err_kfree;
        }
-       c->onenand.base = ioremap(c->phys_base, ONENAND_IO_SIZE);
+       c->onenand.base = ioremap(c->phys_base, c->mem_size);
        if (c->onenand.base == NULL) {
                r = -ENOMEM;
                goto err_release_mem_region;
@@ -776,9 +780,7 @@ err_release_gpio:
 err_iounmap:
        iounmap(c->onenand.base);
 err_release_mem_region:
-       release_mem_region(c->phys_base, ONENAND_IO_SIZE);
-err_free_cs:
-       gpmc_cs_free(c->gpmc_cs);
+       release_mem_region(c->phys_base, c->mem_size);
 err_kfree:
        kfree(c);
 
@@ -800,7 +802,7 @@ static int __devexit omap2_onenand_remove(struct platform_device *pdev)
                gpio_free(c->gpio_irq);
        }
        iounmap(c->onenand.base);
-       release_mem_region(c->phys_base, ONENAND_IO_SIZE);
+       release_mem_region(c->phys_base, c->mem_size);
        gpmc_cs_free(c->gpmc_cs);
        kfree(c);
 
index df808ac..6a40dd0 100644 (file)
@@ -99,13 +99,13 @@ typedef enum {
  * The SEEQ8005 doesn't like us writing to its registers
  * too quickly.
  */
-static inline void ether3_outb(int v, const void __iomem *r)
+static inline void ether3_outb(int v, void __iomem *r)
 {
        writeb(v, r);
        udelay(1);
 }
 
-static inline void ether3_outw(int v, const void __iomem *r)
+static inline void ether3_outw(int v, void __iomem *r)
 {
        writew(v, r);
        udelay(1);
index 0ad06a3..fa74efe 100644 (file)
@@ -24,7 +24,7 @@
 #include <asm/io.h>
 #include <asm/sizes.h>
 
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/tc.h>
 
 
index cc0f00d..b446c96 100644 (file)
@@ -1,11 +1,8 @@
 /*
  * U300 GPIO module.
  *
- * Copyright (C) 2007-2011 ST-Ericsson AB
+ * Copyright (C) 2007-2012 ST-Ericsson AB
  * License terms: GNU General Public License (GPL) version 2
- * This can driver either of the two basic GPIO cores
- * available in the U300 platforms:
- * COH 901 335   - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0)
  * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
  * Author: Linus Walleij <linus.walleij@linaro.org>
  * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
 #include <linux/slab.h>
 #include <linux/pinctrl/consumer.h>
 #include <linux/pinctrl/pinconf-generic.h>
-#include <mach/gpio-u300.h>
+#include <linux/platform_data/pinctrl-coh901.h>
 #include "pinctrl-coh901.h"
 
+#define U300_GPIO_PORT_STRIDE                          (0x30)
 /*
- * Register definitions for COH 901 335 variant
+ * Control Register 32bit (R/W)
+ * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
+ * gives the number of GPIO pins.
+ * bit 8-2  (mask 0x000001FC) contains the core version ID.
  */
-#define U300_335_PORT_STRIDE                           (0x1C)
-/* Port X Pin Data Register 32bit, this is both input and output (R/W) */
-#define U300_335_PXPDIR                                        (0x00)
-#define U300_335_PXPDOR                                        (0x00)
-/* Port X Pin Config Register 32bit (R/W) */
-#define U300_335_PXPCR                                 (0x04)
-/* This register layout is the same in both blocks */
+#define U300_GPIO_CR                                   (0x00)
+#define U300_GPIO_CR_SYNC_SEL_ENABLE                   (0x00000002UL)
+#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE                        (0x00000001UL)
+#define U300_GPIO_PXPDIR                               (0x04)
+#define U300_GPIO_PXPDOR                               (0x08)
+#define U300_GPIO_PXPCR                                        (0x0C)
 #define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK             (0x0000FFFFUL)
 #define U300_GPIO_PXPCR_PIN_MODE_MASK                  (0x00000003UL)
 #define U300_GPIO_PXPCR_PIN_MODE_SHIFT                 (0x00000002UL)
 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL      (0x00000001UL)
 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN     (0x00000002UL)
 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE    (0x00000003UL)
-/* Port X Interrupt Event Register 32bit (R/W) */
-#define U300_335_PXIEV                                 (0x08)
-/* Port X Interrupt Enable Register 32bit (R/W) */
-#define U300_335_PXIEN                                 (0x0C)
-/* Port X Interrupt Force Register 32bit (R/W) */
-#define U300_335_PXIFR                                 (0x10)
-/* Port X Interrupt Config Register 32bit (R/W) */
-#define U300_335_PXICR                                 (0x14)
-/* This register layout is the same in both blocks */
+#define U300_GPIO_PXPER                                        (0x10)
+#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK       (0x000000FFUL)
+#define U300_GPIO_PXPER_PULL_UP_DISABLE                        (0x00000001UL)
+#define U300_GPIO_PXIEV                                        (0x14)
+#define U300_GPIO_PXIEN                                        (0x18)
+#define U300_GPIO_PXIFR                                        (0x1C)
+#define U300_GPIO_PXICR                                        (0x20)
 #define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK            (0x000000FFUL)
 #define U300_GPIO_PXICR_IRQ_CONFIG_MASK                        (0x00000001UL)
 #define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE                (0x00000000UL)
 #define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE         (0x00000001UL)
-/* Port X Pull-up Enable Register 32bit (R/W) */
-#define U300_335_PXPER                                 (0x18)
-/* This register layout is the same in both blocks */
-#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK       (0x000000FFUL)
-#define U300_GPIO_PXPER_PULL_UP_DISABLE                        (0x00000001UL)
-/* Control Register 32bit (R/W) */
-#define U300_335_CR                                    (0x54)
-#define U300_335_CR_BLOCK_CLOCK_ENABLE                 (0x00000001UL)
-
-/*
- * Register definitions for COH 901 571 / 3 variant
- */
-#define U300_571_PORT_STRIDE                           (0x30)
-/*
- * Control Register 32bit (R/W)
- * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
- * gives the number of GPIO pins.
- * bit 8-2  (mask 0x000001FC) contains the core version ID.
- */
-#define U300_571_CR                                    (0x00)
-#define U300_571_CR_SYNC_SEL_ENABLE                    (0x00000002UL)
-#define U300_571_CR_BLOCK_CLKRQ_ENABLE                 (0x00000001UL)
-/*
- * These registers have the same layout and function as the corresponding
- * COH 901 335 registers, just at different offset.
- */
-#define U300_571_PXPDIR                                        (0x04)
-#define U300_571_PXPDOR                                        (0x08)
-#define U300_571_PXPCR                                 (0x0C)
-#define U300_571_PXPER                                 (0x10)
-#define U300_571_PXIEV                                 (0x14)
-#define U300_571_PXIEN                                 (0x18)
-#define U300_571_PXIFR                                 (0x1C)
-#define U300_571_PXICR                                 (0x20)
 
 /* 8 bits per port, no version has more than 7 ports */
 #define U300_GPIO_PINS_PER_PORT 8
@@ -149,8 +113,6 @@ struct u300_gpio_confdata {
 
 /* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */
 #define BS335_GPIO_NUM_PORTS 7
-/* BS365 has five ports of 8 bits each = GPIO pins 0..39 */
-#define BS365_GPIO_NUM_PORTS 5
 
 #define U300_FLOATING_INPUT { \
        .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
@@ -172,7 +134,6 @@ struct u300_gpio_confdata {
        .outval = 1, \
 }
 
-
 /* Initial configuration */
 static const struct __initconst u300_gpio_confdata
 bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
@@ -255,66 +216,6 @@ bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
        }
 };
 
-static const struct __initconst u300_gpio_confdata
-bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
-       /* Port 0, pins 0-7 */
-       {
-               U300_FLOATING_INPUT,
-               U300_OUTPUT_LOW,
-               U300_FLOATING_INPUT,
-               U300_OUTPUT_LOW,
-               U300_OUTPUT_LOW,
-               U300_OUTPUT_LOW,
-               U300_PULL_UP_INPUT,
-               U300_FLOATING_INPUT,
-       },
-       /* Port 1, pins 0-7 */
-       {
-               U300_OUTPUT_LOW,
-               U300_FLOATING_INPUT,
-               U300_OUTPUT_LOW,
-               U300_FLOATING_INPUT,
-               U300_FLOATING_INPUT,
-               U300_OUTPUT_HIGH,
-               U300_OUTPUT_LOW,
-               U300_OUTPUT_LOW,
-       },
-       /* Port 2, pins 0-7 */
-       {
-               U300_FLOATING_INPUT,
-               U300_PULL_UP_INPUT,
-               U300_OUTPUT_LOW,
-               U300_OUTPUT_LOW,
-               U300_PULL_UP_INPUT,
-               U300_PULL_UP_INPUT,
-               U300_PULL_UP_INPUT,
-               U300_PULL_UP_INPUT,
-       },
-       /* Port 3, pins 0-7 */
-       {
-               U300_PULL_UP_INPUT,
-               U300_PULL_UP_INPUT,
-               U300_PULL_UP_INPUT,
-               U300_PULL_UP_INPUT,
-               U300_PULL_UP_INPUT,
-               U300_PULL_UP_INPUT,
-               U300_PULL_UP_INPUT,
-               U300_PULL_UP_INPUT,
-       },
-       /* Port 4, pins 0-7 */
-       {
-               U300_PULL_UP_INPUT,
-               U300_PULL_UP_INPUT,
-               U300_PULL_UP_INPUT,
-               U300_PULL_UP_INPUT,
-               /* These 4 pins doesn't exist on DB3210 */
-               U300_OUTPUT_LOW,
-               U300_OUTPUT_LOW,
-               U300_OUTPUT_LOW,
-               U300_OUTPUT_LOW,
-       }
-};
-
 /**
  * to_u300_gpio() - get the pointer to u300_gpio
  * @chip: the gpio chip member of the structure u300_gpio
@@ -716,13 +617,7 @@ static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio,
                        const struct u300_gpio_confdata *conf;
                        int offset = (i*8) + j;
 
-                       if (plat->variant == U300_GPIO_COH901571_3_BS335)
-                               conf = &bs335_gpio_config[i][j];
-                       else if (plat->variant == U300_GPIO_COH901571_3_BS365)
-                               conf = &bs365_gpio_config[i][j];
-                       else
-                               break;
-
+                       conf = &bs335_gpio_config[i][j];
                        u300_gpio_init_pin(gpio, offset, conf);
                }
        }
@@ -796,50 +691,27 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
                goto err_no_ioremap;
        }
 
-       if (plat->variant == U300_GPIO_COH901335) {
-               dev_info(gpio->dev,
-                        "initializing GPIO Controller COH 901 335\n");
-               gpio->stride = U300_335_PORT_STRIDE;
-               gpio->pcr = U300_335_PXPCR;
-               gpio->dor = U300_335_PXPDOR;
-               gpio->dir = U300_335_PXPDIR;
-               gpio->per = U300_335_PXPER;
-               gpio->icr = U300_335_PXICR;
-               gpio->ien = U300_335_PXIEN;
-               gpio->iev = U300_335_PXIEV;
-               ifr = U300_335_PXIFR;
-
-               /* Turn on the GPIO block */
-               writel(U300_335_CR_BLOCK_CLOCK_ENABLE,
-                      gpio->base + U300_335_CR);
-       } else if (plat->variant == U300_GPIO_COH901571_3_BS335 ||
-                  plat->variant == U300_GPIO_COH901571_3_BS365) {
-               dev_info(gpio->dev,
-                        "initializing GPIO Controller COH 901 571/3\n");
-               gpio->stride = U300_571_PORT_STRIDE;
-               gpio->pcr = U300_571_PXPCR;
-               gpio->dor = U300_571_PXPDOR;
-               gpio->dir = U300_571_PXPDIR;
-               gpio->per = U300_571_PXPER;
-               gpio->icr = U300_571_PXICR;
-               gpio->ien = U300_571_PXIEN;
-               gpio->iev = U300_571_PXIEV;
-               ifr = U300_571_PXIFR;
-
-               val = readl(gpio->base + U300_571_CR);
-               dev_info(gpio->dev, "COH901571/3 block version: %d, " \
-                        "number of cores: %d totalling %d pins\n",
-                        ((val & 0x000001FC) >> 2),
-                        ((val & 0x0000FE00) >> 9),
-                        ((val & 0x0000FE00) >> 9) * 8);
-               writel(U300_571_CR_BLOCK_CLKRQ_ENABLE,
-                      gpio->base + U300_571_CR);
-               u300_gpio_init_coh901571(gpio, plat);
-       } else {
-               dev_err(gpio->dev, "unknown block variant\n");
-               err = -ENODEV;
-               goto err_unknown_variant;
-       }
+       dev_info(gpio->dev,
+                "initializing GPIO Controller COH 901 571/3\n");
+       gpio->stride = U300_GPIO_PORT_STRIDE;
+       gpio->pcr = U300_GPIO_PXPCR;
+       gpio->dor = U300_GPIO_PXPDOR;
+       gpio->dir = U300_GPIO_PXPDIR;
+       gpio->per = U300_GPIO_PXPER;
+       gpio->icr = U300_GPIO_PXICR;
+       gpio->ien = U300_GPIO_PXIEN;
+       gpio->iev = U300_GPIO_PXIEV;
+       ifr = U300_GPIO_PXIFR;
+
+       val = readl(gpio->base + U300_GPIO_CR);
+       dev_info(gpio->dev, "COH901571/3 block version: %d, " \
+                "number of cores: %d totalling %d pins\n",
+                ((val & 0x000001FC) >> 2),
+                ((val & 0x0000FE00) >> 9),
+                ((val & 0x0000FE00) >> 9) * 8);
+       writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,
+              gpio->base + U300_GPIO_CR);
+       u300_gpio_init_coh901571(gpio, plat);
 
        /* Add each port with its IRQ separately */
        INIT_LIST_HEAD(&gpio->port_list);
@@ -906,7 +778,6 @@ err_no_pinctrl:
 err_no_chip:
 err_no_port:
        u300_gpio_free_ports(gpio);
-err_unknown_variant:
        iounmap(gpio->base);
 err_no_ioremap:
        release_mem_region(gpio->memres->start, resource_size(gpio->memres));
@@ -923,16 +794,11 @@ err_no_clk:
 
 static int __exit u300_gpio_remove(struct platform_device *pdev)
 {
-       struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
        struct u300_gpio *gpio = platform_get_drvdata(pdev);
        int err;
 
        /* Turn off the GPIO block */
-       if (plat->variant == U300_GPIO_COH901335)
-               writel(0x00000000U, gpio->base + U300_335_CR);
-       if (plat->variant == U300_GPIO_COH901571_3_BS335 ||
-           plat->variant == U300_GPIO_COH901571_3_BS365)
-               writel(0x00000000U, gpio->base + U300_571_CR);
+       writel(0x00000000U, gpio->base + U300_GPIO_CR);
 
        err = gpiochip_remove(&gpio->chip);
        if (err < 0) {
index 44efc6e..d4957b4 100644 (file)
@@ -27,6 +27,8 @@
 #include <linux/pm_runtime.h>
 #include <linux/power/smartreflex.h>
 
+#include <plat/cpu.h>
+
 #define SMARTREFLEX_NAME_LEN   16
 #define NVALUE_NAME_LEN                40
 #define SR_DISABLE_TIMEOUT     200
index a1f7ac1..b54504e 100644 (file)
@@ -29,7 +29,7 @@
 #include <linux/remoteproc.h>
 
 #include <plat/mailbox.h>
-#include <plat/remoteproc.h>
+#include <linux/platform_data/remoteproc-omap.h>
 
 #include "omap_remoteproc.h"
 #include "remoteproc_internal.h"
index edfd12b..968d083 100644 (file)
@@ -273,7 +273,7 @@ static void eesoxscsi_buffer_out(void *buf, int length, void __iomem *base)
 {
        const void __iomem *reg_fas = base + EESOX_FAS216_OFFSET;
        const void __iomem *reg_dmastat = base + EESOX_DMASTAT;
-       const void __iomem *reg_dmadata = base + EESOX_DMADATA;
+       void __iomem *reg_dmadata = base + EESOX_DMADATA;
 
        do {
                unsigned int status;
index 5f84b55..2d198a0 100644 (file)
@@ -366,7 +366,7 @@ config SPI_STMP3XXX
 
 config SPI_TEGRA
        tristate "Nvidia Tegra SPI controller"
-       depends on ARCH_TEGRA && (TEGRA_SYSTEM_DMA || TEGRA20_APB_DMA)
+       depends on ARCH_TEGRA && TEGRA20_APB_DMA
        help
          SPI driver for NVidia Tegra SoCs
 
index 9b0d716..0a94d9d 100644 (file)
@@ -52,8 +52,9 @@
 #include <asm/io.h>
 #include <asm/mach-types.h>
 
-#include <plat/mux.h>
-#include <plat/omap7xx.h>      /* OMAP7XX_IO_CONF registers */
+#include <mach/mux.h>
+
+#include <mach/omap7xx.h>      /* OMAP7XX_IO_CONF registers */
 
 
 /* FIXME address is now a platform device resource,
index 569714e..5d59a69 100644 (file)
@@ -42,7 +42,7 @@
 #include <linux/spi/spi.h>
 
 #include <plat/clock.h>
-#include <plat/mcspi.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
 
 #define OMAP2_MCSPI_MAX_FREQ           48000000
 #define SPI_AUTOSUSPEND_TIMEOUT                2000
index ef52c1c..488d9b6 100644 (file)
@@ -164,23 +164,15 @@ struct spi_tegra_data {
         * for the generic case.
         */
        int                     dma_req_len;
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
-       struct tegra_dma_req    rx_dma_req;
-       struct tegra_dma_channel *rx_dma;
-#else
        struct dma_chan         *rx_dma;
        struct dma_slave_config sconfig;
        struct dma_async_tx_descriptor  *rx_dma_desc;
        dma_cookie_t            rx_cookie;
-#endif
        u32                     *rx_bb;
        dma_addr_t              rx_bb_phys;
 };
 
-#if !defined(CONFIG_TEGRA_SYSTEM_DMA)
 static void tegra_spi_rx_dma_complete(void *args);
-#endif
-
 static inline unsigned long spi_tegra_readl(struct spi_tegra_data *tspi,
                                            unsigned long reg)
 {
@@ -204,10 +196,6 @@ static void spi_tegra_go(struct spi_tegra_data *tspi)
        val &= ~SLINK_DMA_BLOCK_SIZE(~0) & ~SLINK_DMA_EN;
        val |= SLINK_DMA_BLOCK_SIZE(tspi->dma_req_len / 4 - 1);
        spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
-       tspi->rx_dma_req.size = tspi->dma_req_len;
-       tegra_dma_enqueue_req(tspi->rx_dma, &tspi->rx_dma_req);
-#else
        tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma,
                                tspi->rx_bb_phys, tspi->dma_req_len,
                                DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
@@ -219,7 +207,6 @@ static void spi_tegra_go(struct spi_tegra_data *tspi)
        tspi->rx_dma_desc->callback_param = tspi;
        tspi->rx_cookie = dmaengine_submit(tspi->rx_dma_desc);
        dma_async_issue_pending(tspi->rx_dma);
-#endif
 
        val |= SLINK_DMA_EN;
        spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
@@ -405,19 +392,12 @@ static void handle_spi_rx_dma_complete(struct spi_tegra_data *tspi)
 
        spin_unlock_irqrestore(&tspi->lock, flags);
 }
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
-static void tegra_spi_rx_dma_complete(struct tegra_dma_req *req)
-{
-       struct spi_tegra_data *tspi = req->dev;
-       handle_spi_rx_dma_complete(tspi);
-}
-#else
+
 static void tegra_spi_rx_dma_complete(void *args)
 {
        struct spi_tegra_data *tspi = args;
        handle_spi_rx_dma_complete(tspi);
 }
-#endif
 
 static int spi_tegra_setup(struct spi_device *spi)
 {
@@ -509,9 +489,7 @@ static int __devinit spi_tegra_probe(struct platform_device *pdev)
        struct spi_tegra_data   *tspi;
        struct resource         *r;
        int ret;
-#if !defined(CONFIG_TEGRA_SYSTEM_DMA)
        dma_cap_mask_t mask;
-#endif
 
        master = spi_alloc_master(&pdev->dev, sizeof *tspi);
        if (master == NULL) {
@@ -563,14 +541,6 @@ static int __devinit spi_tegra_probe(struct platform_device *pdev)
 
        INIT_LIST_HEAD(&tspi->queue);
 
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
-       tspi->rx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT);
-       if (!tspi->rx_dma) {
-               dev_err(&pdev->dev, "can not allocate rx dma channel\n");
-               ret = -ENODEV;
-               goto err3;
-       }
-#else
        dma_cap_zero(mask);
        dma_cap_set(DMA_SLAVE, mask);
        tspi->rx_dma = dma_request_channel(mask, NULL, NULL);
@@ -580,8 +550,6 @@ static int __devinit spi_tegra_probe(struct platform_device *pdev)
                goto err3;
        }
 
-#endif
-
        tspi->rx_bb = dma_alloc_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
                                         &tspi->rx_bb_phys, GFP_KERNEL);
        if (!tspi->rx_bb) {
@@ -590,17 +558,6 @@ static int __devinit spi_tegra_probe(struct platform_device *pdev)
                goto err4;
        }
 
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
-       tspi->rx_dma_req.complete = tegra_spi_rx_dma_complete;
-       tspi->rx_dma_req.to_memory = 1;
-       tspi->rx_dma_req.dest_addr = tspi->rx_bb_phys;
-       tspi->rx_dma_req.dest_bus_width = 32;
-       tspi->rx_dma_req.source_addr = tspi->phys + SLINK_RX_FIFO;
-       tspi->rx_dma_req.source_bus_width = 32;
-       tspi->rx_dma_req.source_wrap = 4;
-       tspi->rx_dma_req.req_sel = spi_tegra_req_sels[pdev->id];
-       tspi->rx_dma_req.dev = tspi;
-#else
        /* Dmaengine Dma slave config */
        tspi->sconfig.src_addr = tspi->phys + SLINK_RX_FIFO;
        tspi->sconfig.dst_addr = tspi->phys + SLINK_RX_FIFO;
@@ -616,7 +573,6 @@ static int __devinit spi_tegra_probe(struct platform_device *pdev)
                        ret);
                goto err4;
        }
-#endif
 
        master->dev.of_node = pdev->dev.of_node;
        ret = spi_register_master(master);
@@ -630,11 +586,7 @@ err5:
        dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
                          tspi->rx_bb, tspi->rx_bb_phys);
 err4:
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
-       tegra_dma_free_channel(tspi->rx_dma);
-#else
        dma_release_channel(tspi->rx_dma);
-#endif
 err3:
        clk_put(tspi->clk);
 err2:
@@ -656,12 +608,7 @@ static int __devexit spi_tegra_remove(struct platform_device *pdev)
        tspi = spi_master_get_devdata(master);
 
        spi_unregister_master(master);
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
-       tegra_dma_free_channel(tspi->rx_dma);
-#else
        dma_release_channel(tspi->rx_dma);
-#endif
-
        dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
                          tspi->rx_bb, tspi->rx_bb_phys);
 
index 7eac01e..b647207 100644 (file)
@@ -23,7 +23,7 @@
 /*  ----------------------------------- Host OS */
 #include <dspbridge/host_os.h>
 #include <plat/dmtimer.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
 /*  ----------------------------------- DSP/BIOS Bridge */
 #include <dspbridge/dbdefs.h>
index 012c5a0..066a3ce 100644 (file)
@@ -16,7 +16,7 @@
  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  */
 
-#include <plat/dsp.h>
+#include <linux/platform_data/dsp-omap.h>
 
 #include <linux/types.h>
 /*  ----------------------------------- Host OS */
index 58a1d6d..dafa6d9 100644 (file)
@@ -19,7 +19,7 @@
 /*  ----------------------------------- Host OS */
 #include <dspbridge/host_os.h>
 
-#include <plat/dsp.h>
+#include <linux/platform_data/dsp-omap.h>
 
 /*  ----------------------------------- DSP/BIOS Bridge */
 #include <dspbridge/dbdefs.h>
index 7fda10c..f53ed98 100644 (file)
@@ -16,7 +16,7 @@
  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  */
 
-#include <plat/dsp.h>
+#include <linux/platform_data/dsp-omap.h>
 
 /*  ----------------------------------- DSP/BIOS Bridge */
 #include <dspbridge/dbdefs.h>
index e5adad0..1dce36f 100644 (file)
@@ -26,7 +26,7 @@
 
 
 #define OMAP34XX_WDT3_BASE             (0x49000000 + 0x30000)
-#define INT_34XX_WDT3_IRQ              36
+#define INT_34XX_WDT3_IRQ              (36 + NR_IRQS)
 
 static struct dsp_wdt_setting dsp_wdt;
 
index 6acea2b..bddea1d 100644 (file)
@@ -16,7 +16,7 @@
  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  */
 
-#include <plat/dsp.h>
+#include <linux/platform_data/dsp-omap.h>
 
 #include <linux/types.h>
 #include <linux/platform_device.h>
index 7c13639..9bd004f 100644 (file)
@@ -548,8 +548,8 @@ static struct uart_ops ks8695uart_pops = {
 
 static struct uart_port ks8695uart_ports[SERIAL_KS8695_NR] = {
        {
-               .membase        = (void *) KS8695_UART_VA,
-               .mapbase        = KS8695_UART_VA,
+               .membase        = KS8695_UART_VA,
+               .mapbase        = KS8695_UART_PA,
                .iotype         = SERIAL_IO_MEM,
                .irq            = KS8695_IRQ_UART_TX,
                .uartclk        = KS8695_CLOCK_RATE * 16,
index 2564b54..4c90b51 100644 (file)
@@ -13,7 +13,6 @@ config USB_ARCH_HAS_OHCI
        default y if PXA3xx
        default y if ARCH_EP93XX
        default y if ARCH_AT91
-       default y if ARCH_PNX4008
        default y if MFD_TC6393XB
        default y if ARCH_W90X900
        default y if ARCH_DAVINCI_DA8XX
index b1deb0f..3f1431d 100644 (file)
@@ -292,7 +292,7 @@ config USB_OHCI_HCD
        depends on USB && USB_ARCH_HAS_OHCI
        select ISP1301_OMAP if MACH_OMAP_H2 || MACH_OMAP_H3
        select USB_OTG_UTILS if ARCH_OMAP
-       depends on USB_ISP1301 || !(ARCH_LPC32XX || ARCH_PNX4008)
+       depends on USB_ISP1301 || !ARCH_LPC32XX
        ---help---
          The Open Host Controller Interface (OHCI) is a standard for accessing
          USB 1.1 host controller hardware.  It does more in hardware than Intel's
index 2b1e8d8..6780010 100644 (file)
@@ -1049,7 +1049,7 @@ MODULE_LICENSE ("GPL");
 #define PLATFORM_DRIVER                ohci_hcd_at91_driver
 #endif
 
-#if defined(CONFIG_ARCH_PNX4008) || defined(CONFIG_ARCH_LPC32XX)
+#ifdef CONFIG_ARCH_LPC32XX
 #include "ohci-nxp.c"
 #define PLATFORM_DRIVER                usb_hcd_nxp_driver
 #endif
index c60066a..e068f03 100644 (file)
@@ -2,7 +2,6 @@
  * driver for NXP USB Host devices
  *
  * Currently supported OHCI host devices:
- * - Philips PNX4008
  * - NXP LPC32xx
  *
  * Authors: Dmitry Chigirev <source@mvista.com>
@@ -66,38 +65,6 @@ static struct clk *usb_pll_clk;
 static struct clk *usb_dev_clk;
 static struct clk *usb_otg_clk;
 
-static void isp1301_configure_pnx4008(void)
-{
-       /* PNX4008 only supports DAT_SE0 USB mode */
-       /* PNX4008 R2A requires setting the MAX603 to output 3.6V */
-       /* Power up externel charge-pump */
-
-       i2c_smbus_write_byte_data(isp1301_i2c_client,
-               ISP1301_I2C_MODE_CONTROL_1, MC1_DAT_SE0 | MC1_SPEED_REG);
-       i2c_smbus_write_byte_data(isp1301_i2c_client,
-               ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
-               ~(MC1_DAT_SE0 | MC1_SPEED_REG));
-       i2c_smbus_write_byte_data(isp1301_i2c_client,
-               ISP1301_I2C_MODE_CONTROL_2,
-               MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL);
-       i2c_smbus_write_byte_data(isp1301_i2c_client,
-               ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR,
-               ~(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL));
-       i2c_smbus_write_byte_data(isp1301_i2c_client,
-               ISP1301_I2C_OTG_CONTROL_1, OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN);
-       i2c_smbus_write_byte_data(isp1301_i2c_client,
-               ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
-               ~(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
-       i2c_smbus_write_byte_data(isp1301_i2c_client,
-               ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, 0xFF);
-       i2c_smbus_write_byte_data(isp1301_i2c_client,
-               ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR,
-               0xFF);
-       i2c_smbus_write_byte_data(isp1301_i2c_client,
-               ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR,
-               0xFF);
-}
-
 static void isp1301_configure_lpc32xx(void)
 {
        /* LPC32XX only supports DAT_SE0 USB mode */
@@ -149,10 +116,7 @@ static void isp1301_configure_lpc32xx(void)
 
 static void isp1301_configure(void)
 {
-       if (machine_is_pnx4008())
-               isp1301_configure_pnx4008();
-       else
-               isp1301_configure_lpc32xx();
+       isp1301_configure_lpc32xx();
 }
 
 static inline void isp1301_vbus_on(void)
@@ -241,47 +205,6 @@ static const struct hc_driver ohci_nxp_hc_driver = {
        .start_port_reset = ohci_start_port_reset,
 };
 
-static void nxp_set_usb_bits(void)
-{
-       if (machine_is_pnx4008()) {
-               start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N);
-               start_int_ack(SE_USB_OTG_ATX_INT_N);
-               start_int_umask(SE_USB_OTG_ATX_INT_N);
-
-               start_int_set_rising_edge(SE_USB_OTG_TIMER_INT);
-               start_int_ack(SE_USB_OTG_TIMER_INT);
-               start_int_umask(SE_USB_OTG_TIMER_INT);
-
-               start_int_set_rising_edge(SE_USB_I2C_INT);
-               start_int_ack(SE_USB_I2C_INT);
-               start_int_umask(SE_USB_I2C_INT);
-
-               start_int_set_rising_edge(SE_USB_INT);
-               start_int_ack(SE_USB_INT);
-               start_int_umask(SE_USB_INT);
-
-               start_int_set_rising_edge(SE_USB_NEED_CLK_INT);
-               start_int_ack(SE_USB_NEED_CLK_INT);
-               start_int_umask(SE_USB_NEED_CLK_INT);
-
-               start_int_set_rising_edge(SE_USB_AHB_NEED_CLK_INT);
-               start_int_ack(SE_USB_AHB_NEED_CLK_INT);
-               start_int_umask(SE_USB_AHB_NEED_CLK_INT);
-       }
-}
-
-static void nxp_unset_usb_bits(void)
-{
-       if (machine_is_pnx4008()) {
-               start_int_mask(SE_USB_OTG_ATX_INT_N);
-               start_int_mask(SE_USB_OTG_TIMER_INT);
-               start_int_mask(SE_USB_I2C_INT);
-               start_int_mask(SE_USB_INT);
-               start_int_mask(SE_USB_NEED_CLK_INT);
-               start_int_mask(SE_USB_AHB_NEED_CLK_INT);
-       }
-}
-
 static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev)
 {
        struct usb_hcd *hcd = 0;
@@ -376,9 +299,6 @@ static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev)
                goto out8;
        }
 
-       /* Set all USB bits in the Start Enable register */
-       nxp_set_usb_bits();
-
        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        if (!res) {
                dev_err(&pdev->dev, "Failed to get MEM resource\n");
@@ -413,7 +333,6 @@ static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev)
 
        nxp_stop_hc();
 out8:
-       nxp_unset_usb_bits();
        usb_put_hcd(hcd);
 out7:
        clk_disable(usb_otg_clk);
@@ -441,7 +360,6 @@ static int usb_hcd_nxp_remove(struct platform_device *pdev)
        nxp_stop_hc();
        release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
        usb_put_hcd(hcd);
-       nxp_unset_usb_bits();
        clk_disable(usb_pll_clk);
        clk_put(usb_pll_clk);
        clk_disable(usb_dev_clk);
index f8b2d91..4531d03 100644 (file)
@@ -24,7 +24,7 @@
 #include <asm/io.h>
 #include <asm/mach-types.h>
 
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include <plat/fpga.h>
 
 #include <mach/hardware.h>
index 53e2596..7a62b95 100644 (file)
@@ -17,7 +17,6 @@
 #include <linux/dma-mapping.h>
 #include <linux/slab.h>
 #include <plat/dma.h>
-#include <plat/mux.h>
 
 #include "musb_core.h"
 #include "tusb6010.h"
index 7a88667..81f1f9a 100644 (file)
@@ -36,7 +36,7 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <plat/mux.h>
+#include <mach/mux.h>
 
 #include <mach/usb.h>
 
index bfdc5fb..9a046a4 100644 (file)
 #include <linux/fb.h>
 #include <linux/backlight.h>
 #include <linux/slab.h>
+#include <linux/platform_data/omap1_bl.h>
 
 #include <mach/hardware.h>
-#include <plat/board.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 
 #define OMAPBL_MAX_INTENSITY           0xff
 
index 7ae9d53..113d43a 100644 (file)
 #define UPPER_MARGIN   32
 #define LOWER_MARGIN   32
 
-static resource_size_t da8xx_fb_reg_base;
+static void __iomem *da8xx_fb_reg_base;
 static struct resource *lcdc_regs;
 static unsigned int lcd_revision;
 static irq_handler_t lcdc_irq_handler;
@@ -951,7 +951,7 @@ static int __devexit fb_remove(struct platform_device *dev)
                clk_disable(par->lcdc_clk);
                clk_put(par->lcdc_clk);
                framebuffer_release(info);
-               iounmap((void __iomem *)da8xx_fb_reg_base);
+               iounmap(da8xx_fb_reg_base);
                release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
 
        }
@@ -1171,7 +1171,7 @@ static int __devinit fb_probe(struct platform_device *device)
        if (!lcdc_regs)
                return -EBUSY;
 
-       da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len);
+       da8xx_fb_reg_base = ioremap(lcdc_regs->start, len);
        if (!da8xx_fb_reg_base) {
                ret = -EBUSY;
                goto err_request_mem;
@@ -1392,7 +1392,7 @@ err_clk_put:
        clk_put(fb_clk);
 
 err_ioremap:
-       iounmap((void __iomem *)da8xx_fb_reg_base);
+       iounmap(da8xx_fb_reg_base);
 
 err_request_mem:
        release_mem_region(lcdc_regs->start, len);
index d3a3113..ed4cad8 100644 (file)
@@ -27,8 +27,7 @@
 #include <linux/lcd.h>
 #include <linux/gpio.h>
 
-#include <plat/board-ams-delta.h>
-#include <mach/hardware.h>
+#include <mach/board-ams-delta.h>
 
 #include "omapfb.h"
 
index e3880c4..b739600 100644 (file)
@@ -25,7 +25,7 @@
 #include <linux/spi/spi.h>
 #include <linux/module.h>
 
-#include <plat/lcd_mipid.h>
+#include <linux/platform_data/lcd-mipid.h>
 
 #include "omapfb.h"
 
index 5914220..3aa62da 100644 (file)
@@ -24,7 +24,7 @@
 #include <linux/platform_device.h>
 
 #include <asm/gpio.h>
-#include <plat/mux.h>
+#include <mach/mux.h>
 #include "omapfb.h"
 
 static int osk_panel_init(struct lcd_panel *panel, struct omapfb_device *fbdev)
index 5b289c5..ee9e296 100644 (file)
@@ -37,6 +37,7 @@
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
 
+#include <plat/cpu.h>
 #include <plat/clock.h>
 
 #include <video/omapdss.h>
index fc671d3..3c39aa8 100644 (file)
@@ -31,6 +31,7 @@
 #include <linux/omapfb.h>
 
 #include <video/omapdss.h>
+#include <plat/cpu.h>
 #include <plat/vram.h>
 #include <plat/vrfb.h>
 
index 53d7571..ad1bb93 100644 (file)
@@ -237,12 +237,12 @@ config OMAP_WATCHDOG
          here to enable the OMAP1610/OMAP1710/OMAP2420/OMAP3430/OMAP4430 watchdog timer.
 
 config PNX4008_WATCHDOG
-       tristate "PNX4008 and LPC32XX Watchdog"
-       depends on ARCH_PNX4008 || ARCH_LPC32XX
+       tristate "LPC32XX Watchdog"
+       depends on ARCH_LPC32XX
        select WATCHDOG_CORE
        help
          Say Y here if to include support for the watchdog timer
-         in the PNX4008 or LPC32XX processor.
+         in the LPC32XX processor.
          This driver can be built as a module by choosing M. The module
          will be called pnx4008_wdt.
 
index 59e75d9..c1a4d3b 100644 (file)
 #include <linux/io.h>
 #include <linux/uaccess.h>
 #include <mach/hardware.h>
-#include <mach/regs-timer.h>
+
+#define KS8695_TMR_OFFSET      (0xF0000 + 0xE400)
+#define KS8695_TMR_VA          (KS8695_IO_VA + KS8695_TMR_OFFSET)
+
+/*
+ * Timer registers
+ */
+#define KS8695_TMCON           (0x00)          /* Timer Control Register */
+#define KS8695_T0TC            (0x08)          /* Timer 0 Timeout Count Register */
+#define TMCON_T0EN             (1 << 0)        /* Timer 0 Enable */
+
+/* Timer0 Timeout Counter Register */
+#define T0TC_WATCHDOG          (0xff)          /* Enable watchdog mode */
 
 #define WDT_DEFAULT_TIME       5       /* seconds */
 #define WDT_MAX_TIME           171     /* seconds */
index fceec4f..f5db18d 100644 (file)
@@ -46,6 +46,7 @@
 #include <linux/slab.h>
 #include <linux/pm_runtime.h>
 #include <mach/hardware.h>
+#include <plat/cpu.h>
 #include <plat/prcm.h>
 
 #include "omap_wdt.h"
@@ -218,12 +219,16 @@ static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
        case WDIOC_GETSTATUS:
                return put_user(0, (int __user *)arg);
        case WDIOC_GETBOOTSTATUS:
+#ifdef CONFIG_ARCH_OMAP1
                if (cpu_is_omap16xx())
                        return put_user(__raw_readw(ARM_SYSST),
                                        (int __user *)arg);
+#endif
+#ifdef CONFIG_ARCH_OMAP2PLUS
                if (cpu_is_omap24xx())
                        return put_user(omap_prcm_get_reset_sources(),
                                        (int __user *)arg);
+#endif
                return put_user(0, (int __user *)arg);
        case WDIOC_KEEPALIVE:
                spin_lock(&wdt_lock);
index 7ea898c..a12a381 100644 (file)
@@ -561,9 +561,6 @@ struct twl4030_bci_platform_data {
 
 /* TWL4030_GPIO_MAX (18) GPIOs, with interrupts */
 struct twl4030_gpio_platform_data {
-       int             gpio_base;
-       unsigned        irq_base, irq_end;
-
        /* package the two LED signals as output-only GPIOs? */
        bool            use_leds;
 
index eaad49f..ba43d48 100644 (file)
@@ -194,7 +194,6 @@ struct twl6040_vibra_data {
 
 struct twl6040_platform_data {
        int audpwron_gpio;      /* audio power-on gpio */
-       unsigned int irq_base;
 
        struct twl6040_codec_data *codec;
        struct twl6040_vibra_data *vibra;
index 4ff57e8..85af818 100644 (file)
@@ -220,7 +220,12 @@ struct omapfb_display_info {
 
 #ifdef __KERNEL__
 
-#include <plat/board.h>
+struct omap_lcd_config {
+       char panel_name[16];
+       char ctrl_name[16];
+       s16  nreset_gpio;
+       u8   data_lines;
+};
 
 struct omapfb_platform_data {
        struct omap_lcd_config          lcd;
similarity index 94%
rename from arch/arm/plat-omap/include/plat/gpio.h
rename to include/linux/platform_data/gpio-omap.h
index 50fb7cc..e8741c2 100644 (file)
@@ -1,6 +1,4 @@
 /*
- * arch/arm/plat-omap/include/mach/gpio.h
- *
  * OMAP GPIO handling defines and functions
  *
  * Copyright (C) 2003-2005 Nokia Corporation
 #define OMAP4_GPIO_CLEARDATAOUT                0x0190
 #define OMAP4_GPIO_SETDATAOUT          0x0194
 
+#define OMAP_MAX_GPIO_LINES            192
+
 #define OMAP_MPUIO(nr)         (OMAP_MAX_GPIO_LINES + (nr))
 #define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES)
 
@@ -213,16 +213,5 @@ extern void omap2_gpio_prepare_for_idle(int off_mode);
 extern void omap2_gpio_resume_after_idle(void);
 extern void omap_set_gpio_debounce(int gpio, int enable);
 extern void omap_set_gpio_debounce_time(int gpio, int enable);
-/*-------------------------------------------------------------------------*/
-
-/*
- * Wrappers for "new style" GPIO calls, using the new infrastructure
- * which lets us plug in FPGA, I2C, and other implementations.
- *
- * The original OMAP-specific calls should eventually be removed.
- */
-
-#include <linux/errno.h>
-#include <asm-generic/gpio.h>
 
 #endif
similarity index 96%
rename from arch/arm/plat-omap/include/plat/nand.h
rename to include/linux/platform_data/mtd-nand-omap2.h
index 67fc506..1a68c1e 100644 (file)
@@ -24,11 +24,10 @@ struct omap_nand_platform_data {
        struct gpmc_timings     *gpmc_t;
        int                     nr_parts;
        bool                    dev_ready;
-       int                     gpmc_irq;
        enum nand_io            xfer_type;
-       unsigned long           phys_base;
        int                     devsize;
        enum omap_ecc           ecc_opt;
+       struct gpmc_nand_regs   reg;
 };
 
 /* minimum size for IO mapping */
diff --git a/include/linux/platform_data/omap1_bl.h b/include/linux/platform_data/omap1_bl.h
new file mode 100644 (file)
index 0000000..881a8e9
--- /dev/null
@@ -0,0 +1,11 @@
+#ifndef __OMAP1_BL_H__
+#define __OMAP1_BL_H__
+
+#include <linux/device.h>
+
+struct omap_backlight_config {
+       int default_intensity;
+       int (*set_power)(struct device *dev, int state);
+};
+
+#endif
similarity index 72%
rename from arch/arm/mach-u300/include/mach/gpio-u300.h
rename to include/linux/platform_data/pinctrl-coh901.h
index e81400c..30dea25 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2007-2011 ST-Ericsson AB
+ * Copyright (C) 2007-2012 ST-Ericsson AB
  * License terms: GNU General Public License (GPL) version 2
  * GPIO block resgister definitions and inline macros for
  * U300 GPIO COH 901 335 or COH 901 571/3
 #define __MACH_U300_GPIO_U300_H
 
 /**
- * enum u300_gpio_variant - the type of U300 GPIO employed
- */
-enum u300_gpio_variant {
-       U300_GPIO_COH901335,
-       U300_GPIO_COH901571_3_BS335,
-       U300_GPIO_COH901571_3_BS365,
-};
-
-/**
  * struct u300_gpio_platform - U300 GPIO platform data
- * @variant: IP block variant
  * @ports: number of GPIO block ports
  * @gpio_base: first GPIO number for this block (use a free range)
  * @gpio_irq_base: first GPIO IRQ number for this block (use a free range)
  * @pinctrl_device: pin control device to spawn as child
  */
 struct u300_gpio_platform {
-       enum u300_gpio_variant variant;
        u8 ports;
        int gpio_base;
        int gpio_irq_base;
index 3101e62..4a496eb 100644 (file)
@@ -23,7 +23,7 @@
 #include <linux/types.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
-#include <plat/voltage.h>
+#include <linux/platform_data/voltage-omap.h>
 
 /*
  * Different Smartreflex IPs version. The v1 is the 65nm version used in
index df65f98..a52e87d 100644 (file)
@@ -27,7 +27,7 @@
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
 #include <mach/gpio.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
 #include "omap-mcbsp.h"
 #include "omap-pcm.h"
index 7d4fa8e..dc0ee76 100644 (file)
@@ -32,8 +32,8 @@
 
 #include <asm/mach-types.h>
 
-#include <plat/board-ams-delta.h>
-#include <plat/mcbsp.h>
+#include <mach/board-ams-delta.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
 #include "omap-mcbsp.h"
 #include "omap-pcm.h"
index e835781..5ed8716 100644 (file)
@@ -29,7 +29,7 @@
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
 #include <mach/gpio.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
 #include "omap-mcbsp.h"
 #include "omap-pcm.h"
index d33c48b..a681a9a 100644 (file)
@@ -25,7 +25,9 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
+
+#include <plat/cpu.h>
 
 #include "mcbsp.h"
 
index abac4b6..521bfc3 100644 (file)
@@ -32,7 +32,7 @@
 #include <mach/hardware.h>
 #include <linux/gpio.h>
 #include <linux/module.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
 #include "omap-mcbsp.h"
 #include "omap-pcm.h"
index 9d93793..45909ca 100644 (file)
 #include <sound/soc.h>
 #include <sound/jack.h>
 
-#include <asm/mach-types.h>
-#include <plat/hardware.h>
-#include <plat/mux.h>
-
 #include "omap-dmic.h"
 #include "omap-mcpdm.h"
 #include "omap-pcm.h"
index acdd3ef..1b18627 100644 (file)
@@ -32,8 +32,9 @@
 #include <sound/initval.h>
 #include <sound/soc.h>
 
+#include <plat/cpu.h>
 #include <plat/dma.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 #include "mcbsp.h"
 #include "omap-mcbsp.h"
 #include "omap-pcm.h"
index 2c66e24..ea053c3 100644 (file)
@@ -45,6 +45,8 @@
 #include "omap-mcpdm.h"
 #include "omap-pcm.h"
 
+#define OMAP44XX_MCPDM_L3_BASE         0x49032000
+
 struct omap_mcpdm {
        struct device *dev;
        unsigned long phys_base;
index f0feb06..b309941 100644 (file)
@@ -30,6 +30,7 @@
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
 
+#include <plat/cpu.h>
 #include <plat/dma.h>
 #include "omap-pcm.h"
 
index 2830dfd..e263188 100644 (file)
@@ -29,7 +29,7 @@
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
 #include <mach/gpio.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
 #include "omap-mcbsp.h"
 #include "omap-pcm.h"
index 3d468c9..d632bfb 100644 (file)
@@ -27,7 +27,7 @@
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
 #include <mach/gpio.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
 #include "omap-mcbsp.h"
 #include "omap-pcm.h"
index 4c3a097..43d950a 100644 (file)
@@ -31,7 +31,7 @@
 #include <sound/soc.h>
 
 #include <asm/mach-types.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
 #include "omap-mcbsp.h"
 #include "omap-pcm.h"
index b1a9d64..3960e8d 100644 (file)
@@ -31,7 +31,7 @@
 #include <mach/hardware.h>
 #include <linux/gpio.h>
 #include <linux/module.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
 #include "omap-mcbsp.h"
 #include "omap-pcm.h"
index 6ac3e0c..502bce2 100644 (file)
@@ -29,7 +29,7 @@
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
 #include <mach/gpio.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
 #include "omap-mcbsp.h"
 #include "omap-pcm.h"
index 2712dd2..d921ddb 100644 (file)
@@ -31,7 +31,7 @@
 #include <sound/jack.h>
 #include <sound/pcm.h>
 #include <sound/soc.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 #include "../codecs/tpa6130a2.h"
 
 #include <asm/mach-types.h>
index 0e28322..597cae7 100644 (file)
@@ -33,7 +33,8 @@
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
 #include <mach/gpio.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/gpio-omap.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
 /* Register descriptions for twl4030 codec part */
 #include <linux/mfd/twl4030-audio.h>
index 920e0d9..23de2b2 100644 (file)
@@ -29,7 +29,7 @@
 #include <mach/hardware.h>
 #include <mach/gpio.h>
 #include <mach/board-zoom.h>
-#include <plat/mcbsp.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
 
 /* Register descriptions for twl4030 codec part */
 #include <linux/mfd/twl4030-audio.h>
index 02bcd30..19e5fe7 100644 (file)
@@ -1,6 +1,6 @@
 config SND_SOC_TEGRA
        tristate "SoC Audio for the Tegra System-on-Chip"
-       depends on ARCH_TEGRA && (TEGRA_SYSTEM_DMA || TEGRA20_APB_DMA)
+       depends on ARCH_TEGRA && TEGRA20_APB_DMA
        select REGMAP_MMIO
        select SND_SOC_DMAENGINE_PCM if TEGRA20_APB_DMA
        help
index 8d6900c..e187339 100644 (file)
@@ -57,237 +57,6 @@ static const struct snd_pcm_hardware tegra_pcm_hardware = {
        .fifo_size              = 4,
 };
 
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
-static void tegra_pcm_queue_dma(struct tegra_runtime_data *prtd)
-{
-       struct snd_pcm_substream *substream = prtd->substream;
-       struct snd_dma_buffer *buf = &substream->dma_buffer;
-       struct tegra_dma_req *dma_req;
-       unsigned long addr;
-
-       dma_req = &prtd->dma_req[prtd->dma_req_idx];
-       prtd->dma_req_idx = 1 - prtd->dma_req_idx;
-
-       addr = buf->addr + prtd->dma_pos;
-       prtd->dma_pos += dma_req->size;
-       if (prtd->dma_pos >= prtd->dma_pos_end)
-               prtd->dma_pos = 0;
-
-       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-               dma_req->source_addr = addr;
-       else
-               dma_req->dest_addr = addr;
-
-       tegra_dma_enqueue_req(prtd->dma_chan, dma_req);
-}
-
-static void dma_complete_callback(struct tegra_dma_req *req)
-{
-       struct tegra_runtime_data *prtd = (struct tegra_runtime_data *)req->dev;
-       struct snd_pcm_substream *substream = prtd->substream;
-       struct snd_pcm_runtime *runtime = substream->runtime;
-
-       spin_lock(&prtd->lock);
-
-       if (!prtd->running) {
-               spin_unlock(&prtd->lock);
-               return;
-       }
-
-       if (++prtd->period_index >= runtime->periods)
-               prtd->period_index = 0;
-
-       tegra_pcm_queue_dma(prtd);
-
-       spin_unlock(&prtd->lock);
-
-       snd_pcm_period_elapsed(substream);
-}
-
-static void setup_dma_tx_request(struct tegra_dma_req *req,
-                                       struct tegra_pcm_dma_params * dmap)
-{
-       req->complete = dma_complete_callback;
-       req->to_memory = false;
-       req->dest_addr = dmap->addr;
-       req->dest_wrap = dmap->wrap;
-       req->source_bus_width = 32;
-       req->source_wrap = 0;
-       req->dest_bus_width = dmap->width;
-       req->req_sel = dmap->req_sel;
-}
-
-static void setup_dma_rx_request(struct tegra_dma_req *req,
-                                       struct tegra_pcm_dma_params * dmap)
-{
-       req->complete = dma_complete_callback;
-       req->to_memory = true;
-       req->source_addr = dmap->addr;
-       req->dest_wrap = 0;
-       req->source_bus_width = dmap->width;
-       req->source_wrap = dmap->wrap;
-       req->dest_bus_width = 32;
-       req->req_sel = dmap->req_sel;
-}
-
-static int tegra_pcm_open(struct snd_pcm_substream *substream)
-{
-       struct snd_pcm_runtime *runtime = substream->runtime;
-       struct tegra_runtime_data *prtd;
-       struct snd_soc_pcm_runtime *rtd = substream->private_data;
-       struct tegra_pcm_dma_params * dmap;
-       int ret = 0;
-
-       prtd = kzalloc(sizeof(struct tegra_runtime_data), GFP_KERNEL);
-       if (prtd == NULL)
-               return -ENOMEM;
-
-       runtime->private_data = prtd;
-       prtd->substream = substream;
-
-       spin_lock_init(&prtd->lock);
-
-       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
-               dmap = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
-               setup_dma_tx_request(&prtd->dma_req[0], dmap);
-               setup_dma_tx_request(&prtd->dma_req[1], dmap);
-       } else {
-               dmap = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
-               setup_dma_rx_request(&prtd->dma_req[0], dmap);
-               setup_dma_rx_request(&prtd->dma_req[1], dmap);
-       }
-
-       prtd->dma_req[0].dev = prtd;
-       prtd->dma_req[1].dev = prtd;
-
-       prtd->dma_chan = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT);
-       if (prtd->dma_chan == NULL) {
-               ret = -ENOMEM;
-               goto err;
-       }
-
-       /* Set HW params now that initialization is complete */
-       snd_soc_set_runtime_hwparams(substream, &tegra_pcm_hardware);
-
-       /* Ensure that buffer size is a multiple of period size */
-       ret = snd_pcm_hw_constraint_integer(runtime,
-                                               SNDRV_PCM_HW_PARAM_PERIODS);
-       if (ret < 0)
-               goto err;
-
-       return 0;
-
-err:
-       if (prtd->dma_chan) {
-               tegra_dma_free_channel(prtd->dma_chan);
-       }
-
-       kfree(prtd);
-
-       return ret;
-}
-
-static int tegra_pcm_close(struct snd_pcm_substream *substream)
-{
-       struct snd_pcm_runtime *runtime = substream->runtime;
-       struct tegra_runtime_data *prtd = runtime->private_data;
-
-       tegra_dma_free_channel(prtd->dma_chan);
-
-       kfree(prtd);
-
-       return 0;
-}
-
-static int tegra_pcm_hw_params(struct snd_pcm_substream *substream,
-                               struct snd_pcm_hw_params *params)
-{
-       struct snd_pcm_runtime *runtime = substream->runtime;
-       struct tegra_runtime_data *prtd = runtime->private_data;
-
-       snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
-
-       prtd->dma_req[0].size = params_period_bytes(params);
-       prtd->dma_req[1].size = prtd->dma_req[0].size;
-
-       return 0;
-}
-
-static int tegra_pcm_hw_free(struct snd_pcm_substream *substream)
-{
-       snd_pcm_set_runtime_buffer(substream, NULL);
-
-       return 0;
-}
-
-static int tegra_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
-{
-       struct snd_pcm_runtime *runtime = substream->runtime;
-       struct tegra_runtime_data *prtd = runtime->private_data;
-       unsigned long flags;
-
-       switch (cmd) {
-       case SNDRV_PCM_TRIGGER_START:
-               prtd->dma_pos = 0;
-               prtd->dma_pos_end = frames_to_bytes(runtime, runtime->periods * runtime->period_size);
-               prtd->period_index = 0;
-               prtd->dma_req_idx = 0;
-               /* Fall-through */
-       case SNDRV_PCM_TRIGGER_RESUME:
-       case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
-               spin_lock_irqsave(&prtd->lock, flags);
-               prtd->running = 1;
-               spin_unlock_irqrestore(&prtd->lock, flags);
-               tegra_pcm_queue_dma(prtd);
-               tegra_pcm_queue_dma(prtd);
-               break;
-       case SNDRV_PCM_TRIGGER_STOP:
-       case SNDRV_PCM_TRIGGER_SUSPEND:
-       case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
-               spin_lock_irqsave(&prtd->lock, flags);
-               prtd->running = 0;
-               spin_unlock_irqrestore(&prtd->lock, flags);
-               tegra_dma_dequeue_req(prtd->dma_chan, &prtd->dma_req[0]);
-               tegra_dma_dequeue_req(prtd->dma_chan, &prtd->dma_req[1]);
-               break;
-       default:
-               return -EINVAL;
-       }
-
-       return 0;
-}
-
-static snd_pcm_uframes_t tegra_pcm_pointer(struct snd_pcm_substream *substream)
-{
-       struct snd_pcm_runtime *runtime = substream->runtime;
-       struct tegra_runtime_data *prtd = runtime->private_data;
-
-       return prtd->period_index * runtime->period_size;
-}
-
-
-static int tegra_pcm_mmap(struct snd_pcm_substream *substream,
-                               struct vm_area_struct *vma)
-{
-       struct snd_pcm_runtime *runtime = substream->runtime;
-
-       return dma_mmap_writecombine(substream->pcm->card->dev, vma,
-                                       runtime->dma_area,
-                                       runtime->dma_addr,
-                                       runtime->dma_bytes);
-}
-
-static struct snd_pcm_ops tegra_pcm_ops = {
-       .open           = tegra_pcm_open,
-       .close          = tegra_pcm_close,
-       .ioctl          = snd_pcm_lib_ioctl,
-       .hw_params      = tegra_pcm_hw_params,
-       .hw_free        = tegra_pcm_hw_free,
-       .trigger        = tegra_pcm_trigger,
-       .pointer        = tegra_pcm_pointer,
-       .mmap           = tegra_pcm_mmap,
-};
-#else
 static int tegra_pcm_open(struct snd_pcm_substream *substream)
 {
        struct snd_soc_pcm_runtime *rtd = substream->private_data;
@@ -399,7 +168,6 @@ static struct snd_pcm_ops tegra_pcm_ops = {
        .pointer        = snd_dmaengine_pcm_pointer,
        .mmap           = tegra_pcm_mmap,
 };
-#endif
 
 static int tegra_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
 {
index a3a4503..b40279b 100644 (file)
@@ -40,20 +40,6 @@ struct tegra_pcm_dma_params {
        unsigned long req_sel;
 };
 
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
-struct tegra_runtime_data {
-       struct snd_pcm_substream *substream;
-       spinlock_t lock;
-       int running;
-       int dma_pos;
-       int dma_pos_end;
-       int period_index;
-       int dma_req_idx;
-       struct tegra_dma_req dma_req[2];
-       struct tegra_dma_channel *dma_chan;
-};
-#endif
-
 int tegra_pcm_platform_register(struct device *dev);
 void tegra_pcm_platform_unregister(struct device *dev);