clk: qcom: ipq5332: drop the CLK_SET_RATE_PARENT flag from GPLL clocks

[ Upstream commit 5635ef0bd1052420bc659a00be6fd0c60cec5cb9 ]

GPLL clock rates are fixed and shouldn't be scaled based on the
request from dependent clocks. Doing so will result in the unexpected
behaviour. So drop the CLK_SET_RATE_PARENT flag from the GPLL clocks.

Fixes: 3d89d52970fd ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC")
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-5-c8ceb1a37680@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
index b836159..f985911 100644 (file)
--- a/drivers/clk/qcom/gcc-ipq5332.c
+++ b/drivers/clk/qcom/gcc-ipq5332.c
@@ -112,7 +112,6 @@ static struct clk_alpha_pll_postdiv gpll2 = {
                                &gpll2_main.clkr.hw },
                .num_parents = 1,
                .ops = &clk_alpha_pll_postdiv_ro_ops,
-               .flags = CLK_SET_RATE_PARENT,
        },
 };
 
@@ -152,7 +151,6 @@ static struct clk_alpha_pll_postdiv gpll4 = {
                                &gpll4_main.clkr.hw },
                .num_parents = 1,
                .ops = &clk_alpha_pll_postdiv_ro_ops,
-               .flags = CLK_SET_RATE_PARENT,
        },
 };