drm/i915/xehp: Add compute engine ABI
authorMatt Roper <matthew.d.roper@intel.com>
Thu, 28 Apr 2022 04:19:25 +0000 (21:19 -0700)
committerMatt Roper <matthew.d.roper@intel.com>
Fri, 29 Apr 2022 21:30:27 +0000 (14:30 -0700)
We're now ready to start exposing compute engines to userspace.

v2:
 - Move kerneldoc for other engine classes to a separate patch.  (Andi)

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Szymon Morek <szymon.morek@intel.com>
UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14395
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Jordan Justen <jordan.l.justen@intel.com> # mesa anvil & iris
Link: https://patchwork.freedesktop.org/patch/msgid/20220428041926.1483683-4-matthew.d.roper@intel.com
drivers/gpu/drm/i915/gt/intel_engine_user.c
drivers/gpu/drm/i915/i915_drm_client.c
drivers/gpu/drm/i915/i915_drm_client.h
include/uapi/drm/i915_drm.h

index 0f6cd96b459f6dbb3cfabfde95d540cfd9ab4783..46a174f8aa0076ca71926b23df17f2983ae347ce 100644 (file)
@@ -47,7 +47,7 @@ static const u8 uabi_classes[] = {
        [COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY,
        [VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO,
        [VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,
-       /* TODO: Add COMPUTE_CLASS mapping once ABI is available */
+       [COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE,
 };
 
 static int engine_cmp(void *priv, const struct list_head *A,
index 475a6f824cad7132c04c7c4e6b6e4b1ecd8ab386..18d38cb59923d01b760cd5ae53064bf82b93c6d2 100644 (file)
@@ -81,6 +81,7 @@ static const char * const uabi_class_names[] = {
        [I915_ENGINE_CLASS_COPY] = "copy",
        [I915_ENGINE_CLASS_VIDEO] = "video",
        [I915_ENGINE_CLASS_VIDEO_ENHANCE] = "video-enhance",
+       [I915_ENGINE_CLASS_COMPUTE] = "compute",
 };
 
 static u64 busy_add(struct i915_gem_context *ctx, unsigned int class)
index 5f5b02b01ba041e71ccc3c40c368a03deee6d44d..f796c5e8e06066889cf71a5d101f8f8bb220cc86 100644 (file)
@@ -13,7 +13,7 @@
 
 #include "gt/intel_engine_types.h"
 
-#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_VIDEO_ENHANCE
+#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_COMPUTE
 
 struct drm_i915_private;
 
index ec000fc6c879aaeb4a5c80bc5ec19d117ea9d943..a2def7b270097836327d738e9eb3240fdf248ab4 100644 (file)
@@ -203,6 +203,15 @@ enum drm_i915_gem_engine_class {
         */
        I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
 
+       /**
+        * @I915_ENGINE_CLASS_COMPUTE:
+        *
+        * Compute engines support a subset of the instructions available
+        * on render engines:  compute engines support Compute (GPGPU) and
+        * programmable media workloads, but do not support the 3D pipeline.
+        */
+       I915_ENGINE_CLASS_COMPUTE       = 4,
+
        /* Values in this enum should be kept compact. */
 
        /**