CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
# CONFIG_COMPAT_BRK is not set
+ CONFIG_ARCH_MULTI_V4T=y
+ # CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_S3C24XX=y
CONFIG_S3C_ADC=y
-CONFIG_S3C24XX_PWM=y
# CONFIG_CPU_S3C2410 is not set
CONFIG_CPU_S3C2440=y
CONFIG_MACH_MINI2440=y
# SPDX-License-Identifier: GPL-2.0-only
menuconfig ARCH_SUNXI
bool "Allwinner SoCs"
- depends on ARCH_MULTI_V5 || ARCH_MULTI_V7
+ depends on (CPU_LITTLE_ENDIAN && ARCH_MULTI_V5) || ARCH_MULTI_V7
select ARCH_HAS_RESET_CONTROLLER
select CLKSRC_MMIO
- select GENERIC_IRQ_CHIP
select GPIOLIB
- select IRQ_DOMAIN_HIERARCHY
- select IRQ_FASTEOI_HIERARCHY_HANDLERS
select PINCTRL
select PM_OPP
select SUN4I_TIMER
default ARCH_SUNXI
select ARM_GIC
select ARM_PSCI
- select ARCH_SUPPORTS_BIG_ENDIAN
select HAVE_ARM_ARCH_TIMER
select SUN5I_HSTIMER
+ select SUNXI_NMI_INTC
config MACH_SUN8I
bool "Allwinner sun8i Family SoCs support"
dev_err(fbdev->dev, "failed to adjust LCD rate\n");
goto fail1;
}
- clk_enable(lcdc.lcd_ck);
+ clk_prepare_enable(lcdc.lcd_ck);
- r = request_irq(OMAP_LCDC_IRQ, lcdc_irq_handler, 0, MODULE_NAME, fbdev);
+ r = request_irq(fbdev->int_irq, lcdc_irq_handler, 0, MODULE_NAME, fbdev);
if (r) {
dev_err(fbdev->dev, "unable to get IRQ\n");
goto fail2;
fail4:
omap_free_lcd_dma();
fail3:
- free_irq(OMAP_LCDC_IRQ, lcdc.fbdev);
+ free_irq(fbdev->int_irq, lcdc.fbdev);
fail2:
- clk_disable(lcdc.lcd_ck);
+ clk_disable_unprepare(lcdc.lcd_ck);
fail1:
clk_put(lcdc.lcd_ck);
fail0:
free_palette_ram();
free_fbmem();
omap_free_lcd_dma();
- free_irq(OMAP_LCDC_IRQ, lcdc.fbdev);
+ free_irq(lcdc.fbdev->int_irq, lcdc.fbdev);
- clk_disable(lcdc.lcd_ck);
+ clk_disable_unprepare(lcdc.lcd_ck);
clk_put(lcdc.lcd_ck);
}