}
+bool HexagonInstrInfo::isTailCall(const MachineInstr *MI) const {
+ if (!MI->isBranch())
+ return false;
+
+ for (auto &Op : MI->operands())
+ if (Op.isGlobal() || Op.isSymbol())
+ return true;
+ return false;
+}
+
+
// Returns true when SU has a timing class TC1.
bool HexagonInstrInfo::isTC1(const MachineInstr *MI) const {
unsigned SchedClass = MI->getDesc().getSchedClass();
bool isSignExtendingLoad(const MachineInstr &MI) const;
bool isSolo(const MachineInstr* MI) const;
bool isSpillPredRegOp(const MachineInstr *MI) const;
+ bool isTailCall(const MachineInstr *MI) const;
bool isTC1(const MachineInstr *MI) const;
bool isTC2(const MachineInstr *MI) const;
bool isTC2Early(const MachineInstr *MI) const;
RC = HRI->getMinimalPhysRegClass(DepReg);
}
- if (I->isCall() || I->isReturn()) {
+ if (I->isCall() || I->isReturn() || HII->isTailCall(I)) {
if (!isRegDependence(DepType))
continue;
if (!isCallDependent(I, DepType, SUJ->Succs[i].getReg()))
--- /dev/null
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; There should only be one packet:
+; {
+; jump free
+; r0 = memw(r0 + #-4)
+; }
+;
+; CHECK: {
+; CHECK-NOT: {
+
+define void @fred(i8* %p) nounwind {
+entry:
+ %arrayidx = getelementptr inbounds i8, i8* %p, i32 -4
+ %t0 = bitcast i8* %arrayidx to i8**
+ %t1 = load i8*, i8** %t0, align 4
+ tail call void @free(i8* %t1)
+ ret void
+}
+
+; Function Attrs: nounwind
+declare void @free(i8* nocapture) nounwind
+