arm64: dts: renesas: r8a774a1: Add clkp2 clock to CAN nodes

According to the latest information, clkp2 is available on RZ/G2.
Modify CAN0 and CAN1 nodes accordingly.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index ef3cff2..de282c4 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -879,8 +879,10 @@
                                     "renesas,rcar-gen3-can";
                        reg = <0 0xe6c30000 0 0x1000>;
                        interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&cpg CPG_MOD 916>, <&can_clk>;
-                       clock-names = "clkp1", "can_clk";
+                       clocks = <&cpg CPG_MOD 916>,
+                                <&cpg CPG_CORE R8A774A1_CLK_CANFD>,
+                                <&can_clk>;
+                       clock-names = "clkp1", "clkp2", "can_clk";
                        power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
                        resets = <&cpg 916>;
                        status = "disabled";
@@ -891,8 +893,10 @@
                                     "renesas,rcar-gen3-can";
                        reg = <0 0xe6c38000 0 0x1000>;
                        interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&cpg CPG_MOD 915>, <&can_clk>;
-                       clock-names = "clkp1", "can_clk";
+                       clocks = <&cpg CPG_MOD 915>,
+                                <&cpg CPG_CORE R8A774A1_CLK_CANFD>,
+                                <&can_clk>;
+                       clock-names = "clkp1", "clkp2", "can_clk";
                        power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
                        resets = <&cpg 915>;
                        status = "disabled";