Add cache flush with dma buf sync

Change-Id: Ie277fe20529dca2450f8ace1f8b9a774a94e01ba

diff --git a/src/tbm_backend_dumb.c b/src/tbm_backend_dumb.c
index 931d71e..9b21984 100644 (file)
--- a/src/tbm_backend_dumb.c
+++ b/src/tbm_backend_dumb.c
@@ -51,6 +51,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include <hal-common.h>
 #include <hal-tbm-types.h>
 #include <hal-tbm-interface.h>
+#include <linux/dma-buf.h>
 #include "tbm_backend_log.h"
 
 #define TBM_COLOR_FORMAT_COUNT 4
@@ -1032,6 +1033,7 @@ tbm_dumb_bo_map(hal_tbm_bo *bo, hal_tbm_bo_device_type device,
        tbm_dumb_bo *bo_data = (tbm_dumb_bo *)bo;
        hal_tbm_bo_handle bo_handle;
        tbm_dumb_bufmgr *bufmgr_data;
+       struct dma_buf_sync sync = {0, };
 
        if (!bo_data) {
                if (error)
@@ -1071,6 +1073,22 @@ tbm_dumb_bo_map(hal_tbm_bo *bo, hal_tbm_bo_device_type device,
                return (hal_tbm_bo_handle) NULL;
        }
 
+       if (device == HAL_TBM_DEVICE_CPU) {
+               sync.flags |= DMA_BUF_SYNC_START;
+               if (opt & HAL_TBM_OPTION_READ)
+                       sync.flags |= DMA_BUF_SYNC_READ;
+               else if (opt & HAL_TBM_OPTION_WRITE)
+                       sync.flags |= DMA_BUF_SYNC_WRITE;
+
+               if (drmIoctl(bo_data->dmabuf, DMA_BUF_IOCTL_SYNC, &sync)) {
+                       TBM_BACKEND_WRN("fail to DMA_BUF_IOCTL_SYNC bo_data:%p (%m)",
+                                       bo_data);
+               }
+       }
+
+       bo_data->device = device;
+       bo_data->opt = opt;
+
        if (error)
                *error = HAL_TBM_ERROR_NONE;
 
@@ -1082,6 +1100,7 @@ tbm_dumb_bo_unmap(hal_tbm_bo *bo)
 {
        tbm_dumb_bo *bo_data = (tbm_dumb_bo *)bo;
        tbm_dumb_bufmgr *bufmgr_data;
+       struct dma_buf_sync sync = {0, };
 
        if (!bo_data)
                return HAL_TBM_ERROR_INVALID_PARAMETER;
@@ -1093,6 +1112,22 @@ tbm_dumb_bo_unmap(hal_tbm_bo *bo)
        if (!bo_data->gem)
                return HAL_TBM_ERROR_INVALID_PARAMETER;
 
+       if (bo_data->device == HAL_TBM_DEVICE_CPU) {
+               sync.flags |= DMA_BUF_SYNC_END;
+               if (bo_data->opt & HAL_TBM_OPTION_READ)
+                       sync.flags |= DMA_BUF_SYNC_READ;
+               else if (bo_data->opt & HAL_TBM_OPTION_WRITE)
+                       sync.flags |= DMA_BUF_SYNC_WRITE;
+
+               if (drmIoctl(bo_data->dmabuf, DMA_BUF_IOCTL_SYNC, &sync)) {
+                       TBM_BACKEND_WRN("fail to DMA_BUF_IOCTL_SYNC bo_data:%p (%m)",
+                                       bo_data);
+               }
+       }
+
+       bo_data->device = 0;
+       bo_data->opt = 0;
+
        TBM_BACKEND_DBG("bo_data:%p, gem:%d name:%d fd:%d",
                        bo_data,
                        bo_data->gem,