bool addILPOpts() override;
void addPreRegAlloc() override;
void addPostRegAlloc() override;
- void addMachineLateOptimization() override;
bool addGCPasses() override { return false; }
void addPreEmitPass() override;
};
// TODO: The following CodeGen passes don't currently support code containing
// virtual registers. Consider removing their restrictions and re-enabling
// them.
- //
// Has no asserts of its own, but was not written to handle virtual regs.
disablePass(&ShrinkWrapID);
// We use our own PrologEpilogInserter which is very slightly modified to
// tolerate virtual registers.
disablePass(&PrologEpilogCodeInserterID);
- // Fails with: should be run after register allocation.
+
+ // These functions all require the AllVRegsAllocated property.
disablePass(&MachineCopyPropagationID);
+ disablePass(&PostRASchedulerID);
+ disablePass(&FuncletLayoutID);
+ disablePass(&StackMapLivenessID);
+ disablePass(&LiveDebugValuesID);
if (getOptLevel() != CodeGenOpt::None) {
// Mark registers as representing wasm's expression stack.
addPass(createWebAssemblyPEI());
}
-void WebAssemblyPassConfig::addMachineLateOptimization() {
- disablePass(&MachineCopyPropagationID);
- disablePass(&PostRASchedulerID);
- TargetPassConfig::addMachineLateOptimization();
-}
-
void WebAssemblyPassConfig::addPreEmitPass() {
TargetPassConfig::addPreEmitPass();
// Eliminate multiple-entry loops.
addPass(createWebAssemblyFixIrreducibleControlFlow());
- disablePass(&FuncletLayoutID);
- disablePass(&StackMapLivenessID);
- disablePass(&LiveDebugValuesID);
// Put the CFG in structured form; insert BLOCK and LOOP markers.
addPass(createWebAssemblyCFGStackify());