unsigned size, struct amdgpu_ib *ib);
void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- struct amdgpu_ib *ib, void *owner);
+ struct amdgpu_ib *ib, void *owner,
+ struct fence **f);
int amdgpu_ib_pool_init(struct amdgpu_device *adev);
void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
* @num_ibs: number of IBs to schedule
* @ibs: IB objects to schedule
* @owner: owner for creating the fences
+ * @f: fence created during this submission
*
* Schedule an IB on the associated ring (all asics).
* Returns 0 on success, error on failure.
* to SI there was just a DE IB.
*/
int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- struct amdgpu_ib *ibs, void *owner)
+ struct amdgpu_ib *ibs, void *owner,
+ struct fence **f)
{
struct amdgpu_device *adev = ring->adev;
struct amdgpu_ib *ib = &ibs[0];
AMDGPU_FENCE_FLAG_64BIT);
}
+ if (f)
+ *f = fence_get(&ib->fence->base);
+
amdgpu_ring_commit(ring);
return 0;
}
static struct fence *amdgpu_sched_run_job(struct amd_sched_job *sched_job)
{
- struct amdgpu_fence *fence = NULL;
+ struct fence *fence = NULL;
struct amdgpu_job *job;
int r;
}
job = to_amdgpu_job(sched_job);
trace_amdgpu_sched_run_job(job);
- r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs, job->owner);
+ r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs,
+ job->owner, &fence);
if (r) {
DRM_ERROR("Error scheduling IBs (%d)\n", r);
goto err;
}
- fence = job->ibs[job->num_ibs - 1].fence;
- fence_get(&fence->base);
-
err:
if (job->free_job)
job->free_job(job);
kfree(job);
- return fence ? &fence->base : NULL;
+ return fence;
}
struct amd_sched_backend_ops amdgpu_sched_ops = {