(PIPE_CONTROL_L3_READ_ONLY_CACHE_INVALIDATE | \
PIPE_CONTROL_CONST_CACHE_INVALIDATE)
+#define PIPE_CONTROL_GRAPHICS_BITS \
+ (PIPE_CONTROL_RENDER_TARGET_FLUSH | \
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
+ PIPE_CONTROL_TILE_CACHE_FLUSH | \
+ PIPE_CONTROL_DEPTH_STALL | \
+ PIPE_CONTROL_STALL_AT_SCOREBOARD | \
+ PIPE_CONTROL_PSS_STALL_SYNC | \
+ PIPE_CONTROL_VF_CACHE_INVALIDATE | \
+ PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET | \
+ PIPE_CONTROL_L3_READ_ONLY_CACHE_INVALIDATE |\
+ PIPE_CONTROL_WRITE_DEPTH_COUNT)
+
enum iris_predicate_state {
/* The first two states are used if we can determine whether to draw
* without having to look at the values in the query object buffer. This
PIPE_CONTROL_TILE_CACHE_FLUSH |
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_DATA_CACHE_FLUSH;
+
+ if (batch->name == IRIS_BATCH_COMPUTE)
+ pc &= ~PIPE_CONTROL_GRAPHICS_BITS;
}
iris_emit_pipe_control_write(batch, "fence: fine", pc,
iris_resource_bo(fine->ref.res),
}
if (bits) {
+ /* Stall-at-scoreboard is not supported by the compute pipeline, use the
+ * documented sequence of two PIPE_CONTROLs with PIPE_CONTROL_FLUSH_ENABLE
+ * set in the second PIPE_CONTROL in order to obtain a similar effect.
+ */
+ const bool compute_stall_sequence = batch->name == IRIS_BATCH_COMPUTE &&
+ (bits & PIPE_CONTROL_STALL_AT_SCOREBOARD) &&
+ !(bits & PIPE_CONTROL_CACHE_FLUSH_BITS);
+
/* Stall-at-scoreboard is not expected to work in combination with other
* flush bits.
*/
if (bits & PIPE_CONTROL_CACHE_FLUSH_BITS)
bits &= ~PIPE_CONTROL_STALL_AT_SCOREBOARD;
+ if (batch->name == IRIS_BATCH_COMPUTE)
+ bits &= ~PIPE_CONTROL_GRAPHICS_BITS;
+
/* Emit any required flushes and invalidations. */
- if (bits & all_flush_bits)
+ if ((bits & all_flush_bits) || compute_stall_sequence)
iris_emit_end_of_pipe_sync(batch, "cache tracker: flush",
bits & all_flush_bits);
- if (bits & ~all_flush_bits)
+ if ((bits & ~all_flush_bits) || compute_stall_sequence)
iris_emit_pipe_control_flush(batch, "cache tracker: invalidate",
- bits & ~all_flush_bits);
+ (bits & ~all_flush_bits) |
+ (compute_stall_sequence ?
+ PIPE_CONTROL_FLUSH_ENABLE : 0));
}
}
}
iris_foreach_batch(ice, batch) {
+ const unsigned allowed_bits =
+ batch->name == IRIS_BATCH_COMPUTE ? ~PIPE_CONTROL_GRAPHICS_BITS : ~0u;
+
if (batch->contains_draw) {
iris_batch_maybe_flush(batch, 24);
- iris_emit_pipe_control_flush(batch, "API: memory barrier", bits);
+ iris_emit_pipe_control_flush(batch,
+ "API: memory barrier",
+ bits & allowed_bits);
}
}
}
struct iris_bo *bo = iris_resource_bo(q->query_state_ref.res);
if (!iris_is_query_pipelined(q)) {
+ enum pipe_control_flags flags = PIPE_CONTROL_CS_STALL |
+ PIPE_CONTROL_STALL_AT_SCOREBOARD;
+ if (batch->name == IRIS_BATCH_COMPUTE) {
+ iris_emit_pipe_control_write(batch,
+ "query: write immediate for compute batches",
+ PIPE_CONTROL_WRITE_IMMEDIATE,
+ bo,
+ offset,
+ 0ull);
+ flags = PIPE_CONTROL_FLUSH_ENABLE;
+ }
+
iris_emit_pipe_control_flush(batch,
"query: non-pipelined snapshot write",
- PIPE_CONTROL_CS_STALL |
- PIPE_CONTROL_STALL_AT_SCOREBOARD);
+ flags);
q->stalled = true;
}
enum pipe_control_flags flags = PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_FLUSH_HDC;
- if (pipeline == GPGPU) {
+ if (pipeline == GPGPU && batch->name == IRIS_BATCH_RENDER) {
flags |= PIPE_CONTROL_RENDER_TARGET_FLUSH |
PIPE_CONTROL_DEPTH_CACHE_FLUSH;
}