return Tmp;
}
- case Instruction::Trunc:
- // FIXME: it's tricky to do anything useful for this, but it is an
- // important case for targets like X86.
- break;
+ case Instruction::Trunc: {
+ // If the input contained enough sign bits that some remain after the
+ // truncation, then we can make use of that. Otherwise we don't know
+ // anything.
+ Tmp = ComputeNumSignBits(U->getOperand(0), Depth + 1, Q);
+ unsigned OperandTyBits = U->getOperand(0)->getType()->getScalarSizeInBits();
+ if (Tmp > (OperandTyBits - TyBits))
+ return Tmp - (OperandTyBits - TyBits);
+
+ return 1;
+ }
case Instruction::ExtractElement:
// Look through extract element. At the moment we keep this simple and
; CHECK-NEXT: [[TMP1:%.*]] = shl i64 [[A0:%.*]], 48
; CHECK-NEXT: [[TMP2:%.*]] = ashr i64 [[TMP1]], 63
; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i8
-; CHECK-NEXT: [[NEG:%.*]] = add i8 [[TMP3]], 10
+; CHECK-NEXT: [[NEG:%.*]] = add nsw i8 [[TMP3]], 10
; CHECK-NEXT: ret i8 [[NEG]]
;
%shift = lshr i64 %a0, 15
; CHECK-NEXT: [[TMP1:%.*]] = shl i64 [[A0:%.*]], 48
; CHECK-NEXT: [[TMP2:%.*]] = ashr i64 [[TMP1]], 63
; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i8
-; CHECK-NEXT: [[NARROW:%.*]] = add i8 [[TMP3]], 10
+; CHECK-NEXT: [[NARROW:%.*]] = add nsw i8 [[TMP3]], 10
; CHECK-NEXT: [[NEG:%.*]] = zext i8 [[NARROW]] to i32
; CHECK-NEXT: ret i32 [[NEG]]
;
--- /dev/null
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+
+define <4 x i16> @trunc_add_nsw(<4 x i32> %0) {
+; CHECK-LABEL: @trunc_add_nsw(
+; CHECK-NEXT: [[TMP2:%.*]] = ashr <4 x i32> [[TMP0:%.*]], <i32 17, i32 17, i32 17, i32 17>
+; CHECK-NEXT: [[TMP3:%.*]] = trunc <4 x i32> [[TMP2]] to <4 x i16>
+; CHECK-NEXT: [[TMP4:%.*]] = add nsw <4 x i16> [[TMP3]], <i16 1, i16 1, i16 1, i16 1>
+; CHECK-NEXT: ret <4 x i16> [[TMP4]]
+;
+ %2 = ashr <4 x i32> %0, <i32 17, i32 17, i32 17, i32 17>
+ %3 = trunc <4 x i32> %2 to <4 x i16>
+ %4 = add <4 x i16> %3, <i16 1, i16 1, i16 1, i16 1>
+ ret <4 x i16> %4
+}
+
+define <4 x i16> @trunc_add_no_nsw(<4 x i32> %0) {
+; CHECK-LABEL: @trunc_add_no_nsw(
+; CHECK-NEXT: [[TMP2:%.*]] = lshr <4 x i32> [[TMP0:%.*]], <i32 16, i32 16, i32 16, i32 16>
+; CHECK-NEXT: [[TMP3:%.*]] = trunc <4 x i32> [[TMP2]] to <4 x i16>
+; CHECK-NEXT: [[TMP4:%.*]] = add <4 x i16> [[TMP3]], <i16 1, i16 1, i16 1, i16 1>
+; CHECK-NEXT: ret <4 x i16> [[TMP4]]
+;
+ %2 = ashr <4 x i32> %0, <i32 16, i32 16, i32 16, i32 16>
+ %3 = trunc <4 x i32> %2 to <4 x i16>
+ %4 = add <4 x i16> %3, <i16 1, i16 1, i16 1, i16 1>
+ ret <4 x i16> %4
+}
+
+define <4 x i16> @trunc_add_mixed(<4 x i32> %0) {
+; CHECK-LABEL: @trunc_add_mixed(
+; CHECK-NEXT: [[TMP2:%.*]] = ashr <4 x i32> [[TMP0:%.*]], <i32 17, i32 16, i32 17, i32 16>
+; CHECK-NEXT: [[TMP3:%.*]] = trunc <4 x i32> [[TMP2]] to <4 x i16>
+; CHECK-NEXT: [[TMP4:%.*]] = add <4 x i16> [[TMP3]], <i16 1, i16 1, i16 1, i16 1>
+; CHECK-NEXT: ret <4 x i16> [[TMP4]]
+;
+ %2 = ashr <4 x i32> %0, <i32 17, i32 16, i32 17, i32 16>
+ %3 = trunc <4 x i32> %2 to <4 x i16>
+ %4 = add <4 x i16> %3, <i16 1, i16 1, i16 1, i16 1>
+ ret <4 x i16> %4
+}