drm/i915/tgl: Implement Wa_1409804808

This workaround the CS not done issue on PIPE_CONTROL.

v2:
- replaced BIT() by REG_BIT() in all GEN7_ROW_CHICKEN2() bits
- shortened the name of the new bit

BSpec: 52890
BSpec: 46218
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200227220101.321671-1-jose.souza@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 06cef3c..d402b8e 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1362,6 +1362,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
                             GEN12_DISABLE_EARLY_READ);
        }
 
+       if (IS_TIGERLAKE(i915)) {
+               /* Wa_1409804808:tgl */
+               wa_masked_en(wal, GEN7_ROW_CHICKEN2,
+                            GEN12_PUSH_CONST_DEREF_HOLD_DIS);
+       }
+
        if (IS_GEN(i915, 11)) {
                /* This is not an Wa. Enable for better image quality */
                wa_masked_en(wal,

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 72de959..acace01 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9140,8 +9140,9 @@ enum {
 #define   THROTTLE_12_5                                (7 << 2)
 #define   DISABLE_EARLY_EOT                    (1 << 1)
 
-#define GEN7_ROW_CHICKEN2              _MMIO(0xe4f4)
-#define GEN12_DISABLE_EARLY_READ       BIT(14)
+#define GEN7_ROW_CHICKEN2                      _MMIO(0xe4f4)
+#define   GEN12_DISABLE_EARLY_READ             REG_BIT(14)
+#define   GEN12_PUSH_CONST_DEREF_HOLD_DIS      REG_BIT(8)
 
 #define GEN7_ROW_CHICKEN2_GT2          _MMIO(0xf4f4)
 #define   DOP_CLOCK_GATING_DISABLE     (1 << 0)