;
; RV64ZBS-LABEL: bclr_i32:
; RV64ZBS: # %bb.0:
-; RV64ZBS-NEXT: li a2, 1
-; RV64ZBS-NEXT: sllw a1, a2, a1
-; RV64ZBS-NEXT: not a1, a1
-; RV64ZBS-NEXT: and a0, a1, a0
+; RV64ZBS-NEXT: andi a1, a1, 31
+; RV64ZBS-NEXT: bclr a0, a0, a1
+; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%and = and i32 %b, 31
%shl = shl nuw i32 1, %and
;
; RV64ZBS-LABEL: bclr_i32_no_mask:
; RV64ZBS: # %bb.0:
-; RV64ZBS-NEXT: li a2, 1
-; RV64ZBS-NEXT: sllw a1, a2, a1
-; RV64ZBS-NEXT: not a1, a1
-; RV64ZBS-NEXT: and a0, a1, a0
+; RV64ZBS-NEXT: bclr a0, a0, a1
+; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%shl = shl i32 1, %b
%neg = xor i32 %shl, -1
; RV64ZBS-LABEL: bclr_i32_load:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: lw a0, 0(a0)
-; RV64ZBS-NEXT: li a2, 1
-; RV64ZBS-NEXT: sllw a1, a2, a1
-; RV64ZBS-NEXT: not a1, a1
-; RV64ZBS-NEXT: and a0, a1, a0
+; RV64ZBS-NEXT: bclr a0, a0, a1
+; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%a = load i32, i32* %p
%shl = shl i32 1, %b
;
; RV64ZBS-LABEL: bset_i32:
; RV64ZBS: # %bb.0:
-; RV64ZBS-NEXT: li a2, 1
-; RV64ZBS-NEXT: sllw a1, a2, a1
-; RV64ZBS-NEXT: or a0, a1, a0
+; RV64ZBS-NEXT: andi a1, a1, 31
+; RV64ZBS-NEXT: bset a0, a0, a1
+; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%and = and i32 %b, 31
%shl = shl nuw i32 1, %and
;
; RV64ZBS-LABEL: bset_i32_no_mask:
; RV64ZBS: # %bb.0:
-; RV64ZBS-NEXT: li a2, 1
-; RV64ZBS-NEXT: sllw a1, a2, a1
-; RV64ZBS-NEXT: or a0, a1, a0
+; RV64ZBS-NEXT: bset a0, a0, a1
+; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%shl = shl i32 1, %b
%or = or i32 %shl, %a
; RV64ZBS-LABEL: bset_i32_load:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: lw a0, 0(a0)
-; RV64ZBS-NEXT: li a2, 1
-; RV64ZBS-NEXT: sllw a1, a2, a1
-; RV64ZBS-NEXT: or a0, a1, a0
+; RV64ZBS-NEXT: bset a0, a0, a1
+; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%a = load i32, i32* %p
%shl = shl i32 1, %b
;
; RV64ZBS-LABEL: bset_i32_zero:
; RV64ZBS: # %bb.0:
-; RV64ZBS-NEXT: li a1, 1
-; RV64ZBS-NEXT: sllw a0, a1, a0
+; RV64ZBS-NEXT: bset a0, zero, a0
+; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%shl = shl i32 1, %a
ret i32 %shl
;
; RV64ZBS-LABEL: binv_i32:
; RV64ZBS: # %bb.0:
-; RV64ZBS-NEXT: li a2, 1
-; RV64ZBS-NEXT: sllw a1, a2, a1
-; RV64ZBS-NEXT: xor a0, a1, a0
+; RV64ZBS-NEXT: andi a1, a1, 31
+; RV64ZBS-NEXT: binv a0, a0, a1
+; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%and = and i32 %b, 31
%shl = shl nuw i32 1, %and
;
; RV64ZBS-LABEL: binv_i32_no_mask:
; RV64ZBS: # %bb.0:
-; RV64ZBS-NEXT: li a2, 1
-; RV64ZBS-NEXT: sllw a1, a2, a1
-; RV64ZBS-NEXT: xor a0, a1, a0
+; RV64ZBS-NEXT: binv a0, a0, a1
+; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%shl = shl i32 1, %b
%xor = xor i32 %shl, %a
; RV64ZBS-LABEL: binv_i32_load:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: lw a0, 0(a0)
-; RV64ZBS-NEXT: li a2, 1
-; RV64ZBS-NEXT: sllw a1, a2, a1
-; RV64ZBS-NEXT: xor a0, a1, a0
+; RV64ZBS-NEXT: binv a0, a0, a1
+; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%a = load i32, i32* %p
%shl = shl i32 1, %b