break;
case AC2_VI:
- AcmCtrl |= AcmHw_ViqEn;
+ AcmCtrl |= ACM_HW_VIQ_EN;
break;
case AC3_VO:
- AcmCtrl |= AcmHw_VoqEn;
+ AcmCtrl |= ACM_HW_VOQ_EN;
break;
}
} else {
break;
case AC2_VI:
- AcmCtrl &= (~AcmHw_ViqEn);
+ AcmCtrl &= (~ACM_HW_VIQ_EN);
break;
case AC3_VO:
#define CPU_GEN_NO_LOOPBACK_SET 0x00080000
ACM_HW_CTRL = 0x171,
#define ACM_HW_BEQ_EN BIT1
-#define AcmHw_ViqEn BIT2
-#define AcmHw_VoqEn BIT3
+#define ACM_HW_VIQ_EN BIT2
+#define ACM_HW_VOQ_EN BIT3
RQPN1 = 0x180,
RQPN2 = 0x184,
RQPN3 = 0x188,
#define GPI 0x108
-#define ANAPAR_FOR_8192PciE 0x17
+#define ANAPAR_FOR_8192PCIE 0x17
#endif
rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0);
rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0);
- rtl92e_writeb(dev, ANAPAR_FOR_8192PciE, 0x07);
+ rtl92e_writeb(dev, ANAPAR_FOR_8192PCIE, 0x07);
}