#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CLKS_NR_MAIN (CLK_SCLK_MMC2 + 1)
+#define CLKS_NR_DMC (CLK_DIV_DMCD + 1)
+#define CLKS_NR_ISP (CLK_SCLK_MPWM_ISP + 1)
+
static const unsigned long exynos3250_cmu_clk_regs[] __initconst = {
SRC_LEFTBUS,
DIV_LEFTBUS,
.nr_fixed_factor_clks = ARRAY_SIZE(fixed_factor_clks),
.cpu_clks = exynos3250_cpu_clks,
.nr_cpu_clks = ARRAY_SIZE(exynos3250_cpu_clks),
- .nr_clk_ids = CLK_NR_CLKS,
+ .nr_clk_ids = CLKS_NR_MAIN,
.clk_regs = exynos3250_cmu_clk_regs,
.nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_clk_regs),
};
.nr_mux_clks = ARRAY_SIZE(dmc_mux_clks),
.div_clks = dmc_div_clks,
.nr_div_clks = ARRAY_SIZE(dmc_div_clks),
- .nr_clk_ids = NR_CLKS_DMC,
+ .nr_clk_ids = CLKS_NR_DMC,
.clk_regs = exynos3250_cmu_dmc_clk_regs,
.nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs),
};
.nr_div_clks = ARRAY_SIZE(isp_div_clks),
.gate_clks = isp_gate_clks,
.nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
- .nr_clk_ids = NR_CLKS_ISP,
+ .nr_clk_ids = CLKS_NR_ISP,
};
static int __init exynos3250_cmu_isp_probe(struct platform_device *pdev)