bool rx_start;
bool is_master_mode;
const struct rk_i2s_pins *pins;
+ unsigned int bclk_ratio;
};
static int i2s_runtime_suspend(struct device *dev)
if (i2s->is_master_mode) {
mclk_rate = clk_get_rate(i2s->mclk);
- bclk_rate = 2 * 32 * params_rate(params);
+ bclk_rate = i2s->bclk_ratio * params_rate(params);
if (bclk_rate == 0 || mclk_rate % bclk_rate)
return -EINVAL;
return ret;
}
+static int rockchip_i2s_set_bclk_ratio(struct snd_soc_dai *dai,
+ unsigned int ratio)
+{
+ struct rk_i2s_dev *i2s = to_info(dai);
+
+ i2s->bclk_ratio = ratio;
+
+ return 0;
+}
+
static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
unsigned int freq, int dir)
{
static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
.hw_params = rockchip_i2s_hw_params,
+ .set_bclk_ratio = rockchip_i2s_set_bclk_ratio,
.set_sysclk = rockchip_i2s_set_sysclk,
.set_fmt = rockchip_i2s_set_fmt,
.trigger = rockchip_i2s_trigger,
i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
i2s->capture_dma_data.maxburst = 4;
+ i2s->bclk_ratio = 64;
+
dev_set_drvdata(&pdev->dev, i2s);
pm_runtime_enable(&pdev->dev);