break;
case SystemZ::CallBR:
- LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R1D);
+ LoweredMI = MCInstBuilder(SystemZ::BR)
+ .addReg(MI->getOperand(0).getReg());
break;
case SystemZ::CallBCR:
LoweredMI = MCInstBuilder(SystemZ::BCR)
.addImm(MI->getOperand(0).getImm())
.addImm(MI->getOperand(1).getImm())
- .addReg(SystemZ::R1D);
+ .addReg(MI->getOperand(2).getReg());
break;
case SystemZ::CRBCall:
.addReg(MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg())
.addImm(MI->getOperand(2).getImm())
- .addReg(SystemZ::R1D)
+ .addReg(MI->getOperand(3).getReg())
.addImm(0);
break;
.addReg(MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg())
.addImm(MI->getOperand(2).getImm())
- .addReg(SystemZ::R1D)
+ .addReg(MI->getOperand(3).getReg())
.addImm(0);
break;
.addReg(MI->getOperand(0).getReg())
.addImm(MI->getOperand(1).getImm())
.addImm(MI->getOperand(2).getImm())
- .addReg(SystemZ::R1D)
+ .addReg(MI->getOperand(3).getReg())
.addImm(0);
break;
.addReg(MI->getOperand(0).getReg())
.addImm(MI->getOperand(1).getImm())
.addImm(MI->getOperand(2).getImm())
- .addReg(SystemZ::R1D)
+ .addReg(MI->getOperand(3).getReg())
.addImm(0);
break;
.addReg(MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg())
.addImm(MI->getOperand(2).getImm())
- .addReg(SystemZ::R1D)
+ .addReg(MI->getOperand(3).getReg())
.addImm(0);
break;
.addReg(MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg())
.addImm(MI->getOperand(2).getImm())
- .addReg(SystemZ::R1D)
+ .addReg(MI->getOperand(3).getReg())
.addImm(0);
break;
.addReg(MI->getOperand(0).getReg())
.addImm(MI->getOperand(1).getImm())
.addImm(MI->getOperand(2).getImm())
- .addReg(SystemZ::R1D)
+ .addReg(MI->getOperand(3).getReg())
.addImm(0);
break;
.addReg(MI->getOperand(0).getReg())
.addImm(MI->getOperand(1).getImm())
.addImm(MI->getOperand(2).getImm())
- .addReg(SystemZ::R1D)
+ .addReg(MI->getOperand(3).getReg())
.addImm(0);
break;
MachineOperand CCMask(MBBI->getOperand(1));
assert((CCMask.getImm() & ~SystemZ::CCMASK_ICMP) == 0 &&
"Invalid condition-code mask for integer comparison");
- // This is only valid for CompareAndBranch.
+ // This is only valid for CompareAndBranch and CompareAndSibcall.
MachineOperand Target(MBBI->getOperand(
- Type == SystemZII::CompareAndBranch ? 2 : 0));
+ (Type == SystemZII::CompareAndBranch ||
+ Type == SystemZII::CompareAndSibcall) ? 2 : 0));
const uint32_t *RegMask;
if (Type == SystemZII::CompareAndSibcall)
- RegMask = MBBI->getOperand(2).getRegMask();
+ RegMask = MBBI->getOperand(3).getRegMask();
// Clear out all current operands.
int CCUse = MBBI->findRegisterUseOperandIdx(SystemZ::CC, false, TRI);
assert(CCUse >= 0 && "BRC/BCR must use CC");
Branch->RemoveOperand(CCUse);
- // Remove target (branch) or regmask (sibcall).
+ // Remove regmask (sibcall).
+ if (Type == SystemZII::CompareAndSibcall)
+ Branch->RemoveOperand(3);
+ // Remove target (branch or sibcall).
if (Type == SystemZII::CompareAndBranch ||
Type == SystemZII::CompareAndSibcall)
Branch->RemoveOperand(2);
RegState::ImplicitDefine | RegState::Dead);
}
- if (Type == SystemZII::CompareAndSibcall)
+ if (Type == SystemZII::CompareAndSibcall) {
+ MIB.add(Target);
MIB.addRegMask(RegMask);
+ }
// Clear any intervening kills of SrcReg and SrcReg2.
MBBI = Compare;
[(z_tls_ldcall tglobaltlsaddr:$I2)]>;
}
-// Sibling calls. Indirect sibling calls must be via R1, since R2 upwards
-// are argument registers and since branching to R0 is a no-op.
+// Sibling calls.
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
def CallJG : Alias<6, (outs), (ins pcrel32:$I2),
[(z_sibcall pcrel32:$I2)]>;
- let Uses = [R1D] in
- def CallBR : Alias<2, (outs), (ins), [(z_sibcall R1D)]>;
+ def CallBR : Alias<2, (outs), (ins ADDR64:$R2),
+ [(z_sibcall ADDR64:$R2)]>;
}
// Conditional sibling calls.
let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in {
def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1,
pcrel32:$I2), []>;
- let Uses = [R1D] in
- def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>;
+ def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1,
+ ADDR64:$R2), []>;
}
// Fused compare and conditional sibling calls.
-let isCall = 1, isTerminator = 1, isReturn = 1, Uses = [R1D] in {
- def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>;
- def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>;
- def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>;
- def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>;
- def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>;
- def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>;
- def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>;
- def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>;
+let isCall = 1, isTerminator = 1, isReturn = 1 in {
+ def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>;
+ def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>;
+ def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3, ADDR64:$R4), []>;
+ def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3, ADDR64:$R4), []>;
+ def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>;
+ def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>;
+ def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3, ADDR64:$R4), []>;
+ def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3, ADDR64:$R4), []>;
}
// A return instruction (br %r14).