clk: nuvoton: Update all constant hex values to lowercase

The constant hex values used to define register offsets were written
in uppercase. This patch update all these constant hex values to
be lowercase.

Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

diff --git a/drivers/clk/nuvoton/clk-ma35d1.c b/drivers/clk/nuvoton/clk-ma35d1.c
index 8dfa762..733750d 100644 (file)
--- a/drivers/clk/nuvoton/clk-ma35d1.c
+++ b/drivers/clk/nuvoton/clk-ma35d1.c
@@ -22,19 +22,19 @@ static DEFINE_SPINLOCK(ma35d1_lock);
 #define REG_CLK_PWRCTL         0x00
 #define REG_CLK_SYSCLK0                0x04
 #define REG_CLK_SYSCLK1                0x08
-#define REG_CLK_APBCLK0                0x0C
+#define REG_CLK_APBCLK0                0x0c
 #define REG_CLK_APBCLK1                0x10
 #define REG_CLK_APBCLK2                0x14
 #define REG_CLK_CLKSEL0                0x18
-#define REG_CLK_CLKSEL1                0x1C
+#define REG_CLK_CLKSEL1                0x1c
 #define REG_CLK_CLKSEL2                0x20
 #define REG_CLK_CLKSEL3                0x24
 #define REG_CLK_CLKSEL4                0x28
-#define REG_CLK_CLKDIV0                0x2C
+#define REG_CLK_CLKDIV0                0x2c
 #define REG_CLK_CLKDIV1                0x30
 #define REG_CLK_CLKDIV2                0x34
 #define REG_CLK_CLKDIV3                0x38
-#define REG_CLK_CLKDIV4                0x3C
+#define REG_CLK_CLKDIV4                0x3c
 #define REG_CLK_CLKOCTL                0x40
 #define REG_CLK_STATUS         0x50
 #define REG_CLK_PLL0CTL0       0x60
@@ -44,18 +44,18 @@ static DEFINE_SPINLOCK(ma35d1_lock);
 #define REG_CLK_PLL3CTL0       0x90
 #define REG_CLK_PLL3CTL1       0x94
 #define REG_CLK_PLL3CTL2       0x98
-#define REG_CLK_PLL4CTL0       0xA0
-#define REG_CLK_PLL4CTL1       0xA4
-#define REG_CLK_PLL4CTL2       0xA8
-#define REG_CLK_PLL5CTL0       0xB0
-#define REG_CLK_PLL5CTL1       0xB4
-#define REG_CLK_PLL5CTL2       0xB8
-#define REG_CLK_CLKDCTL                0xC0
-#define REG_CLK_CLKDSTS                0xC4
-#define REG_CLK_CDUPB          0xC8
-#define REG_CLK_CDLOWB         0xCC
-#define REG_CLK_CKFLTRCTL      0xD0
-#define REG_CLK_TESTCLK                0xF0
+#define REG_CLK_PLL4CTL0       0xa0
+#define REG_CLK_PLL4CTL1       0xa4
+#define REG_CLK_PLL4CTL2       0xa8
+#define REG_CLK_PLL5CTL0       0xb0
+#define REG_CLK_PLL5CTL1       0xb4
+#define REG_CLK_PLL5CTL2       0xb8
+#define REG_CLK_CLKDCTL                0xc0
+#define REG_CLK_CLKDSTS                0xc4
+#define REG_CLK_CDUPB          0xc8
+#define REG_CLK_CDLOWB         0xcc
+#define REG_CLK_CKFLTRCTL      0xd0
+#define REG_CLK_TESTCLK                0xf0
 #define REG_CLK_PLLCTL         0x40
 
 #define PLL_MODE_INT            0