drm/amd/display: minor dp link training refactor

[how]
The change includes some dp link training refactors:
1. break down is_ch_eq_done to checking individual conditions in
its own function.
2. update dpcd_set_training_pattern to take in dc_dp_training_pattern
as input.
3. moving lttpr mode struct definition into link_service_types.h

Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Reviewed-by: George Shen <George.Shen@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 46a1d81..37ec894 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -108,10 +108,50 @@ static void wait_for_training_aux_rd_interval(
                wait_in_micro_secs);
 }
 
+static enum dpcd_training_patterns
+       dc_dp_training_pattern_to_dpcd_training_pattern(
+       struct dc_link *link,
+       enum dc_dp_training_pattern pattern)
+{
+       enum dpcd_training_patterns dpcd_tr_pattern =
+       DPCD_TRAINING_PATTERN_VIDEOIDLE;
+
+       switch (pattern) {
+       case DP_TRAINING_PATTERN_SEQUENCE_1:
+               dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
+               break;
+       case DP_TRAINING_PATTERN_SEQUENCE_2:
+               dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
+               break;
+       case DP_TRAINING_PATTERN_SEQUENCE_3:
+               dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
+               break;
+       case DP_TRAINING_PATTERN_SEQUENCE_4:
+               dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
+               break;
+       case DP_TRAINING_PATTERN_VIDEOIDLE:
+               dpcd_tr_pattern = DPCD_TRAINING_PATTERN_VIDEOIDLE;
+               break;
+       default:
+               ASSERT(0);
+               DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
+                       __func__, pattern);
+               break;
+       }
+
+       return dpcd_tr_pattern;
+}
+
 static void dpcd_set_training_pattern(
        struct dc_link *link,
-       union dpcd_training_pattern dpcd_pattern)
+       enum dc_dp_training_pattern training_pattern)
 {
+       union dpcd_training_pattern dpcd_pattern = { {0} };
+
+       dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
+                       dc_dp_training_pattern_to_dpcd_training_pattern(
+                                       link, training_pattern);
+
        core_link_write_dpcd(
                link,
                DP_TRAINING_PATTERN_SET,
@@ -240,37 +280,6 @@ static void dpcd_set_link_settings(
        }
 }
 
-static enum dpcd_training_patterns
-       dc_dp_training_pattern_to_dpcd_training_pattern(
-       struct dc_link *link,
-       enum dc_dp_training_pattern pattern)
-{
-       enum dpcd_training_patterns dpcd_tr_pattern =
-       DPCD_TRAINING_PATTERN_VIDEOIDLE;
-
-       switch (pattern) {
-       case DP_TRAINING_PATTERN_SEQUENCE_1:
-               dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
-               break;
-       case DP_TRAINING_PATTERN_SEQUENCE_2:
-               dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
-               break;
-       case DP_TRAINING_PATTERN_SEQUENCE_3:
-               dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
-               break;
-       case DP_TRAINING_PATTERN_SEQUENCE_4:
-               dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
-               break;
-       default:
-               ASSERT(0);
-               DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
-                       __func__, pattern);
-               break;
-       }
-
-       return dpcd_tr_pattern;
-}
-
 static uint8_t dc_dp_initialize_scrambling_data_symbols(
        struct dc_link *link,
        enum dc_dp_training_pattern pattern)
@@ -433,20 +442,30 @@ static bool is_cr_done(enum dc_lane_count ln_count,
 }
 
 static bool is_ch_eq_done(enum dc_lane_count ln_count,
-       union lane_status *dpcd_lane_status,
-       union lane_align_status_updated *lane_status_updated)
+               union lane_status *dpcd_lane_status)
 {
+       bool done = true;
        uint32_t lane;
-       if (!lane_status_updated->bits.INTERLANE_ALIGN_DONE)
-               return false;
-       else {
-               for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
-                       if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0 ||
-                               !dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
-                               return false;
-               }
-       }
-       return true;
+       for (lane = 0; lane < (uint32_t)(ln_count); lane++)
+               if (!dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
+                       done = false;
+       return done;
+}
+
+static bool is_symbol_locked(enum dc_lane_count ln_count,
+               union lane_status *dpcd_lane_status)
+{
+       bool locked = true;
+       uint32_t lane;
+       for (lane = 0; lane < (uint32_t)(ln_count); lane++)
+               if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0)
+                       locked = false;
+       return locked;
+}
+
+static inline bool is_interlane_aligned(union lane_align_status_updated align_status)
+{
+       return align_status.bits.INTERLANE_ALIGN_DONE == 1;
 }
 
 static void update_drive_settings(
@@ -848,10 +867,9 @@ static bool perform_post_lt_adj_req_sequence(
                        if (!is_cr_done(lane_count, dpcd_lane_status))
                                return false;
 
-                       if (!is_ch_eq_done(
-                               lane_count,
-                               dpcd_lane_status,
-                               &dpcd_lane_status_updated))
+                       if (!is_ch_eq_done(lane_count, dpcd_lane_status) ||
+                                       !is_symbol_locked(lane_count, dpcd_lane_status) ||
+                                       !is_interlane_aligned(dpcd_lane_status_updated))
                                return false;
 
                        for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
@@ -1005,9 +1023,9 @@ static enum link_training_result perform_channel_equalization_sequence(
                        return LINK_TRAINING_EQ_FAIL_CR;
 
                /* 6. check CHEQ done*/
-               if (is_ch_eq_done(lane_count,
-                       dpcd_lane_status,
-                       &dpcd_lane_status_updated))
+               if (is_ch_eq_done(lane_count, dpcd_lane_status) &&
+                               is_symbol_locked(lane_count, dpcd_lane_status) &&
+                               is_interlane_aligned(dpcd_lane_status_updated))
                        return LINK_TRAINING_SUCCESS;
 
                /* 7. update VS/PE/PC2 in lt_settings*/
@@ -1569,7 +1587,6 @@ enum link_training_result dc_link_dp_perform_link_training(
 {
        enum link_training_result status = LINK_TRAINING_SUCCESS;
        struct link_training_settings lt_settings;
-       union dpcd_training_pattern dpcd_pattern = { { 0 } };
 
        bool fec_enable;
        uint8_t repeater_cnt;
@@ -1635,8 +1652,7 @@ enum link_training_result dc_link_dp_perform_link_training(
        }
 
        /* 3. set training not in progress*/
-       dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
-       dpcd_set_training_pattern(link, dpcd_pattern);
+       dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE);
        if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
                status = perform_link_training_int(link,
                                &lt_settings,

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index cc6fb83..fcfde2e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -95,6 +95,7 @@ enum dc_dp_training_pattern {
        DP_TRAINING_PATTERN_SEQUENCE_2,
        DP_TRAINING_PATTERN_SEQUENCE_3,
        DP_TRAINING_PATTERN_SEQUENCE_4,
+       DP_TRAINING_PATTERN_VIDEOIDLE,
 };
 
 struct dc_link_settings {

diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index 41a09ea..4131d00 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -36,12 +36,6 @@ enum dc_link_fec_state {
        dc_link_fec_enabled
 };
 
-enum lttpr_mode {
-       LTTPR_MODE_NON_LTTPR,
-       LTTPR_MODE_TRANSPARENT,
-       LTTPR_MODE_NON_TRANSPARENT,
-};
-
 struct dc_link_status {
        bool link_active;
        struct dpcd_caps *dpcd_caps;

diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h
index 5a250f4..73ada16 100644 (file)
--- a/drivers/gpu/drm/amd/display/include/link_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/link_service_types.h
@@ -72,6 +72,12 @@ enum link_training_result {
        LINK_TRAINING_ABORT,
 };
 
+enum lttpr_mode {
+       LTTPR_MODE_NON_LTTPR,
+       LTTPR_MODE_TRANSPARENT,
+       LTTPR_MODE_NON_TRANSPARENT,
+};
+
 struct link_training_settings {
        struct dc_link_settings link_settings;
        struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];