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drm/amdgpu: enable VCN3.0 PG and CG for navy_flounder
author
Boyuan Zhang
<boyuan.zhang@amd.com>
Wed, 1 Jul 2020 21:57:47 +0000
(17:57 -0400)
committer
Alex Deucher
<alexander.deucher@amd.com>
Wed, 15 Jul 2020 16:47:12 +0000
(12:47 -0400)
Enable VCN3.0 PG and CG for navy_flounder by setting up the flags to the ASIC
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/nv.c
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diff --git
a/drivers/gpu/drm/amd/amdgpu/nv.c
b/drivers/gpu/drm/amd/amdgpu/nv.c
index 5e03e3c59aae337163555e200bafaaac8ed03a68..13efe87c7a75eaf6ed4d3f5c15fb0753ddf0a0b1 100644
(file)
--- a/
drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/
drivers/gpu/drm/amd/amdgpu/nv.c
@@
-775,8
+775,8
@@
static int nv_common_early_init(void *handle)
adev->external_rev_id = adev->rev_id + 0x28;
break;
case CHIP_NAVY_FLOUNDER:
- adev->cg_flags =
0
;
- adev->pg_flags =
0
;
+ adev->cg_flags =
AMD_CG_SUPPORT_VCN_MGCG
;
+ adev->pg_flags =
AMD_PG_SUPPORT_VCN
;
adev->external_rev_id = adev->rev_id + 0x32;
break;