drm/i915: constify clock gating init vtable.

I used a macro to avoid making any really silly mistakes here.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/7c97f7e5ab0eae3c4cd7ce8344254356c34f3ad6.1632869550.git.jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index dd0d996972f5abc7d3c3e7c65cbe10aa0c52d92f..4e28645c73c6b35b0e63581fb8b77566b406f4ca 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -975,7 +975,7 @@ struct drm_i915_private {
        struct workqueue_struct *flip_wq;
 
        /* pm private clock gating functions */
-       struct drm_i915_clock_gating_funcs clock_gating_funcs;
+       const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
 
        /* pm display functions */
        struct drm_i915_wm_disp_funcs wm_disp;

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b37888781ec95cbfb326839b41fe1d157c941cf0..08e0195edeb7e2cec1e251b053cdf121e66fb268 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7869,7 +7869,7 @@ static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
 
 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-       dev_priv->clock_gating_funcs.init_clock_gating(dev_priv);
+       dev_priv->clock_gating_funcs->init_clock_gating(dev_priv);
 }
 
 void intel_suspend_hw(struct drm_i915_private *dev_priv)
@@ -7884,6 +7884,36 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
                    "No clock gating settings or workarounds applied.\n");
 }
 
+#define CG_FUNCS(platform)                                             \
+static const struct drm_i915_clock_gating_funcs platform##_clock_gating_funcs = { \
+       .init_clock_gating = platform##_init_clock_gating,              \
+}
+
+CG_FUNCS(adlp);
+CG_FUNCS(dg1);
+CG_FUNCS(gen12lp);
+CG_FUNCS(icl);
+CG_FUNCS(cfl);
+CG_FUNCS(skl);
+CG_FUNCS(kbl);
+CG_FUNCS(bxt);
+CG_FUNCS(glk);
+CG_FUNCS(bdw);
+CG_FUNCS(chv);
+CG_FUNCS(hsw);
+CG_FUNCS(ivb);
+CG_FUNCS(vlv);
+CG_FUNCS(gen6);
+CG_FUNCS(ilk);
+CG_FUNCS(g4x);
+CG_FUNCS(i965gm);
+CG_FUNCS(i965g);
+CG_FUNCS(gen3);
+CG_FUNCS(i85x);
+CG_FUNCS(i830);
+CG_FUNCS(nop);
+#undef CG_FUNCS
+
 /**
  * intel_init_clock_gating_hooks - setup the clock gating hooks
  * @dev_priv: device private
@@ -7896,52 +7926,52 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
        if (IS_ALDERLAKE_P(dev_priv))
-               dev_priv->clock_gating_funcs.init_clock_gating = adlp_init_clock_gating;
+               dev_priv->clock_gating_funcs = &adlp_clock_gating_funcs;
        else if (IS_DG1(dev_priv))
-               dev_priv->clock_gating_funcs.init_clock_gating = dg1_init_clock_gating;
+               dev_priv->clock_gating_funcs = &dg1_clock_gating_funcs;
        else if (GRAPHICS_VER(dev_priv) == 12)
-               dev_priv->clock_gating_funcs.init_clock_gating = gen12lp_init_clock_gating;
+               dev_priv->clock_gating_funcs = &gen12lp_clock_gating_funcs;
        else if (GRAPHICS_VER(dev_priv) == 11)
-               dev_priv->clock_gating_funcs.init_clock_gating = icl_init_clock_gating;
+               dev_priv->clock_gating_funcs = &icl_clock_gating_funcs;
        else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
-               dev_priv->clock_gating_funcs.init_clock_gating = cfl_init_clock_gating;
+               dev_priv->clock_gating_funcs = &cfl_clock_gating_funcs;
        else if (IS_SKYLAKE(dev_priv))
-               dev_priv->clock_gating_funcs.init_clock_gating = skl_init_clock_gating;
+               dev_priv->clock_gating_funcs = &skl_clock_gating_funcs;
        else if (IS_KABYLAKE(dev_priv))
-               dev_priv->clock_gating_funcs.init_clock_gating = kbl_init_clock_gating;
+               dev_priv->clock_gating_funcs = &kbl_clock_gating_funcs;
        else if (IS_BROXTON(dev_priv))
-               dev_priv->clock_gating_funcs.init_clock_gating = bxt_init_clock_gating;
+               dev_priv->clock_gating_funcs = &bxt_clock_gating_funcs;
        else if (IS_GEMINILAKE(dev_priv))
-               dev_priv->clock_gating_funcs.init_clock_gating = glk_init_clock_gating;
+               dev_priv->clock_gating_funcs = &glk_clock_gating_funcs;
        else if (IS_BROADWELL(dev_priv))
-               dev_priv->clock_gating_funcs.init_clock_gating = bdw_init_clock_gating;
+               dev_priv->clock_gating_funcs = &bdw_clock_gating_funcs;
        else if (IS_CHERRYVIEW(dev_priv))
-               dev_priv->clock_gating_funcs.init_clock_gating = chv_init_clock_gating;
+               dev_priv->clock_gating_funcs = &chv_clock_gating_funcs;
        else if (IS_HASWELL(dev_priv))
-               dev_priv->clock_gating_funcs.init_clock_gating = hsw_init_clock_gating;
+               dev_priv->clock_gating_funcs = &hsw_clock_gating_funcs;
        else if (IS_IVYBRIDGE(dev_priv))
-               dev_priv->clock_gating_funcs.init_clock_gating = ivb_init_clock_gating;
+               dev_priv->clock_gating_funcs = &ivb_clock_gating_funcs;
        else if (IS_VALLEYVIEW(dev_priv))
-               dev_priv->clock_gating_funcs.init_clock_gating = vlv_init_clock_gating;
+               dev_priv->clock_gating_funcs = &vlv_clock_gating_funcs;
        else if (GRAPHICS_VER(dev_priv) == 6)
-               dev_priv->clock_gating_funcs.init_clock_gating = gen6_init_clock_gating;
+               dev_priv->clock_gating_funcs = &gen6_clock_gating_funcs;
        else if (GRAPHICS_VER(dev_priv) == 5)
-               dev_priv->clock_gating_funcs.init_clock_gating = ilk_init_clock_gating;
+               dev_priv->clock_gating_funcs = &ilk_clock_gating_funcs;
        else if (IS_G4X(dev_priv))
-               dev_priv->clock_gating_funcs.init_clock_gating = g4x_init_clock_gating;
+               dev_priv->clock_gating_funcs = &g4x_clock_gating_funcs;
        else if (IS_I965GM(dev_priv))
-               dev_priv->clock_gating_funcs.init_clock_gating = i965gm_init_clock_gating;
+               dev_priv->clock_gating_funcs = &i965gm_clock_gating_funcs;
        else if (IS_I965G(dev_priv))
-               dev_priv->clock_gating_funcs.init_clock_gating = i965g_init_clock_gating;
+               dev_priv->clock_gating_funcs = &i965g_clock_gating_funcs;
        else if (GRAPHICS_VER(dev_priv) == 3)
-               dev_priv->clock_gating_funcs.init_clock_gating = gen3_init_clock_gating;
+               dev_priv->clock_gating_funcs = &gen3_clock_gating_funcs;
        else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
-               dev_priv->clock_gating_funcs.init_clock_gating = i85x_init_clock_gating;
+               dev_priv->clock_gating_funcs = &i85x_clock_gating_funcs;
        else if (GRAPHICS_VER(dev_priv) == 2)
-               dev_priv->clock_gating_funcs.init_clock_gating = i830_init_clock_gating;
+               dev_priv->clock_gating_funcs = &i830_clock_gating_funcs;
        else {
                MISSING_CASE(INTEL_DEVID(dev_priv));
-               dev_priv->clock_gating_funcs.init_clock_gating = nop_init_clock_gating;
+               dev_priv->clock_gating_funcs = &nop_clock_gating_funcs;
        }
 }