.getRegister(RegIdx.Index);
}
- /// Coerce the register to FGRH32 and return the real register for the current
- /// target.
- unsigned getFGRH32Reg() const {
- assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
- return RegIdx.RegInfo->getRegClass(Mips::FGRH32RegClassID)
- .getRegister(RegIdx.Index);
- }
-
/// Coerce the register to FCC and return the real register for the current
/// target.
unsigned getFCCReg() const {
"registers");
}
- void addFGRH32AsmRegOperands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::createReg(getFGRH32Reg()));
- }
-
void addFCCAsmRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createReg(getFCCReg()));
}];
}
-def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>,
- Unallocatable {
- // Do not allocate odd registers when given -mattr=+nooddspreg.
- let AltOrders = [(decimate FGRH32, 2)];
- let AltOrderSelect = [{
- const auto & S = MF.getSubtarget<MipsSubtarget>();
- return S.isABI_O32() && !S.useOddSPReg();
- }];
-}
-
def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
// Return Values and Arguments
D0, D1,
let PredicateMethod = "isStrictlyFGRAsmReg";
}
-def FGRH32AsmOperand : MipsAsmRegOperand {
- let Name = "FGRH32AsmReg";
- let PredicateMethod = "isFGRAsmReg";
-}
-
def FCCRegsAsmOperand : MipsAsmRegOperand {
let Name = "FCCAsmReg";
}
let ParserMatchClass = FGR32AsmOperand;
}
-def FGRH32Opnd : RegisterOperand<FGRH32> {
- let ParserMatchClass = FGRH32AsmOperand;
-}
-
def FCCRegsOpnd : RegisterOperand<FCC> {
let ParserMatchClass = FCCRegsAsmOperand;
}