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xtensa: rename MISC SR definition to avoid name clashes
authorMax Filippov <jcmvbkbc@gmail.com>
Mon, 17 Sep 2012 01:44:54 +0000 (05:44 +0400)
committerChris Zankel <chris@zankel.net>
Wed, 3 Oct 2012 22:12:43 +0000 (15:12 -0700)
There are other special register that cause build warnings and may as
well need renaming as well.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
arch/xtensa/include/asm/regs.h patch | blob | history

diff --git a/arch/xtensa/include/asm/regs.h b/arch/xtensa/include/asm/regs.h
index d4baed2..a3075b1 100644 (file)
--- a/arch/xtensa/include/asm/regs.h
+++ b/arch/xtensa/include/asm/regs.h
@@ -66,7 +66,7 @@
 #define ICOUNTLEVEL    237
 #define EXCVADDR       238
 #define CCOMPARE       240
-#define MISC           244
+#define MISC_SR                244
 
 /*  Special names for read-only and write-only interrupt registers.  */
 
Domain: System / Uncategorized;